1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * From Coreboot soc/intel/broadwell/include/soc/iomap.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Google Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: BSD-3-Clause 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __asm_arch_iomap_h 10*4882a593Smuzhiyun #define __asm_arch_iomap_h 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MCFG_BASE_ADDRESS 0xf0000000 13*4882a593Smuzhiyun #define MCFG_BASE_SIZE 0x4000000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define HPET_BASE_ADDRESS 0xfed00000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MCH_BASE_ADDRESS 0xfed10000 18*4882a593Smuzhiyun #define MCH_BASE_SIZE 0x8000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define DMI_BASE_ADDRESS 0xfed18000 21*4882a593Smuzhiyun #define DMI_BASE_SIZE 0x1000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define EP_BASE_ADDRESS 0xfed19000 24*4882a593Smuzhiyun #define EP_BASE_SIZE 0x1000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define EDRAM_BASE_ADDRESS 0xfed80000 27*4882a593Smuzhiyun #define EDRAM_BASE_SIZE 0x4000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define GDXC_BASE_ADDRESS 0xfed84000 30*4882a593Smuzhiyun #define GDXC_BASE_SIZE 0x1000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define RCBA_BASE_ADDRESS 0xfed1c000 33*4882a593Smuzhiyun #define RCBA_BASE_SIZE 0x4000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define HPET_BASE_ADDRESS 0xfed00000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define ACPI_BASE_ADDRESS 0x1000 38*4882a593Smuzhiyun #define ACPI_BASE_SIZE 0x100 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define GPIO_BASE_ADDRESS 0x1400 41*4882a593Smuzhiyun #define GPIO_BASE_SIZE 0x400 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define SMBUS_BASE_ADDRESS 0x0400 44*4882a593Smuzhiyun #define SMBUS_BASE_SIZE 0x10 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Temporary addresses used before relocation */ 47*4882a593Smuzhiyun #define EARLY_GTT_BAR 0xe0000000 48*4882a593Smuzhiyun #define EARLY_XHCI_BAR 0xd7000000 49*4882a593Smuzhiyun #define EARLY_EHCI_BAR 0xd8000000 50*4882a593Smuzhiyun #define EARLY_UART_BAR 0x3f8 51*4882a593Smuzhiyun #define EARLY_TEMP_MMIO 0xfed08000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif 54