1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * hardware_am33xx.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * AM33xx hardware specific header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __AM33XX_HARDWARE_AM33XX_H 12*4882a593Smuzhiyun #define __AM33XX_HARDWARE_AM33XX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Module base addresses */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* UART Base Address */ 17*4882a593Smuzhiyun #define UART0_BASE 0x44E09000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* GPIO Base address */ 20*4882a593Smuzhiyun #define GPIO2_BASE 0x481AC000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Watchdog Timer */ 23*4882a593Smuzhiyun #define WDT_BASE 0x44E35000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Control Module Base Address */ 26*4882a593Smuzhiyun #define CTRL_BASE 0x44E10000 27*4882a593Smuzhiyun #define CTRL_DEVICE_BASE 0x44E10600 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* PRCM Base Address */ 30*4882a593Smuzhiyun #define PRCM_BASE 0x44E00000 31*4882a593Smuzhiyun #define CM_PER 0x44E00000 32*4882a593Smuzhiyun #define CM_WKUP 0x44E00400 33*4882a593Smuzhiyun #define CM_DPLL 0x44E00500 34*4882a593Smuzhiyun #define CM_RTC 0x44E00800 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) 37*4882a593Smuzhiyun #define PRM_RSTST (PRM_RSTCTRL + 8) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* VTP Base address */ 40*4882a593Smuzhiyun #define VTP0_CTRL_ADDR 0x44E10E0C 41*4882a593Smuzhiyun #define VTP1_CTRL_ADDR 0x48140E10 42*4882a593Smuzhiyun #define PRM_DEVICE_INST 0x44E00F00 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* DDR Base address */ 45*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR 0x44E12000 46*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR 0x44E120C8 47*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR2 0x47C0C800 48*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 49*4882a593Smuzhiyun #define DDR_DATA_REGS_NR 2 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) 52*4882a593Smuzhiyun #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* CPSW Config space */ 55*4882a593Smuzhiyun #define CPSW_MDIO_BASE 0x4A101000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* RTC base address */ 58*4882a593Smuzhiyun #define RTC_BASE 0x44E3E000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* OTG */ 61*4882a593Smuzhiyun #define USB0_OTG_BASE 0x47401000 62*4882a593Smuzhiyun #define USB1_OTG_BASE 0x47401800 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* LCD Controller */ 65*4882a593Smuzhiyun #define LCD_CNTL_BASE 0x4830E000 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* PWMSS */ 68*4882a593Smuzhiyun #define PWMSS0_BASE 0x48300000 69*4882a593Smuzhiyun #define AM33XX_ECAP0_BASE 0x48300100 70*4882a593Smuzhiyun #define AM33XX_EPWM_BASE 0x48300200 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __AM33XX_HARDWARE_AM33XX_H */ 73