Home
last modified time | relevance | path

Searched +full:0 +full:x10010000 (Results 1 – 25 of 63) sorted by relevance

123

/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h11 #define DEVICE_NOT_AVAILABLE 0
14 #define EXYNOS4_ADDR_BASE 0x10000000
17 #define EXYNOS4_I2C_SPACING 0x10000
19 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
20 #define EXYNOS4_PRO_ID 0x10000000
21 #define EXYNOS4_SYSREG_BASE 0x10010000
22 #define EXYNOS4_POWER_BASE 0x10020000
23 #define EXYNOS4_SWRESET 0x10020400
24 #define EXYNOS4_CLOCK_BASE 0x10030000
25 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dexynos5250-clock.txt27 reg = <0x10010000 0x30000>;
37 reg = <0x13820000 0x100>;
38 interrupts = <0 54 0>;
H A Dexynos5420-clock.txt28 reg = <0x10010000 0x30000>;
38 reg = <0x13820000 0x100>;
39 interrupts = <0 54 0>;
H A Dexynos5410-clock.txt30 #clock-cells = <0>;
35 reg = <0x10010000 0x30000>;
46 reg = <0x12C00000 0x100>;
47 interrupts = <0 51 0>;
/OK3568_Linux_fs/u-boot/include/configs/
H A Dstm32f429-discovery.h15 #define CONFIG_SYS_FLASH_BASE 0x08000000
17 #define CONFIG_SYS_INIT_SP_ADDR 0x10010000
18 #define CONFIG_SYS_TEXT_BASE 0x08000000
30 #define CONFIG_SYS_RAM_BASE 0xD0000000
32 #define CONFIG_SYS_LOAD_ADDR 0xD0400000
33 #define CONFIG_LOADADDR 0xD0400000
68 "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
70 "bootm 0x08044000 - 0x08042000\0"
H A Dmx6qarm2.h28 #define CONFIG_FEC_MXC_PHYADDR 0
31 "script=boot.scr\0" \
32 "image=zImage\0" \
33 "console=ttymxc3\0" \
34 "fdt_file=imx6q-arm2.dtb\0" \
35 "fdt_addr=0x18000000\0" \
36 "fdt_high=0xffffffff\0" \
37 "initrd_high=0xffffffff\0" \
38 "boot_fdt=try\0" \
39 "ip_dyn=yes\0" \
[all …]
H A Dembestmx6boards.h40 #define CONFIG_MXC_USB_FLAGS 0
43 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
56 #define CONFIG_SF_DEFAULT_BUS 0
57 #define CONFIG_SF_DEFAULT_CS 0
64 #define CONFIG_SYS_MEMTEST_START 0x10000000
65 #define CONFIG_SYS_MEMTEST_END 0x10010000
66 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
121 "bootm_size=0x10000000\0" \
122 "kernel_addr_r=0x12000000\0" \
123 "fdt_addr_r=0x13000000\0" \
[all …]
H A Dimx6_logic.h24 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
32 #define CONFIG_FEC_MXC_PHYADDR 0
38 "script=boot.scr\0" \
39 "image=zImage\0" \
40 "bootm_size=0x10000000\0" \
41 "fdt_addr_r=0x18000000\0" \
42 "fdt_addr=0x18000000\0" \
43 "ramdisk_addr_r=0x13000000\0" \
44 "ramdiskaddr=0x13000000\0" \
45 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
[all …]
H A Dmx6sabre_common.h22 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #define CONFIG_SF_DEFAULT_BUS 0
36 #define CONFIG_SF_DEFAULT_CS 0
43 "emmcdev=2\0" \
52 "setexpr fw_sz ${filesize} / 0x200; " \
54 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
56 "fi\0"
64 "script=boot.scr\0" \
65 "image=zImage\0" \
66 "fdt_file=undefined\0" \
[all …]
H A Dcm_fx6.h29 #define CONFIG_SYS_MEMTEST_START 0x10000000
30 #define CONFIG_SYS_MEMTEST_END 0x10010000
44 #define CONFIG_SF_DEFAULT_BUS 0
45 #define CONFIG_SF_DEFAULT_CS 0
54 #define MTDIDS_DEFAULT "nor0=spi0.0"
55 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \
70 "stdin=serial,usbkbd\0" \
71 "stdout=serial,vga\0" \
72 "stderr=serial,vga\0" \
73 "panel=HDMI\0" \
[all …]
H A Dcgtqmx6eval.h35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
41 #define CONFIG_SF_DEFAULT_BUS 0
60 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
65 #define CONFIG_MXC_USB_FLAGS 0
90 #define CONFIG_DWC_AHSATA_PORT_ID 0
109 #define CONFIG_SYS_MMC_ENV_DEV 0
113 "script=boot.scr\0" \
114 "image=zImage\0" \
115 "fdtfile=undefined\0" \
116 "fdt_addr_r=0x18000000\0" \
[all …]
H A Dadvantech_dms-ba16.h44 #define CONFIG_DWC_AHSATA_PORT_ID 0
52 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
59 #define CONFIG_MXC_USB_FLAGS 0
76 #define CONFIG_SF_DEFAULT_BUS 0
77 #define CONFIG_SF_DEFAULT_CS 0
86 #define CONFIG_LOADADDR 0x12000000
87 #define CONFIG_SYS_TEXT_BASE 0x17800000
90 "script=boot.scr\0" \
91 "image=" CONFIG_BOOT_DIR "/uImage\0" \
92 "uboot=u-boot.imx\0" \
[all …]
H A Dnitrogen6x.h29 #define CONFIG_SF_DEFAULT_BUS 0
30 #define CONFIG_SF_DEFAULT_CS 0
45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
54 #define CONFIG_DWC_AHSATA_PORT_ID 0
71 #define CONFIG_MXC_USB_FLAGS 0
110 "script=boot.scr\0" \
111 "uimage=uImage\0" \
112 "console=ttymxc1\0" \
113 "fdt_high=0xffffffff\0" \
114 "initrd_high=0xffffffff\0" \
[all …]
H A Dge_bx50v3.h56 #define CONFIG_DWC_AHSATA_PORT_ID 0
65 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_MXC_USB_FLAGS 0
94 #define CONFIG_SF_DEFAULT_BUS 0
95 #define CONFIG_SF_DEFAULT_CS 0
104 #define CONFIG_LOADADDR 0x12000000
105 #define CONFIG_SYS_TEXT_BASE 0x17800000
108 "script=boot.scr\0" \
109 "image=/boot/uImage\0" \
110 "uboot=u-boot.imx\0" \
[all …]
H A Dcolibri_imx6.h24 #define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
62 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
84 #define CONFIG_MXC_USB_FLAGS 0
127 #define CONFIG_LOADADDR 0x12000000
128 #define CONFIG_SYS_TEXT_BASE 0x17800000
139 "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
140 "boot part 0 1;" \
141 "rootfs part 0 2;" \
142 "uImage fat 0 1;" \
143 "imx6q-colibri-eval-v3.dtb fat 0 1;" \
[all …]
H A Dapalis_imx6.h26 #define CONFIG_SPL_PAD_TO 0x11000 /* 4k IVT/DCD, 64k SPL */
64 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
76 #define CONFIG_DWC_AHSATA_PORT_ID 0
98 #define CONFIG_MXC_USB_FLAGS 0
141 #define CONFIG_LOADADDR 0x12000000
142 #define CONFIG_SYS_TEXT_BASE 0x17800000
159 "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
160 "boot part 0 1;" \
161 "rootfs part 0 2;" \
162 "uImage fat 0 1;" \
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
15 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
16 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
17 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
18 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
19 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml58 reg = <0x10010000 0x1000>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h10 #define OCRAM_BASE_ADDR 0x10000000
11 #define OCRAM_SIZE 0x00010000
12 #define OCRAM_BASE_S_ADDR 0x10010000
13 #define OCRAM_S_SIZE 0x00010000
15 #define CONFIG_SYS_IMMR 0x01000000
16 #define CONFIG_SYS_DCSRBAR 0x20000000
18 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
19 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
21 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
22 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
30 pattern: "^pinctrl@[0-9a-f]+$"
57 const: 0
60 "^gpio@[0-9]$":
157 reg = <0x10010000 0x600>;
160 #size-cells = <0>;
162 gpio@0 {
164 reg = <0>;
167 gpio-ranges = <&pinctrl 0 0 32>;
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_psd_8852b.c28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/halrf_8852b/
H A Dhalrf_psd_8852b.c28 for (i = 0; i < reg_num; i++) { in _halrf_psd_backup_bb_registers_8852b()
31 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Backup BB 0x%08x = 0x%08x\n", in _halrf_psd_backup_bb_registers_8852b()
46 for (i = 0; i < reg_num; i++) { in _halrf_psd_reload_bb_registers_8852b()
49 RF_DBG(rf, DBG_RF_PSD, "[TXGAPK] Reload BB 0x%08x = 0x%08x\n", in _halrf_psd_reload_bb_registers_8852b()
59 0x20fc, 0x5864, 0x7864, 0x12b8, 0x32b8, in halrf_psd_init_8852b()
60 0x030c, 0x032c, 0x58c8, 0x78c8, 0x2008, in halrf_psd_init_8852b()
61 0x0c1c, 0x0700, 0x0c70, 0x0c60, 0x0c6c, in halrf_psd_init_8852b()
62 0x58ac, 0x78ac, 0x0c3c, 0x2320, 0x4490, in halrf_psd_init_8852b()
63 0x12a0, 0x32a0, 0x8008, 0x8080, 0x8088, in halrf_psd_init_8852b()
64 0x80d0, 0x8074, 0x81dc, 0x82dc, 0x8120, in halrf_psd_init_8852b()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
66 reg = <0x10002000 0x1000>;
[all …]
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]

123