1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014, Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARMV7_LS102XA_CONFIG_ 8*4882a593Smuzhiyun #define _ASM_ARMV7_LS102XA_CONFIG_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define OCRAM_BASE_ADDR 0x10000000 11*4882a593Smuzhiyun #define OCRAM_SIZE 0x00010000 12*4882a593Smuzhiyun #define OCRAM_BASE_S_ADDR 0x10010000 13*4882a593Smuzhiyun #define OCRAM_S_SIZE 0x00010000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_SYS_IMMR 0x01000000 16*4882a593Smuzhiyun #define CONFIG_SYS_DCSRBAR 0x20000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 19*4882a593Smuzhiyun #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) 22*4882a593Smuzhiyun #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 23*4882a593Smuzhiyun #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 24*4882a593Smuzhiyun #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 25*4882a593Smuzhiyun #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 26*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 27*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 28*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 29*4882a593Smuzhiyun #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 30*4882a593Smuzhiyun #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 31*4882a593Smuzhiyun #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 32*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 33*4882a593Smuzhiyun #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 34*4882a593Smuzhiyun #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 35*4882a593Smuzhiyun #define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) 36*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 37*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 38*4882a593Smuzhiyun #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) 39*4882a593Smuzhiyun #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 40*4882a593Smuzhiyun #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 43*4882a593Smuzhiyun #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 44*4882a593Smuzhiyun #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 45*4882a593Smuzhiyun #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 46*4882a593Smuzhiyun #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 47*4882a593Smuzhiyun #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 50*4882a593Smuzhiyun #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 55*4882a593Smuzhiyun #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 56*4882a593Smuzhiyun #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 61*4882a593Smuzhiyun #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 66*4882a593Smuzhiyun #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL 69*4882a593Smuzhiyun #define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL 70*4882a593Smuzhiyun #define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL 71*4882a593Smuzhiyun #define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL 72*4882a593Smuzhiyun #define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) 75*4882a593Smuzhiyun * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ 78*4882a593Smuzhiyun CONFIG_SYS_PCIE1_VIRT_ADDR) 79*4882a593Smuzhiyun #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ 80*4882a593Smuzhiyun CONFIG_SYS_PCIE2_VIRT_ADDR) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* SATA */ 83*4882a593Smuzhiyun #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 84*4882a593Smuzhiyun #define CONFIG_LIBATA 85*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI 86*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI_PLAT 87*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 88*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_LUN 1 89*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 90*4882a593Smuzhiyun CONFIG_SYS_SCSI_MAX_LUN) 91*4882a593Smuzhiyun #ifdef CONFIG_DDR_SPD 92*4882a593Smuzhiyun #define CONFIG_VERY_BIG_RAM 93*4882a593Smuzhiyun #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 94*4882a593Smuzhiyun #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CONFIG_SYS_FSL_IFC_BE 98*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_BE 99*4882a593Smuzhiyun #define CONFIG_SYS_FSL_WDOG_BE 100*4882a593Smuzhiyun #define CONFIG_SYS_FSL_DSPI_BE 101*4882a593Smuzhiyun #define CONFIG_SYS_FSL_QSPI_BE 102*4882a593Smuzhiyun #define CONFIG_SYS_FSL_DCU_BE 103*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SEC_MON_LE 104*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SFP_VER_3_2 105*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SFP_BE 106*4882a593Smuzhiyun #define CONFIG_SYS_FSL_SRK_LE 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define DCU_LAYER_MAX_NUM 16 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #ifdef CONFIG_ARCH_LS1021A 111*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 112*4882a593Smuzhiyun #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 113*4882a593Smuzhiyun #else 114*4882a593Smuzhiyun #error SoC not defined 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define FSL_IFC_COMPAT "fsl,ifc" 118*4882a593Smuzhiyun #define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" 119*4882a593Smuzhiyun #define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 122