1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include <dt-bindings/clock/ingenic,tcu.h> 3*4882a593Smuzhiyun#include <dt-bindings/clock/x1830-cgu.h> 4*4882a593Smuzhiyun#include <dt-bindings/dma/x1830-dma.h> 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun #address-cells = <1>; 8*4882a593Smuzhiyun #size-cells = <1>; 9*4882a593Smuzhiyun compatible = "ingenic,x1830"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun cpus { 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <0>; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpu0: cpu@0 { 16*4882a593Smuzhiyun device_type = "cpu"; 17*4882a593Smuzhiyun compatible = "ingenic,xburst-fpu2.0-mxu2.0"; 18*4882a593Smuzhiyun reg = <0>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_CPU>; 21*4882a593Smuzhiyun clock-names = "cpu"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpuintc: interrupt-controller { 26*4882a593Smuzhiyun #address-cells = <0>; 27*4882a593Smuzhiyun #interrupt-cells = <1>; 28*4882a593Smuzhiyun interrupt-controller; 29*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun intc: interrupt-controller@10001000 { 33*4882a593Smuzhiyun compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc"; 34*4882a593Smuzhiyun reg = <0x10001000 0x50>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #interrupt-cells = <1>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 40*4882a593Smuzhiyun interrupts = <2>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun exclk: ext { 44*4882a593Smuzhiyun compatible = "fixed-clock"; 45*4882a593Smuzhiyun #clock-cells = <0>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun rtclk: rtc { 49*4882a593Smuzhiyun compatible = "fixed-clock"; 50*4882a593Smuzhiyun #clock-cells = <0>; 51*4882a593Smuzhiyun clock-frequency = <32768>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun cgu: x1830-cgu@10000000 { 55*4882a593Smuzhiyun compatible = "ingenic,x1830-cgu"; 56*4882a593Smuzhiyun reg = <0x10000000 0x100>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #clock-cells = <1>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun clocks = <&exclk>, <&rtclk>; 61*4882a593Smuzhiyun clock-names = "ext", "rtc"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun tcu: timer@10002000 { 65*4882a593Smuzhiyun compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd"; 66*4882a593Smuzhiyun reg = <0x10002000 0x1000>; 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <1>; 69*4882a593Smuzhiyun ranges = <0x0 0x10002000 0x1000>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #clock-cells = <1>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_RTCLK 74*4882a593Smuzhiyun &cgu X1830_CLK_EXCLK 75*4882a593Smuzhiyun &cgu X1830_CLK_PCLK>; 76*4882a593Smuzhiyun clock-names = "rtc", "ext", "pclk"; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun interrupt-controller; 79*4882a593Smuzhiyun #interrupt-cells = <1>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun interrupt-parent = <&intc>; 82*4882a593Smuzhiyun interrupts = <27 26 25>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun wdt: watchdog@0 { 85*4882a593Smuzhiyun compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog"; 86*4882a593Smuzhiyun reg = <0x0 0x10>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun clocks = <&tcu TCU_CLK_WDT>; 89*4882a593Smuzhiyun clock-names = "wdt"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun rtc: rtc@10003000 { 94*4882a593Smuzhiyun compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc"; 95*4882a593Smuzhiyun reg = <0x10003000 0x4c>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun interrupt-parent = <&intc>; 98*4882a593Smuzhiyun interrupts = <32>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_RTCLK>; 101*4882a593Smuzhiyun clock-names = "rtc"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun pinctrl: pin-controller@10010000 { 105*4882a593Smuzhiyun compatible = "ingenic,x1830-pinctrl"; 106*4882a593Smuzhiyun reg = <0x10010000 0x800>; 107*4882a593Smuzhiyun #address-cells = <1>; 108*4882a593Smuzhiyun #size-cells = <0>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun gpa: gpio@0 { 111*4882a593Smuzhiyun compatible = "ingenic,x1830-gpio"; 112*4882a593Smuzhiyun reg = <0>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun gpio-controller; 115*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 32>; 116*4882a593Smuzhiyun #gpio-cells = <2>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun interrupt-controller; 119*4882a593Smuzhiyun #interrupt-cells = <2>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun interrupt-parent = <&intc>; 122*4882a593Smuzhiyun interrupts = <17>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun gpb: gpio@1 { 126*4882a593Smuzhiyun compatible = "ingenic,x1830-gpio"; 127*4882a593Smuzhiyun reg = <1>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun gpio-controller; 130*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 32 32>; 131*4882a593Smuzhiyun #gpio-cells = <2>; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun interrupt-controller; 134*4882a593Smuzhiyun #interrupt-cells = <2>; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun interrupt-parent = <&intc>; 137*4882a593Smuzhiyun interrupts = <16>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun gpc: gpio@2 { 141*4882a593Smuzhiyun compatible = "ingenic,x1830-gpio"; 142*4882a593Smuzhiyun reg = <2>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun gpio-controller; 145*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 64 32>; 146*4882a593Smuzhiyun #gpio-cells = <2>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun interrupt-controller; 149*4882a593Smuzhiyun #interrupt-cells = <2>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun interrupt-parent = <&intc>; 152*4882a593Smuzhiyun interrupts = <15>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun gpd: gpio@3 { 156*4882a593Smuzhiyun compatible = "ingenic,x1830-gpio"; 157*4882a593Smuzhiyun reg = <3>; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun gpio-controller; 160*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 96 32>; 161*4882a593Smuzhiyun #gpio-cells = <2>; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun interrupt-controller; 164*4882a593Smuzhiyun #interrupt-cells = <2>; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun interrupt-parent = <&intc>; 167*4882a593Smuzhiyun interrupts = <14>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun uart0: serial@10030000 { 172*4882a593Smuzhiyun compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 173*4882a593Smuzhiyun reg = <0x10030000 0x100>; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun interrupt-parent = <&intc>; 176*4882a593Smuzhiyun interrupts = <51>; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun clocks = <&exclk>, <&cgu X1830_CLK_UART0>; 179*4882a593Smuzhiyun clock-names = "baud", "module"; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun status = "disabled"; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun uart1: serial@10031000 { 185*4882a593Smuzhiyun compatible = "ingenic,x1830-uart", "ingenic,x1000-uart"; 186*4882a593Smuzhiyun reg = <0x10031000 0x100>; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun interrupt-parent = <&intc>; 189*4882a593Smuzhiyun interrupts = <50>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun clocks = <&exclk>, <&cgu X1830_CLK_UART1>; 192*4882a593Smuzhiyun clock-names = "baud", "module"; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun status = "disabled"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun i2c0: i2c-controller@10050000 { 198*4882a593Smuzhiyun compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 199*4882a593Smuzhiyun reg = <0x10050000 0x1000>; 200*4882a593Smuzhiyun #address-cells = <1>; 201*4882a593Smuzhiyun #size-cells = <0>; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun interrupt-parent = <&intc>; 204*4882a593Smuzhiyun interrupts = <60>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_SMB0>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun status = "disabled"; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun i2c1: i2c-controller@10051000 { 212*4882a593Smuzhiyun compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 213*4882a593Smuzhiyun reg = <0x10051000 0x1000>; 214*4882a593Smuzhiyun #address-cells = <1>; 215*4882a593Smuzhiyun #size-cells = <0>; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun interrupt-parent = <&intc>; 218*4882a593Smuzhiyun interrupts = <59>; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_SMB1>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun status = "disabled"; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun i2c2: i2c-controller@10052000 { 226*4882a593Smuzhiyun compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c"; 227*4882a593Smuzhiyun reg = <0x10052000 0x1000>; 228*4882a593Smuzhiyun #address-cells = <1>; 229*4882a593Smuzhiyun #size-cells = <0>; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun interrupt-parent = <&intc>; 232*4882a593Smuzhiyun interrupts = <58>; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_SMB2>; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun status = "disabled"; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun pdma: dma-controller@13420000 { 240*4882a593Smuzhiyun compatible = "ingenic,x1830-dma"; 241*4882a593Smuzhiyun reg = <0x13420000 0x400 242*4882a593Smuzhiyun 0x13421000 0x40>; 243*4882a593Smuzhiyun #dma-cells = <2>; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun interrupt-parent = <&intc>; 246*4882a593Smuzhiyun interrupts = <10>; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_PDMA>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun msc0: mmc@13450000 { 252*4882a593Smuzhiyun compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 253*4882a593Smuzhiyun reg = <0x13450000 0x1000>; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun interrupt-parent = <&intc>; 256*4882a593Smuzhiyun interrupts = <37>; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_MSC0>; 259*4882a593Smuzhiyun clock-names = "mmc"; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun cap-sd-highspeed; 262*4882a593Smuzhiyun cap-mmc-highspeed; 263*4882a593Smuzhiyun cap-sdio-irq; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>, 266*4882a593Smuzhiyun <&pdma X1830_DMA_MSC0_TX 0xffffffff>; 267*4882a593Smuzhiyun dma-names = "rx", "tx"; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun status = "disabled"; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun msc1: mmc@13460000 { 273*4882a593Smuzhiyun compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc"; 274*4882a593Smuzhiyun reg = <0x13460000 0x1000>; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun interrupt-parent = <&intc>; 277*4882a593Smuzhiyun interrupts = <36>; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_MSC1>; 280*4882a593Smuzhiyun clock-names = "mmc"; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun cap-sd-highspeed; 283*4882a593Smuzhiyun cap-mmc-highspeed; 284*4882a593Smuzhiyun cap-sdio-irq; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>, 287*4882a593Smuzhiyun <&pdma X1830_DMA_MSC1_TX 0xffffffff>; 288*4882a593Smuzhiyun dma-names = "rx", "tx"; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun status = "disabled"; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun mac: ethernet@134b0000 { 294*4882a593Smuzhiyun compatible = "ingenic,x1830-mac", "snps,dwmac"; 295*4882a593Smuzhiyun reg = <0x134b0000 0x2000>; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun interrupt-parent = <&intc>; 298*4882a593Smuzhiyun interrupts = <55>; 299*4882a593Smuzhiyun interrupt-names = "macirq"; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun clocks = <&cgu X1830_CLK_MAC>; 302*4882a593Smuzhiyun clock-names = "stmmaceth"; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun status = "disabled"; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun mdio: mdio { 307*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 308*4882a593Smuzhiyun #address-cells = <1>; 309*4882a593Smuzhiyun #size-cells = <0>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun status = "disabled"; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun}; 315