1*4882a593Smuzhiyun* Samsung Exynos5410 Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Exynos5410 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the Exynos5410 SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be "samsung,exynos5410-clock" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 11*4882a593Smuzhiyun region. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- #clock-cells: should be 1. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- clocks: should contain an entry specifying the root clock from external 16*4882a593Smuzhiyun oscillator supplied through XXTI or XusbXTI pin. This clock should be 17*4882a593Smuzhiyun defined using standard clock bindings with "fin_pll" clock-output-name. 18*4882a593Smuzhiyun That clock is being passed internally to the 9 PLLs. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunAll available clocks are defined as preprocessor macros in 21*4882a593Smuzhiyundt-bindings/clock/exynos5410.h header and can be used in device 22*4882a593Smuzhiyuntree sources. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample 1: An example of a clock controller node is listed below. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun fin_pll: xxti { 27*4882a593Smuzhiyun compatible = "fixed-clock"; 28*4882a593Smuzhiyun clock-frequency = <24000000>; 29*4882a593Smuzhiyun clock-output-names = "fin_pll"; 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clock: clock-controller@10010000 { 34*4882a593Smuzhiyun compatible = "samsung,exynos5410-clock"; 35*4882a593Smuzhiyun reg = <0x10010000 0x30000>; 36*4882a593Smuzhiyun #clock-cells = <1>; 37*4882a593Smuzhiyun clocks = <&fin_pll>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample 2: UART controller node that consumes the clock generated by the clock 41*4882a593Smuzhiyun controller. Refer to the standard clock bindings for information 42*4882a593Smuzhiyun about 'clocks' and 'clock-names' property. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun serial@12c20000 { 45*4882a593Smuzhiyun compatible = "samsung,exynos4210-uart"; 46*4882a593Smuzhiyun reg = <0x12C00000 0x100>; 47*4882a593Smuzhiyun interrupts = <0 51 0>; 48*4882a593Smuzhiyun clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 49*4882a593Smuzhiyun clock-names = "uart", "clk_uart_baud0"; 50*4882a593Smuzhiyun }; 51