1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Config file for Compulab CM-FX6 board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Nikita Kiryanov <nikita@compulab.co.il> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CONFIG_CM_FX6_H 12*4882a593Smuzhiyun #define __CONFIG_CM_FX6_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "mx6_common.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Machine config */ 17*4882a593Smuzhiyun #define CONFIG_SYS_LITTLE_ENDIAN 18*4882a593Smuzhiyun #define CONFIG_MACH_TYPE 4273 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* MMC */ 21*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM 3 22*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* RAM */ 25*4882a593Smuzhiyun #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR 26*4882a593Smuzhiyun #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR 27*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 28*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 29*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x10000000 30*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x10010000 31*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 32*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 33*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 34*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 35*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 36*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Serial console */ 39*4882a593Smuzhiyun #define CONFIG_MXC_UART 40*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART4_BASE 41*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* SPI flash */ 44*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_BUS 0 45*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_CS 0 46*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 25000000 47*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* MTD support */ 50*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 51*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_MTD 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define MTDIDS_DEFAULT "nor0=spi0.0" 55*4882a593Smuzhiyun #define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \ 56*4882a593Smuzhiyun "768k(uboot)," \ 57*4882a593Smuzhiyun "256k(uboot-environment)," \ 58*4882a593Smuzhiyun "-(reserved)" 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Environment */ 61*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 62*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 63*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 64*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 65*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 66*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (8 * 1024) 67*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (768 * 1024) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 70*4882a593Smuzhiyun "stdin=serial,usbkbd\0" \ 71*4882a593Smuzhiyun "stdout=serial,vga\0" \ 72*4882a593Smuzhiyun "stderr=serial,vga\0" \ 73*4882a593Smuzhiyun "panel=HDMI\0" \ 74*4882a593Smuzhiyun "autoload=no\0" \ 75*4882a593Smuzhiyun "uImage=uImage-cm-fx6\0" \ 76*4882a593Smuzhiyun "zImage=zImage-cm-fx6\0" \ 77*4882a593Smuzhiyun "kernel=uImage-cm-fx6\0" \ 78*4882a593Smuzhiyun "script=boot.scr\0" \ 79*4882a593Smuzhiyun "dtb=cm-fx6.dtb\0" \ 80*4882a593Smuzhiyun "bootm_low=18000000\0" \ 81*4882a593Smuzhiyun "loadaddr=0x10800000\0" \ 82*4882a593Smuzhiyun "fdtaddr=0x11000000\0" \ 83*4882a593Smuzhiyun "console=ttymxc3,115200\0" \ 84*4882a593Smuzhiyun "ethprime=FEC0\0" \ 85*4882a593Smuzhiyun "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ 86*4882a593Smuzhiyun "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ 87*4882a593Smuzhiyun "doboot=bootm ${loadaddr}\0" \ 88*4882a593Smuzhiyun "doloadfdt=false\0" \ 89*4882a593Smuzhiyun "mtdids=" MTDIDS_DEFAULT "\0" \ 90*4882a593Smuzhiyun "mtdparts=" MTDPARTS_DEFAULT "\0" \ 91*4882a593Smuzhiyun "setboottypez=setenv kernel ${zImage};" \ 92*4882a593Smuzhiyun "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ 93*4882a593Smuzhiyun "setenv doloadfdt true;\0" \ 94*4882a593Smuzhiyun "setboottypem=setenv kernel ${uImage};" \ 95*4882a593Smuzhiyun "setenv doboot bootm ${loadaddr};" \ 96*4882a593Smuzhiyun "setenv doloadfdt false;\0"\ 97*4882a593Smuzhiyun "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 98*4882a593Smuzhiyun "sataroot=/dev/sda2 rw rootwait\0" \ 99*4882a593Smuzhiyun "nandroot=/dev/mtdblock4 rw\0" \ 100*4882a593Smuzhiyun "nandrootfstype=ubifs\0" \ 101*4882a593Smuzhiyun "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ 102*4882a593Smuzhiyun "${video} ${extrabootargs}\0" \ 103*4882a593Smuzhiyun "sataargs=setenv bootargs console=${console} root=${sataroot} " \ 104*4882a593Smuzhiyun "${video} ${extrabootargs}\0" \ 105*4882a593Smuzhiyun "nandargs=setenv bootargs console=${console} " \ 106*4882a593Smuzhiyun "root=${nandroot} " \ 107*4882a593Smuzhiyun "rootfstype=${nandrootfstype} " \ 108*4882a593Smuzhiyun "${video} ${extrabootargs}\0" \ 109*4882a593Smuzhiyun "nandboot=if run nandloadkernel; then " \ 110*4882a593Smuzhiyun "run nandloadfdt;" \ 111*4882a593Smuzhiyun "run setboottypem;" \ 112*4882a593Smuzhiyun "run storagebootcmd;" \ 113*4882a593Smuzhiyun "run setboottypez;" \ 114*4882a593Smuzhiyun "run storagebootcmd;" \ 115*4882a593Smuzhiyun "fi;\0" \ 116*4882a593Smuzhiyun "run_eboot=echo Starting EBOOT ...; "\ 117*4882a593Smuzhiyun "mmc dev 2 && " \ 118*4882a593Smuzhiyun "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ 119*4882a593Smuzhiyun "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ 120*4882a593Smuzhiyun "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ 121*4882a593Smuzhiyun "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ 122*4882a593Smuzhiyun "bootscript=echo Running bootscript from ${storagetype} ...;" \ 123*4882a593Smuzhiyun "source ${loadaddr};\0" \ 124*4882a593Smuzhiyun "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ 125*4882a593Smuzhiyun "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ 126*4882a593Smuzhiyun "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ 127*4882a593Smuzhiyun "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ 128*4882a593Smuzhiyun "setupnandboot=setenv storagetype nand;\0" \ 129*4882a593Smuzhiyun "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ 130*4882a593Smuzhiyun "storagebootcmd=echo Booting from ${storagetype} ...;" \ 131*4882a593Smuzhiyun "run ${storagetype}args; run doboot;\0" \ 132*4882a593Smuzhiyun "trybootk=if run loadkernel; then " \ 133*4882a593Smuzhiyun "if ${doloadfdt}; then " \ 134*4882a593Smuzhiyun "run loadfdt;" \ 135*4882a593Smuzhiyun "fi;" \ 136*4882a593Smuzhiyun "run storagebootcmd;" \ 137*4882a593Smuzhiyun "fi;\0" \ 138*4882a593Smuzhiyun "trybootsmz=if run loadscript; then " \ 139*4882a593Smuzhiyun "run bootscript;" \ 140*4882a593Smuzhiyun "fi;" \ 141*4882a593Smuzhiyun "run setboottypem;" \ 142*4882a593Smuzhiyun "run trybootk;" \ 143*4882a593Smuzhiyun "run setboottypez;" \ 144*4882a593Smuzhiyun "run trybootk;\0" 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 147*4882a593Smuzhiyun "run setupmmcboot;" \ 148*4882a593Smuzhiyun "mmc dev ${storagedev};" \ 149*4882a593Smuzhiyun "if mmc rescan; then " \ 150*4882a593Smuzhiyun "run trybootsmz;" \ 151*4882a593Smuzhiyun "fi;" \ 152*4882a593Smuzhiyun "run setupusbboot;" \ 153*4882a593Smuzhiyun "if usb start; then "\ 154*4882a593Smuzhiyun "if run loadscript; then " \ 155*4882a593Smuzhiyun "run bootscript;" \ 156*4882a593Smuzhiyun "fi;" \ 157*4882a593Smuzhiyun "fi;" \ 158*4882a593Smuzhiyun "run setupsataboot;" \ 159*4882a593Smuzhiyun "if sata init; then " \ 160*4882a593Smuzhiyun "run trybootsmz;" \ 161*4882a593Smuzhiyun "fi;" \ 162*4882a593Smuzhiyun "run setupnandboot;" \ 163*4882a593Smuzhiyun "run nandboot;" 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define CONFIG_PREBOOT "usb start;sf probe" 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* SPI */ 168*4882a593Smuzhiyun #define CONFIG_SPI 169*4882a593Smuzhiyun #define CONFIG_MXC_SPI 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* NAND */ 172*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 173*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 174*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MAX_CHIPS 1 175*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 176*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 177*4882a593Smuzhiyun /* APBH DMA is required for NAND support */ 178*4882a593Smuzhiyun #endif 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* Ethernet */ 181*4882a593Smuzhiyun #define CONFIG_FEC_MXC 182*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 0 183*4882a593Smuzhiyun #define CONFIG_FEC_XCV_TYPE RGMII 184*4882a593Smuzhiyun #define IMX_FEC_BASE ENET_BASE_ADDR 185*4882a593Smuzhiyun #define CONFIG_PHY_ATHEROS 186*4882a593Smuzhiyun #define CONFIG_MII 187*4882a593Smuzhiyun #define CONFIG_ETHPRIME "FEC0" 188*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200UL 189*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 5 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* USB */ 192*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 193*4882a593Smuzhiyun #define CONFIG_MXC_USB_FLAGS 0 194*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 195*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* I2C */ 198*4882a593Smuzhiyun #define CONFIG_SYS_I2C 199*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 200*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 201*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 202*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 203*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 204*4882a593Smuzhiyun #define CONFIG_SYS_MXC_I2C3_SPEED 400000 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 207*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 208*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_BUS 2 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* SATA */ 211*4882a593Smuzhiyun #define CONFIG_SYS_SATA_MAX_DEVICE 1 212*4882a593Smuzhiyun #define CONFIG_LIBATA 213*4882a593Smuzhiyun #define CONFIG_LBA48 214*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA 215*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA_PORT_ID 0 216*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* Boot */ 219*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 220*4882a593Smuzhiyun #define CONFIG_SERIAL_TAG 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* misc */ 223*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 224*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* SPL */ 227*4882a593Smuzhiyun #include "imx6_spl.h" 228*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 229*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* Display */ 232*4882a593Smuzhiyun #define CONFIG_VIDEO_IPUV3 233*4882a593Smuzhiyun #define CONFIG_IPUV3_CLK 260000000 234*4882a593Smuzhiyun #define CONFIG_IMX_HDMI 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define CONFIG_SPLASH_SCREEN 237*4882a593Smuzhiyun #define CONFIG_SPLASH_SOURCE 238*4882a593Smuzhiyun #define CONFIG_VIDEO_BMP_RLE8 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define CONFIG_VIDEO_LOGO 241*4882a593Smuzhiyun #define CONFIG_VIDEO_BMP_LOGO 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* EEPROM */ 244*4882a593Smuzhiyun #define CONFIG_ENV_EEPROM_IS_ON_I2C 245*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 246*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 247*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 248*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_SIZE 256 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #endif /* __CONFIG_CM_FX6_H */ 251