1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 3*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CONFIG_H 9*4882a593Smuzhiyun #define __CONFIG_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_STM32F4DISCOVERY 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x08000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x10010000 18*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x08000000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SYS_ICACHE_OFF 21*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_OFF 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Configuration of the external SDRAM memory 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 27*4882a593Smuzhiyun #define CONFIG_SYS_RAM_SIZE (8 << 20) 28*4882a593Smuzhiyun #define CONFIG_SYS_RAM_CS 1 29*4882a593Smuzhiyun #define CONFIG_SYS_RAM_FREQ_DIV 2 30*4882a593Smuzhiyun #define CONFIG_SYS_RAM_BASE 0xD0000000 31*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE 32*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0xD0400000 33*4882a593Smuzhiyun #define CONFIG_LOADADDR 0xD0400000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 12 36*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (256 << 10) 39*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 << 10) 40*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (8 << 10) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CONFIG_RED_LED 110 43*4882a593Smuzhiyun #define CONFIG_GREEN_LED 109 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CONFIG_STM32_GPIO 46*4882a593Smuzhiyun #define CONFIG_STM32_FLASH 47*4882a593Smuzhiyun #define CONFIG_STM32_SERIAL 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CONFIG_STM32_HSE_HZ 8000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 56*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 57*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 58*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (2 << 20) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 65*4882a593Smuzhiyun "run bootcmd_romfs" 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 68*4882a593Smuzhiyun "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ 69*4882a593Smuzhiyun "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ 70*4882a593Smuzhiyun "bootm 0x08044000 - 0x08042000\0" 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Command line configuration. 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 76*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 77*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __CONFIG_H */ 80