xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/jz4740.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include <dt-bindings/clock/jz4740-cgu.h>
3*4882a593Smuzhiyun#include <dt-bindings/clock/ingenic,tcu.h>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	#address-cells = <1>;
7*4882a593Smuzhiyun	#size-cells = <1>;
8*4882a593Smuzhiyun	compatible = "ingenic,jz4740";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	cpus {
11*4882a593Smuzhiyun		#address-cells = <1>;
12*4882a593Smuzhiyun		#size-cells = <0>;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun		cpu0: cpu@0 {
15*4882a593Smuzhiyun			device_type = "cpu";
16*4882a593Smuzhiyun			compatible = "ingenic,xburst-mxu1.0";
17*4882a593Smuzhiyun			reg = <0>;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun			clocks = <&cgu JZ4740_CLK_CCLK>;
20*4882a593Smuzhiyun			clock-names = "cpu";
21*4882a593Smuzhiyun		};
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	cpuintc: interrupt-controller {
25*4882a593Smuzhiyun		#address-cells = <0>;
26*4882a593Smuzhiyun		#interrupt-cells = <1>;
27*4882a593Smuzhiyun		interrupt-controller;
28*4882a593Smuzhiyun		compatible = "mti,cpu-interrupt-controller";
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	intc: interrupt-controller@10001000 {
32*4882a593Smuzhiyun		compatible = "ingenic,jz4740-intc";
33*4882a593Smuzhiyun		reg = <0x10001000 0x14>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		interrupt-controller;
36*4882a593Smuzhiyun		#interrupt-cells = <1>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		interrupt-parent = <&cpuintc>;
39*4882a593Smuzhiyun		interrupts = <2>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	ext: ext {
43*4882a593Smuzhiyun		compatible = "fixed-clock";
44*4882a593Smuzhiyun		#clock-cells = <0>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	rtc: rtc {
48*4882a593Smuzhiyun		compatible = "fixed-clock";
49*4882a593Smuzhiyun		#clock-cells = <0>;
50*4882a593Smuzhiyun		clock-frequency = <32768>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	cgu: jz4740-cgu@10000000 {
54*4882a593Smuzhiyun		compatible = "ingenic,jz4740-cgu";
55*4882a593Smuzhiyun		reg = <0x10000000 0x100>;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		clocks = <&ext>, <&rtc>;
58*4882a593Smuzhiyun		clock-names = "ext", "rtc";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		#clock-cells = <1>;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	tcu: timer@10002000 {
64*4882a593Smuzhiyun		compatible = "ingenic,jz4740-tcu", "simple-mfd";
65*4882a593Smuzhiyun		reg = <0x10002000 0x1000>;
66*4882a593Smuzhiyun		#address-cells = <1>;
67*4882a593Smuzhiyun		#size-cells = <1>;
68*4882a593Smuzhiyun		ranges = <0x0 0x10002000 0x1000>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		#clock-cells = <1>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_RTC>,
73*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_EXT>,
74*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_PCLK>,
75*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_TCU>;
76*4882a593Smuzhiyun		clock-names = "rtc", "ext", "pclk", "tcu";
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		interrupt-controller;
79*4882a593Smuzhiyun		#interrupt-cells = <1>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		interrupt-parent = <&intc>;
82*4882a593Smuzhiyun		interrupts = <23 22 21>;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun		watchdog: watchdog@0 {
85*4882a593Smuzhiyun			compatible = "ingenic,jz4740-watchdog";
86*4882a593Smuzhiyun			reg = <0x0 0xc>;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun			clocks = <&tcu TCU_CLK_WDT>;
89*4882a593Smuzhiyun			clock-names = "wdt";
90*4882a593Smuzhiyun		};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		pwm: pwm@40 {
93*4882a593Smuzhiyun			compatible = "ingenic,jz4740-pwm";
94*4882a593Smuzhiyun			reg = <0x40 0x80>;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun			#pwm-cells = <3>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
99*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
100*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
101*4882a593Smuzhiyun				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
102*4882a593Smuzhiyun			clock-names = "timer0", "timer1", "timer2", "timer3",
103*4882a593Smuzhiyun				      "timer4", "timer5", "timer6", "timer7";
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	rtc_dev: rtc@10003000 {
108*4882a593Smuzhiyun		compatible = "ingenic,jz4740-rtc";
109*4882a593Smuzhiyun		reg = <0x10003000 0x40>;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		interrupt-parent = <&intc>;
112*4882a593Smuzhiyun		interrupts = <15>;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_RTC>;
115*4882a593Smuzhiyun		clock-names = "rtc";
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	pinctrl: pin-controller@10010000 {
119*4882a593Smuzhiyun		compatible = "ingenic,jz4740-pinctrl";
120*4882a593Smuzhiyun		reg = <0x10010000 0x400>;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		#address-cells = <1>;
123*4882a593Smuzhiyun		#size-cells = <0>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		gpa: gpio@0 {
126*4882a593Smuzhiyun			compatible = "ingenic,jz4740-gpio";
127*4882a593Smuzhiyun			reg = <0>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun			gpio-controller;
130*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 0 32>;
131*4882a593Smuzhiyun			#gpio-cells = <2>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun			interrupt-controller;
134*4882a593Smuzhiyun			#interrupt-cells = <2>;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun			interrupt-parent = <&intc>;
137*4882a593Smuzhiyun			interrupts = <28>;
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		gpb: gpio@1 {
141*4882a593Smuzhiyun			compatible = "ingenic,jz4740-gpio";
142*4882a593Smuzhiyun			reg = <1>;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			gpio-controller;
145*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 32 32>;
146*4882a593Smuzhiyun			#gpio-cells = <2>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun			interrupt-controller;
149*4882a593Smuzhiyun			#interrupt-cells = <2>;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun			interrupt-parent = <&intc>;
152*4882a593Smuzhiyun			interrupts = <27>;
153*4882a593Smuzhiyun		};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun		gpc: gpio@2 {
156*4882a593Smuzhiyun			compatible = "ingenic,jz4740-gpio";
157*4882a593Smuzhiyun			reg = <2>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun			gpio-controller;
160*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 64 32>;
161*4882a593Smuzhiyun			#gpio-cells = <2>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			interrupt-controller;
164*4882a593Smuzhiyun			#interrupt-cells = <2>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun			interrupt-parent = <&intc>;
167*4882a593Smuzhiyun			interrupts = <26>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		gpd: gpio@3 {
171*4882a593Smuzhiyun			compatible = "ingenic,jz4740-gpio";
172*4882a593Smuzhiyun			reg = <3>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			gpio-controller;
175*4882a593Smuzhiyun			gpio-ranges = <&pinctrl 0 96 32>;
176*4882a593Smuzhiyun			#gpio-cells = <2>;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun			interrupt-controller;
179*4882a593Smuzhiyun			#interrupt-cells = <2>;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun			interrupt-parent = <&intc>;
182*4882a593Smuzhiyun			interrupts = <25>;
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	aic: audio-controller@10020000 {
187*4882a593Smuzhiyun		compatible = "ingenic,jz4740-i2s";
188*4882a593Smuzhiyun		reg = <0x10020000 0x38>;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun		#sound-dai-cells = <0>;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun		interrupt-parent = <&intc>;
193*4882a593Smuzhiyun		interrupts = <18>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_AIC>,
196*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_I2S>,
197*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_EXT>,
198*4882a593Smuzhiyun			 <&cgu JZ4740_CLK_PLL_HALF>;
199*4882a593Smuzhiyun		clock-names = "aic", "i2s", "ext", "pll half";
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun		dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
202*4882a593Smuzhiyun		dma-names = "rx", "tx";
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	codec: audio-codec@100200a4 {
206*4882a593Smuzhiyun		compatible = "ingenic,jz4740-codec";
207*4882a593Smuzhiyun		reg = <0x10020080 0x8>;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		#sound-dai-cells = <0>;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_AIC>;
212*4882a593Smuzhiyun		clock-names = "aic";
213*4882a593Smuzhiyun	};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun	mmc: mmc@10021000 {
216*4882a593Smuzhiyun		compatible = "ingenic,jz4740-mmc";
217*4882a593Smuzhiyun		reg = <0x10021000 0x1000>;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_MMC>;
220*4882a593Smuzhiyun		clock-names = "mmc";
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun		interrupt-parent = <&intc>;
223*4882a593Smuzhiyun		interrupts = <14>;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun		dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
226*4882a593Smuzhiyun		dma-names = "rx", "tx";
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun		cap-sd-highspeed;
229*4882a593Smuzhiyun		cap-mmc-highspeed;
230*4882a593Smuzhiyun		cap-sdio-irq;
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	uart0: serial@10030000 {
234*4882a593Smuzhiyun		compatible = "ingenic,jz4740-uart";
235*4882a593Smuzhiyun		reg = <0x10030000 0x100>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		interrupt-parent = <&intc>;
238*4882a593Smuzhiyun		interrupts = <9>;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
241*4882a593Smuzhiyun		clock-names = "baud", "module";
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun	uart1: serial@10031000 {
245*4882a593Smuzhiyun		compatible = "ingenic,jz4740-uart";
246*4882a593Smuzhiyun		reg = <0x10031000 0x100>;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		interrupt-parent = <&intc>;
249*4882a593Smuzhiyun		interrupts = <8>;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun		clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
252*4882a593Smuzhiyun		clock-names = "baud", "module";
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	adc: adc@10070000 {
256*4882a593Smuzhiyun		compatible = "ingenic,jz4740-adc";
257*4882a593Smuzhiyun		reg = <0x10070000 0x30>;
258*4882a593Smuzhiyun		#io-channel-cells = <1>;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_ADC>;
261*4882a593Smuzhiyun		clock-names = "adc";
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun		interrupt-parent = <&intc>;
264*4882a593Smuzhiyun		interrupts = <12>;
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun	nemc: memory-controller@13010000 {
268*4882a593Smuzhiyun		compatible = "ingenic,jz4740-nemc";
269*4882a593Smuzhiyun		reg = <0x13010000 0x54>;
270*4882a593Smuzhiyun		#address-cells = <2>;
271*4882a593Smuzhiyun		#size-cells = <1>;
272*4882a593Smuzhiyun		ranges = <1 0 0x18000000 0x4000000>,
273*4882a593Smuzhiyun			 <2 0 0x14000000 0x4000000>,
274*4882a593Smuzhiyun			 <3 0 0x0c000000 0x4000000>,
275*4882a593Smuzhiyun			 <4 0 0x08000000 0x4000000>;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_MCLK>;
278*4882a593Smuzhiyun	};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	ecc: ecc-controller@13010100 {
281*4882a593Smuzhiyun		compatible = "ingenic,jz4740-ecc";
282*4882a593Smuzhiyun		reg = <0x13010100 0x2C>;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_MCLK>;
285*4882a593Smuzhiyun	};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun	dmac: dma-controller@13020000 {
288*4882a593Smuzhiyun		compatible = "ingenic,jz4740-dma";
289*4882a593Smuzhiyun		reg = <0x13020000 0xbc>, <0x13020300 0x14>;
290*4882a593Smuzhiyun		#dma-cells = <2>;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun		interrupt-parent = <&intc>;
293*4882a593Smuzhiyun		interrupts = <20>;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_DMA>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	uhc: uhc@13030000 {
299*4882a593Smuzhiyun		compatible = "ingenic,jz4740-ohci", "generic-ohci";
300*4882a593Smuzhiyun		reg = <0x13030000 0x1000>;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_UHC>;
303*4882a593Smuzhiyun		assigned-clocks = <&cgu JZ4740_CLK_UHC>;
304*4882a593Smuzhiyun		assigned-clock-rates = <48000000>;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		interrupt-parent = <&intc>;
307*4882a593Smuzhiyun		interrupts = <3>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		status = "disabled";
310*4882a593Smuzhiyun	};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	udc: usb@13040000 {
313*4882a593Smuzhiyun		compatible = "ingenic,jz4740-musb";
314*4882a593Smuzhiyun		reg = <0x13040000 0x10000>;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun		interrupt-parent = <&intc>;
317*4882a593Smuzhiyun		interrupts = <24>;
318*4882a593Smuzhiyun		interrupt-names = "mc";
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_UDC>;
321*4882a593Smuzhiyun		clock-names = "udc";
322*4882a593Smuzhiyun	};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun	lcd: lcd-controller@13050000 {
325*4882a593Smuzhiyun		compatible = "ingenic,jz4740-lcd";
326*4882a593Smuzhiyun		reg = <0x13050000 0x1000>;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun		interrupt-parent = <&intc>;
329*4882a593Smuzhiyun		interrupts = <30>;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun		clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
332*4882a593Smuzhiyun		clock-names = "lcd_pclk", "lcd";
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun};
335