1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Ingenic SoCs pin controller devicetree bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: > 10*4882a593Smuzhiyun Please refer to pinctrl-bindings.txt in this directory for details of the 11*4882a593Smuzhiyun common pinctrl bindings used by client devices, including the meaning of the 12*4882a593Smuzhiyun phrase "pin configuration node". 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins 15*4882a593Smuzhiyun may be used as GPIOs, multiplexed device functions are configured within the 16*4882a593Smuzhiyun GPIO port configuration registers and it is typical to refer to pins using the 17*4882a593Smuzhiyun naming scheme "PxN" where x is a character identifying the GPIO port with 18*4882a593Smuzhiyun which the pin is associated and N is an integer from 0 to 31 identifying the 19*4882a593Smuzhiyun pin within that GPIO port. For example PA0 is the first pin in GPIO port A, 20*4882a593Smuzhiyun and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830 21*4882a593Smuzhiyun contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the 22*4882a593Smuzhiyun JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192 23*4882a593Smuzhiyun pins. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunmaintainers: 26*4882a593Smuzhiyun - Paul Cercueil <paul@crapouillou.net> 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunproperties: 29*4882a593Smuzhiyun nodename: 30*4882a593Smuzhiyun pattern: "^pinctrl@[0-9a-f]+$" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun compatible: 33*4882a593Smuzhiyun oneOf: 34*4882a593Smuzhiyun - enum: 35*4882a593Smuzhiyun - ingenic,jz4740-pinctrl 36*4882a593Smuzhiyun - ingenic,jz4725b-pinctrl 37*4882a593Smuzhiyun - ingenic,jz4760-pinctrl 38*4882a593Smuzhiyun - ingenic,jz4770-pinctrl 39*4882a593Smuzhiyun - ingenic,jz4780-pinctrl 40*4882a593Smuzhiyun - ingenic,x1000-pinctrl 41*4882a593Smuzhiyun - ingenic,x1500-pinctrl 42*4882a593Smuzhiyun - ingenic,x1830-pinctrl 43*4882a593Smuzhiyun - items: 44*4882a593Smuzhiyun - const: ingenic,jz4760b-pinctrl 45*4882a593Smuzhiyun - const: ingenic,jz4760-pinctrl 46*4882a593Smuzhiyun - items: 47*4882a593Smuzhiyun - const: ingenic,x1000e-pinctrl 48*4882a593Smuzhiyun - const: ingenic,x1000-pinctrl 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun reg: 51*4882a593Smuzhiyun maxItems: 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun "#address-cells": 54*4882a593Smuzhiyun const: 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun "#size-cells": 57*4882a593Smuzhiyun const: 0 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunpatternProperties: 60*4882a593Smuzhiyun "^gpio@[0-9]$": 61*4882a593Smuzhiyun type: object 62*4882a593Smuzhiyun properties: 63*4882a593Smuzhiyun compatible: 64*4882a593Smuzhiyun enum: 65*4882a593Smuzhiyun - ingenic,jz4740-gpio 66*4882a593Smuzhiyun - ingenic,jz4725b-gpio 67*4882a593Smuzhiyun - ingenic,jz4760-gpio 68*4882a593Smuzhiyun - ingenic,jz4770-gpio 69*4882a593Smuzhiyun - ingenic,jz4780-gpio 70*4882a593Smuzhiyun - ingenic,x1000-gpio 71*4882a593Smuzhiyun - ingenic,x1500-gpio 72*4882a593Smuzhiyun - ingenic,x1830-gpio 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun reg: 75*4882a593Smuzhiyun items: 76*4882a593Smuzhiyun - description: The GPIO bank number 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun gpio-controller: true 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun "#gpio-cells": 81*4882a593Smuzhiyun const: 2 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun gpio-ranges: 84*4882a593Smuzhiyun maxItems: 1 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun interrupt-controller: true 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun "#interrupt-cells": 89*4882a593Smuzhiyun const: 2 90*4882a593Smuzhiyun description: 91*4882a593Smuzhiyun Refer to ../interrupt-controller/interrupts.txt for more details. 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun interrupts: 94*4882a593Smuzhiyun maxItems: 1 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun required: 97*4882a593Smuzhiyun - compatible 98*4882a593Smuzhiyun - reg 99*4882a593Smuzhiyun - gpio-controller 100*4882a593Smuzhiyun - "#gpio-cells" 101*4882a593Smuzhiyun - interrupts 102*4882a593Smuzhiyun - interrupt-controller 103*4882a593Smuzhiyun - "#interrupt-cells" 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun additionalProperties: false 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunrequired: 108*4882a593Smuzhiyun - compatible 109*4882a593Smuzhiyun - reg 110*4882a593Smuzhiyun - "#address-cells" 111*4882a593Smuzhiyun - "#size-cells" 112*4882a593Smuzhiyun 113*4882a593SmuzhiyunadditionalProperties: 114*4882a593Smuzhiyun anyOf: 115*4882a593Smuzhiyun - type: object 116*4882a593Smuzhiyun allOf: 117*4882a593Smuzhiyun - $ref: pincfg-node.yaml# 118*4882a593Smuzhiyun - $ref: pinmux-node.yaml# 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun properties: 121*4882a593Smuzhiyun phandle: true 122*4882a593Smuzhiyun function: true 123*4882a593Smuzhiyun groups: true 124*4882a593Smuzhiyun pins: true 125*4882a593Smuzhiyun bias-disable: true 126*4882a593Smuzhiyun bias-pull-up: true 127*4882a593Smuzhiyun bias-pull-down: true 128*4882a593Smuzhiyun output-low: true 129*4882a593Smuzhiyun output-high: true 130*4882a593Smuzhiyun additionalProperties: false 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun - type: object 133*4882a593Smuzhiyun properties: 134*4882a593Smuzhiyun phandle: true 135*4882a593Smuzhiyun additionalProperties: 136*4882a593Smuzhiyun type: object 137*4882a593Smuzhiyun allOf: 138*4882a593Smuzhiyun - $ref: pincfg-node.yaml# 139*4882a593Smuzhiyun - $ref: pinmux-node.yaml# 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun properties: 142*4882a593Smuzhiyun phandle: true 143*4882a593Smuzhiyun function: true 144*4882a593Smuzhiyun groups: true 145*4882a593Smuzhiyun pins: true 146*4882a593Smuzhiyun bias-disable: true 147*4882a593Smuzhiyun bias-pull-up: true 148*4882a593Smuzhiyun bias-pull-down: true 149*4882a593Smuzhiyun output-low: true 150*4882a593Smuzhiyun output-high: true 151*4882a593Smuzhiyun additionalProperties: false 152*4882a593Smuzhiyun 153*4882a593Smuzhiyunexamples: 154*4882a593Smuzhiyun - | 155*4882a593Smuzhiyun pin-controller@10010000 { 156*4882a593Smuzhiyun compatible = "ingenic,jz4770-pinctrl"; 157*4882a593Smuzhiyun reg = <0x10010000 0x600>; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #address-cells = <1>; 160*4882a593Smuzhiyun #size-cells = <0>; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun gpio@0 { 163*4882a593Smuzhiyun compatible = "ingenic,jz4770-gpio"; 164*4882a593Smuzhiyun reg = <0>; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun gpio-controller; 167*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 32>; 168*4882a593Smuzhiyun #gpio-cells = <2>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun interrupt-controller; 171*4882a593Smuzhiyun #interrupt-cells = <2>; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun interrupt-parent = <&intc>; 174*4882a593Smuzhiyun interrupts = <17>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun }; 177