1*4882a593Smuzhiyun* Samsung Exynos5420 Clock Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Exynos5420 clock controller generates and supplies clock to various 4*4882a593Smuzhiyuncontrollers within the Exynos5420 SoC and for the Exynos5800 SoC. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: should be one of the following. 9*4882a593Smuzhiyun - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 10*4882a593Smuzhiyun - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 13*4882a593Smuzhiyun region. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #clock-cells: should be 1. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunEach clock is assigned an identifier and client nodes can use this identifier 18*4882a593Smuzhiyunto specify the clock which they consume. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunAll available clocks are defined as preprocessor macros in 21*4882a593Smuzhiyundt-bindings/clock/exynos5420.h header and can be used in device 22*4882a593Smuzhiyuntree sources. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample 1: An example of a clock controller node is listed below. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clock: clock-controller@10010000 { 27*4882a593Smuzhiyun compatible = "samsung,exynos5420-clock"; 28*4882a593Smuzhiyun reg = <0x10010000 0x30000>; 29*4882a593Smuzhiyun #clock-cells = <1>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExample 2: UART controller node that consumes the clock generated by the clock 33*4882a593Smuzhiyun controller. Refer to the standard clock bindings for information 34*4882a593Smuzhiyun about 'clocks' and 'clock-names' property. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun serial@13820000 { 37*4882a593Smuzhiyun compatible = "samsung,exynos4210-uart"; 38*4882a593Smuzhiyun reg = <0x13820000 0x100>; 39*4882a593Smuzhiyun interrupts = <0 54 0>; 40*4882a593Smuzhiyun clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 41*4882a593Smuzhiyun clock-names = "uart", "clk_uart_baud0"; 42*4882a593Smuzhiyun }; 43