1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/serial/sifive-serial.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: SiFive asynchronous serial interface (UART) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Pragnesh Patel <pragnesh.patel@sifive.com> 11*4882a593Smuzhiyun - Paul Walmsley <paul.walmsley@sifive.com> 12*4882a593Smuzhiyun - Palmer Dabbelt <palmer@sifive.com> 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunallOf: 15*4882a593Smuzhiyun - $ref: /schemas/serial.yaml# 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun items: 20*4882a593Smuzhiyun - const: sifive,fu540-c000-uart 21*4882a593Smuzhiyun - const: sifive,uart0 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun description: 24*4882a593Smuzhiyun Should be something similar to "sifive,<chip>-uart" 25*4882a593Smuzhiyun for the UART as integrated on a particular chip, 26*4882a593Smuzhiyun and "sifive,uart<version>" for the general UART IP 27*4882a593Smuzhiyun block programming model. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun UART HDL that corresponds to the IP block version 30*4882a593Smuzhiyun numbers can be found here - 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reg: 35*4882a593Smuzhiyun maxItems: 1 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun interrupts: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clocks: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunrequired: 44*4882a593Smuzhiyun - compatible 45*4882a593Smuzhiyun - reg 46*4882a593Smuzhiyun - interrupts 47*4882a593Smuzhiyun - clocks 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunadditionalProperties: false 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunexamples: 52*4882a593Smuzhiyun - | 53*4882a593Smuzhiyun #include <dt-bindings/clock/sifive-fu540-prci.h> 54*4882a593Smuzhiyun serial@10010000 { 55*4882a593Smuzhiyun compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 56*4882a593Smuzhiyun interrupt-parent = <&plic0>; 57*4882a593Smuzhiyun interrupts = <80>; 58*4882a593Smuzhiyun reg = <0x10010000 0x1000>; 59*4882a593Smuzhiyun clocks = <&prci PRCI_CLK_TLCLK>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun... 63