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/OK3568_Linux_fs/u-boot/include/configs/
H A Dpogo_e02.h42 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
45 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
46 #define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
54 "bootm 0x00800000 0x01100000"
58 "32M(rootfs),-(data)\0"\
59 "mtdids=nand0=orion_nand\0"\
60 "bootargs_console=console=ttyS0,115200\0" \
61 "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
62 "ext2load usb 0:1 0x01100000 /uInitrd\0"
68 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
[all …]
H A DUCP1020.h28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
92 #define CONFIG_SYS_TEXT_BASE 0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
100 #define CONFIG_SYS_TEXT_BASE 0x11000000
101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
105 #define CONFIG_SYS_TEXT_BASE 0xeff80000
107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Danubis.h17 #define ANUBIS_CTRL1_NANDSEL (0x3)
21 #define ANUBIS_IDREG_REVMASK (0x7)
33 #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
39 #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000)
42 #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000)
45 #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
46 #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
47 #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
48 #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/sdram_inc/rv1126/
H A Dsdram-rv1126-lpddr3-detect-664.inc4 .rank = 0x1,
5 .col = 0xC,
6 .bk = 0x3,
7 .bw = 0x1,
8 .dbw = 0x0,
9 .row_3_4 = 0x0,
10 .cs0_row = 0x10,
11 .cs1_row = 0x10,
12 .cs0_high16bit_row = 0x10,
13 .cs1_high16bit_row = 0x10,
[all …]
H A Dsdram-rv1126-lpddr4-detect-664.inc4 .rank = 0x1,
5 .col = 0xB,
6 .bk = 0x3,
7 .bw = 0x1,
8 .dbw = 0x1,
9 .row_3_4 = 0x0,
10 .cs0_row = 0x11,
11 .cs1_row = 0x11,
12 .cs0_high16bit_row = 0x0,
13 .cs1_high16bit_row = 0x0,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-de2-mixer.yaml16 - allwinner,sun8i-a83t-de2-mixer-0
18 - allwinner,sun8i-h3-de2-mixer-0
19 - allwinner,sun8i-r40-de2-mixer-0
22 - allwinner,sun50i-a64-de2-mixer-0
24 - allwinner,sun50i-h6-de3-mixer-0
56 const: 0
58 port@0:
91 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
92 reg = <0x01100000 0x100000>;
101 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h10 #define OCRAM_BASE_ADDR 0x10000000
11 #define OCRAM_SIZE 0x00010000
12 #define OCRAM_BASE_S_ADDR 0x10010000
13 #define OCRAM_S_SIZE 0x00010000
15 #define CONFIG_SYS_IMMR 0x01000000
16 #define CONFIG_SYS_DCSRBAR 0x20000000
18 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
19 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
21 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
22 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_DCSRBAR 0x20000000
14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
20 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
21 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
[all …]
H A Dimmap_lsch3.h13 #define CONFIG_SYS_IMMR 0x01000000
14 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
15 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
16 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
17 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
18 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
21 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
22 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp2020rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp1020rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp1020rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
68 reg = <0x00400000 0x00b00000>;
76 reg = <0x00f00000 0x00100000>;
82 nand@1,0 {
87 reg = <0x1 0x0 0x40000>;
[all …]
H A Dp2020rdb.dts29 reg = <0 0xffe05000 0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
33 0x1 0x0 0x0 0xffa00000 0x00040000
34 0x2 0x0 0x0 0xffb00000 0x00020000>;
36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
61 reg = <0x00080000 0x00380000>;
[all …]
H A Dp1021rdb-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00ac0000>;
73 reg = <0x00ec0000 0x00040000>;
82 reg = <0x00f00000 0x00100000>;
87 nand@1,0 {
[all …]
H A Dp1021mds.dts23 reg = <0x0 0xffe05000 0x0 0x1000>;
26 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
27 0x1 0x0 0x0 0xf8000000 0x00008000
28 0x2 0x0 0x0 0xf8010000 0x00020000
29 0x3 0x0 0x0 0xf8020000 0x00020000>;
31 nand@0,0 {
36 reg = <0x0 0x0 0x40000>;
38 partition@0 {
41 reg = <0x0 0x00100000>;
48 reg = <0x00100000 0x00100000>;
[all …]
H A Dp1025rdb.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x1000000>;
44 partition@0 {
47 reg = <0x0 0x00040000>;
54 reg = <0x00040000 0x00040000>;
60 reg = <0x00080000 0x00380000>;
66 reg = <0x00400000 0x00b00000>;
74 reg = <0x00f00000 0x00100000>;
80 nand@1,0 {
85 reg = <0x1 0x0 0x40000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dda850-lcdk.dts24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x00 0x00101010 0x00f0f0f0
207 0x04 0x00000110 0x00000ff0
213 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
[all …]
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
H A Dsun8i-v3s.dtsi70 #size-cells = <0>;
72 cpu@0 {
75 reg = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
124 reg = <0x01000000 0x10000>;
136 reg = <0x01100000 0x100000>;
137 clocks = <&display_clocks 0>,
141 resets = <&display_clocks 0>;
145 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8723b.c36 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
37 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
38 {0x430, 0x00}, {0x431, 0x00},
39 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
40 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
41 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
42 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
43 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
44 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
45 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dtrizeps4.c151 .offset = 0x00000000,
152 .size = 0x00040000,
156 .offset = 0x00040000,
157 .size = 0x00040000,
160 .offset = 0x00080000,
161 .size = 0x01080000,
164 .offset = 0x01100000,
165 .size = 0x00e00000,
168 .offset = 0x01f00000,
189 .id = 0,
[all …]
/OK3568_Linux_fs/u-boot/drivers/pci/
H A Dpcie_imx.c24 #define PCI_ACCESS_READ 0
28 #define MX6_DBI_ADDR 0x08ffc000
29 #define MX6_IO_ADDR 0x08000000
30 #define MX6_MEM_ADDR 0x08100000
31 #define MX6_ROOT_ADDR 0x08f00000
33 #define MX6_DBI_ADDR 0x01ffc000
34 #define MX6_IO_ADDR 0x01000000
35 #define MX6_MEM_ADDR 0x01100000
36 #define MX6_ROOT_ADDR 0x01f00000
38 #define MX6_DBI_SIZE 0x4000
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/devices/
H A Dlart.c71 #define FLASH_OFFSET 0xe8000000 /* see linux/arch/arm/mach-sa1100/lart.c */
75 #define PART_BLOB_START 0x00000000
91 #define READ_ARRAY 0x00FF00FF /* Read Array/Reset */
92 #define READ_ID_CODES 0x00900090 /* Read Identifier Codes */
93 #define ERASE_SETUP 0x00200020 /* Block Erase */
94 #define ERASE_CONFIRM 0x00D000D0 /* Block Erase and Program Resume */
95 #define PGM_SETUP 0x00400040 /* Program */
96 #define STATUS_READ 0x00700070 /* Read Status Register */
97 #define STATUS_CLEAR 0x00500050 /* Clear Status Register */
98 #define STATUS_BUSY 0x00800080 /* Write State Machine Status (WSMS) */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x000FFFFF
16 #define GPU_2D_ARB_BASE_ADDR 0x02200000
17 #define GPU_2D_ARB_END_ADDR 0x02203FFF
18 #define OPENVG_ARB_BASE_ADDR 0x02204000
19 #define OPENVG_ARB_END_ADDR 0x02207FFF
21 #define CAAM_ARB_BASE_ADDR 0x00100000
22 #define CAAM_ARB_END_ADDR 0x00107FFF
23 #define GPU_ARB_BASE_ADDR 0x01800000
24 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]

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