xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/da850-evm.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree for DA850 EVM board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include "da850.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	compatible = "ti,da850-evm", "ti,da850";
13*4882a593Smuzhiyun	model = "DA850/AM1808/OMAP-L138 EVM";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	chosen {
16*4882a593Smuzhiyun		stdout-path = &serial2;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		serial0 = &serial0;
21*4882a593Smuzhiyun		serial1 = &serial1;
22*4882a593Smuzhiyun		serial2 = &serial2;
23*4882a593Smuzhiyun		ethernet0 = &eth0;
24*4882a593Smuzhiyun		spi0 = &spi1;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	backlight: backlight-pwm {
28*4882a593Smuzhiyun		pinctrl-names = "default";
29*4882a593Smuzhiyun		pinctrl-0 = <&ecap2_pins>;
30*4882a593Smuzhiyun		power-supply = <&backlight_lcd>;
31*4882a593Smuzhiyun		compatible = "pwm-backlight";
32*4882a593Smuzhiyun		/*
33*4882a593Smuzhiyun		 * The PWM here corresponds to production hardware. The
34*4882a593Smuzhiyun		 * schematic needs to be 1015171 (15 March 2010), Rev A
35*4882a593Smuzhiyun		 * or newer.
36*4882a593Smuzhiyun		 */
37*4882a593Smuzhiyun		pwms = <&ecap2 0 50000 0>;
38*4882a593Smuzhiyun		brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
39*4882a593Smuzhiyun		default-brightness-level = <7>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	panel {
43*4882a593Smuzhiyun		compatible = "ti,tilcdc,panel";
44*4882a593Smuzhiyun		pinctrl-names = "default";
45*4882a593Smuzhiyun		pinctrl-0 = <&lcd_pins>;
46*4882a593Smuzhiyun		/*
47*4882a593Smuzhiyun		 * The vpif and the LCD are mutually exclusive.
48*4882a593Smuzhiyun		 * To enable VPIF, change the status below to 'disabled' then
49*4882a593Smuzhiyun		 * then change the status of the vpif below to 'okay'
50*4882a593Smuzhiyun		 */
51*4882a593Smuzhiyun		status = "okay";
52*4882a593Smuzhiyun		enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		panel-info {
55*4882a593Smuzhiyun			ac-bias		= <255>;
56*4882a593Smuzhiyun			ac-bias-intrpt	= <0>;
57*4882a593Smuzhiyun			dma-burst-sz	= <16>;
58*4882a593Smuzhiyun			bpp		= <16>;
59*4882a593Smuzhiyun			fdd		= <0x80>;
60*4882a593Smuzhiyun			sync-edge	= <0>;
61*4882a593Smuzhiyun			sync-ctrl	= <1>;
62*4882a593Smuzhiyun			raster-order	= <0>;
63*4882a593Smuzhiyun			fifo-th		= <0>;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		display-timings {
67*4882a593Smuzhiyun			native-mode = <&timing0>;
68*4882a593Smuzhiyun			timing0: 480x272 {
69*4882a593Smuzhiyun				clock-frequency = <9000000>;
70*4882a593Smuzhiyun				hactive = <480>;
71*4882a593Smuzhiyun				vactive = <272>;
72*4882a593Smuzhiyun				hfront-porch = <3>;
73*4882a593Smuzhiyun				hback-porch = <2>;
74*4882a593Smuzhiyun				hsync-len = <42>;
75*4882a593Smuzhiyun				vback-porch = <3>;
76*4882a593Smuzhiyun				vfront-porch = <4>;
77*4882a593Smuzhiyun				vsync-len = <11>;
78*4882a593Smuzhiyun				hsync-active = <0>;
79*4882a593Smuzhiyun				vsync-active = <0>;
80*4882a593Smuzhiyun				de-active = <1>;
81*4882a593Smuzhiyun				pixelclk-active = <1>;
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	vbat: fixedregulator0 {
87*4882a593Smuzhiyun		compatible = "regulator-fixed";
88*4882a593Smuzhiyun		regulator-name = "vbat";
89*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
90*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
91*4882a593Smuzhiyun		regulator-boot-on;
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	baseboard_3v3: fixedregulator-3v3 {
95*4882a593Smuzhiyun		/* TPS73701DCQ */
96*4882a593Smuzhiyun		compatible = "regulator-fixed";
97*4882a593Smuzhiyun		regulator-name = "baseboard_3v3";
98*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
99*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
100*4882a593Smuzhiyun		vin-supply = <&vbat>;
101*4882a593Smuzhiyun		regulator-always-on;
102*4882a593Smuzhiyun		regulator-boot-on;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	baseboard_1v8: fixedregulator-1v8 {
106*4882a593Smuzhiyun		/* TPS73701DCQ */
107*4882a593Smuzhiyun		compatible = "regulator-fixed";
108*4882a593Smuzhiyun		regulator-name = "baseboard_1v8";
109*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
110*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
111*4882a593Smuzhiyun		vin-supply = <&vbat>;
112*4882a593Smuzhiyun		regulator-always-on;
113*4882a593Smuzhiyun		regulator-boot-on;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	backlight_lcd: backlight-regulator {
117*4882a593Smuzhiyun		compatible = "regulator-fixed";
118*4882a593Smuzhiyun		regulator-name = "lcd_backlight_pwr";
119*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
120*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
121*4882a593Smuzhiyun		gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
122*4882a593Smuzhiyun		enable-active-high;
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	sound {
126*4882a593Smuzhiyun		compatible = "simple-audio-card";
127*4882a593Smuzhiyun		simple-audio-card,name = "DA850-OMAPL138 EVM";
128*4882a593Smuzhiyun		simple-audio-card,widgets =
129*4882a593Smuzhiyun			"Line", "Line In",
130*4882a593Smuzhiyun			"Line", "Line Out";
131*4882a593Smuzhiyun		simple-audio-card,routing =
132*4882a593Smuzhiyun			"LINE1L", "Line In",
133*4882a593Smuzhiyun			"LINE1R", "Line In",
134*4882a593Smuzhiyun			"Line Out", "LLOUT",
135*4882a593Smuzhiyun			"Line Out", "RLOUT";
136*4882a593Smuzhiyun		simple-audio-card,format = "dsp_b";
137*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&link0_codec>;
138*4882a593Smuzhiyun		simple-audio-card,frame-master = <&link0_codec>;
139*4882a593Smuzhiyun		simple-audio-card,bitclock-inversion;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		simple-audio-card,cpu {
142*4882a593Smuzhiyun			sound-dai = <&mcasp0>;
143*4882a593Smuzhiyun			system-clock-frequency = <24576000>;
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun		link0_codec: simple-audio-card,codec {
147*4882a593Smuzhiyun			sound-dai = <&tlv320aic3106>;
148*4882a593Smuzhiyun			system-clock-frequency = <24576000>;
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&ecap2 {
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&ref_clk {
158*4882a593Smuzhiyun	clock-frequency = <24000000>;
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&pmx_core {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	mcasp0_pins: pinmux_mcasp0_pins {
165*4882a593Smuzhiyun		pinctrl-single,bits = <
166*4882a593Smuzhiyun			/*
167*4882a593Smuzhiyun			 * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
168*4882a593Smuzhiyun			 * AFSR, AMUTE
169*4882a593Smuzhiyun			 */
170*4882a593Smuzhiyun			0x00 0x11111111 0xffffffff
171*4882a593Smuzhiyun			/* AXR11, AXR12 */
172*4882a593Smuzhiyun			0x04 0x00011000 0x000ff000
173*4882a593Smuzhiyun		>;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun	nand_pins: nand_pins {
176*4882a593Smuzhiyun		pinctrl-single,bits = <
177*4882a593Smuzhiyun			/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
178*4882a593Smuzhiyun			0x1c 0x10110110  0xf0ff0ff0
179*4882a593Smuzhiyun			/*
180*4882a593Smuzhiyun			 * EMA_D[0], EMA_D[1], EMA_D[2],
181*4882a593Smuzhiyun			 * EMA_D[3], EMA_D[4], EMA_D[5],
182*4882a593Smuzhiyun			 * EMA_D[6], EMA_D[7]
183*4882a593Smuzhiyun			 */
184*4882a593Smuzhiyun			0x24 0x11111111  0xffffffff
185*4882a593Smuzhiyun			/* EMA_A[1], EMA_A[2] */
186*4882a593Smuzhiyun			0x30 0x01100000  0x0ff00000
187*4882a593Smuzhiyun		>;
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&cpu {
192*4882a593Smuzhiyun	cpu-supply = <&vdcdc3_reg>;
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun/*
196*4882a593Smuzhiyun * The standard da850-evm kits and SOM's are 375MHz so enable this operating
197*4882a593Smuzhiyun * point by default. Higher frequencies must be enabled for custom boards with
198*4882a593Smuzhiyun * other variants of the SoC.
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun&opp_375 {
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&sata {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&serial0 {
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&serial1 {
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&serial2 {
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&rtc0 {
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&lcdc {
225*4882a593Smuzhiyun	status = "okay";
226*4882a593Smuzhiyun};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun&i2c0 {
229*4882a593Smuzhiyun	status = "okay";
230*4882a593Smuzhiyun	clock-frequency = <100000>;
231*4882a593Smuzhiyun	pinctrl-names = "default";
232*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun	tps: tps@48 {
235*4882a593Smuzhiyun		reg = <0x48>;
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun	tlv320aic3106: tlv320aic3106@18 {
238*4882a593Smuzhiyun		#sound-dai-cells = <0>;
239*4882a593Smuzhiyun		compatible = "ti,tlv320aic3106";
240*4882a593Smuzhiyun		reg = <0x18>;
241*4882a593Smuzhiyun		status = "okay";
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun		/* Regulators */
244*4882a593Smuzhiyun		IOVDD-supply = <&vdcdc2_reg>;
245*4882a593Smuzhiyun		AVDD-supply = <&baseboard_3v3>;
246*4882a593Smuzhiyun		DRVDD-supply = <&baseboard_3v3>;
247*4882a593Smuzhiyun		DVDD-supply = <&baseboard_1v8>;
248*4882a593Smuzhiyun	};
249*4882a593Smuzhiyun	tca6416: gpio@20 {
250*4882a593Smuzhiyun		compatible = "ti,tca6416";
251*4882a593Smuzhiyun		reg = <0x20>;
252*4882a593Smuzhiyun		gpio-controller;
253*4882a593Smuzhiyun		#gpio-cells = <2>;
254*4882a593Smuzhiyun	};
255*4882a593Smuzhiyun	tca6416_bb: gpio@21 {
256*4882a593Smuzhiyun		compatible = "ti,tca6416";
257*4882a593Smuzhiyun		reg = <0x21>;
258*4882a593Smuzhiyun		gpio-controller;
259*4882a593Smuzhiyun		#gpio-cells = <2>;
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&wdt {
264*4882a593Smuzhiyun	status = "okay";
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&mmc0 {
268*4882a593Smuzhiyun	max-frequency = <50000000>;
269*4882a593Smuzhiyun	bus-width = <4>;
270*4882a593Smuzhiyun	status = "okay";
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&mmc0_pins>;
273*4882a593Smuzhiyun	cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
274*4882a593Smuzhiyun	wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
275*4882a593Smuzhiyun};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun&spi1 {
278*4882a593Smuzhiyun	status = "okay";
279*4882a593Smuzhiyun	pinctrl-names = "default";
280*4882a593Smuzhiyun	pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
281*4882a593Smuzhiyun	flash: m25p80@0 {
282*4882a593Smuzhiyun		#address-cells = <1>;
283*4882a593Smuzhiyun		#size-cells = <1>;
284*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
285*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
286*4882a593Smuzhiyun		m25p,fast-read;
287*4882a593Smuzhiyun		reg = <0>;
288*4882a593Smuzhiyun		partition@0 {
289*4882a593Smuzhiyun			label = "U-Boot-SPL";
290*4882a593Smuzhiyun			reg = <0x00000000 0x00010000>;
291*4882a593Smuzhiyun			read-only;
292*4882a593Smuzhiyun		};
293*4882a593Smuzhiyun		partition@1 {
294*4882a593Smuzhiyun			label = "U-Boot";
295*4882a593Smuzhiyun			reg = <0x00010000 0x00080000>;
296*4882a593Smuzhiyun			read-only;
297*4882a593Smuzhiyun		};
298*4882a593Smuzhiyun		partition@2 {
299*4882a593Smuzhiyun			label = "U-Boot-Env";
300*4882a593Smuzhiyun			reg = <0x00090000 0x00010000>;
301*4882a593Smuzhiyun			read-only;
302*4882a593Smuzhiyun		};
303*4882a593Smuzhiyun		partition@3 {
304*4882a593Smuzhiyun			label = "Kernel";
305*4882a593Smuzhiyun			reg = <0x000a0000 0x00280000>;
306*4882a593Smuzhiyun		};
307*4882a593Smuzhiyun		partition@4 {
308*4882a593Smuzhiyun			label = "Filesystem";
309*4882a593Smuzhiyun			reg = <0x00320000 0x00400000>;
310*4882a593Smuzhiyun		};
311*4882a593Smuzhiyun		partition@5 {
312*4882a593Smuzhiyun			label = "MAC-Address";
313*4882a593Smuzhiyun			reg = <0x007f0000 0x00010000>;
314*4882a593Smuzhiyun			read-only;
315*4882a593Smuzhiyun		};
316*4882a593Smuzhiyun	};
317*4882a593Smuzhiyun};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun&mdio {
320*4882a593Smuzhiyun	status = "okay";
321*4882a593Smuzhiyun	pinctrl-names = "default";
322*4882a593Smuzhiyun	pinctrl-0 = <&mdio_pins>;
323*4882a593Smuzhiyun	bus_freq = <2200000>;
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&eth0 {
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&mii_pins>;
330*4882a593Smuzhiyun};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun&gpio {
333*4882a593Smuzhiyun	status = "okay";
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun/include/ "tps6507x.dtsi"
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&tps {
339*4882a593Smuzhiyun	vdcdc1_2-supply = <&vbat>;
340*4882a593Smuzhiyun	vdcdc3-supply = <&vbat>;
341*4882a593Smuzhiyun	vldo1_2-supply = <&vbat>;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun	regulators {
344*4882a593Smuzhiyun		vdcdc1_reg: regulator@0 {
345*4882a593Smuzhiyun			regulator-name = "VDCDC1_3.3V";
346*4882a593Smuzhiyun			regulator-min-microvolt = <3150000>;
347*4882a593Smuzhiyun			regulator-max-microvolt = <3450000>;
348*4882a593Smuzhiyun			regulator-always-on;
349*4882a593Smuzhiyun			regulator-boot-on;
350*4882a593Smuzhiyun		};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun		vdcdc2_reg: regulator@1 {
353*4882a593Smuzhiyun			regulator-name = "VDCDC2_3.3V";
354*4882a593Smuzhiyun			regulator-min-microvolt = <1710000>;
355*4882a593Smuzhiyun			regulator-max-microvolt = <3450000>;
356*4882a593Smuzhiyun			regulator-always-on;
357*4882a593Smuzhiyun			regulator-boot-on;
358*4882a593Smuzhiyun			ti,defdcdc_default = <1>;
359*4882a593Smuzhiyun		};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun		vdcdc3_reg: regulator@2 {
362*4882a593Smuzhiyun			regulator-name = "VDCDC3_1.2V";
363*4882a593Smuzhiyun			regulator-min-microvolt = <950000>;
364*4882a593Smuzhiyun			regulator-max-microvolt = <1350000>;
365*4882a593Smuzhiyun			regulator-always-on;
366*4882a593Smuzhiyun			regulator-boot-on;
367*4882a593Smuzhiyun			ti,defdcdc_default = <1>;
368*4882a593Smuzhiyun		};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun		ldo1_reg: regulator@3 {
371*4882a593Smuzhiyun			regulator-name = "LDO1_1.8V";
372*4882a593Smuzhiyun			regulator-min-microvolt = <1710000>;
373*4882a593Smuzhiyun			regulator-max-microvolt = <1890000>;
374*4882a593Smuzhiyun			regulator-always-on;
375*4882a593Smuzhiyun			regulator-boot-on;
376*4882a593Smuzhiyun		};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun		ldo2_reg: regulator@4 {
379*4882a593Smuzhiyun			regulator-name = "LDO2_1.2V";
380*4882a593Smuzhiyun			regulator-min-microvolt = <1140000>;
381*4882a593Smuzhiyun			regulator-max-microvolt = <1320000>;
382*4882a593Smuzhiyun			regulator-always-on;
383*4882a593Smuzhiyun			regulator-boot-on;
384*4882a593Smuzhiyun		};
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&mcasp0 {
389*4882a593Smuzhiyun	#sound-dai-cells = <0>;
390*4882a593Smuzhiyun	status = "okay";
391*4882a593Smuzhiyun	pinctrl-names = "default";
392*4882a593Smuzhiyun	pinctrl-0 = <&mcasp0_pins>;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun	op-mode = <0>;          /* MCASP_IIS_MODE */
395*4882a593Smuzhiyun	tdm-slots = <2>;
396*4882a593Smuzhiyun	/* 4 serializer */
397*4882a593Smuzhiyun	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
398*4882a593Smuzhiyun		0 0 0 0
399*4882a593Smuzhiyun		0 0 0 0
400*4882a593Smuzhiyun		0 0 0 1
401*4882a593Smuzhiyun		2 0 0 0
402*4882a593Smuzhiyun	>;
403*4882a593Smuzhiyun	tx-num-evt = <32>;
404*4882a593Smuzhiyun	rx-num-evt = <32>;
405*4882a593Smuzhiyun};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun&edma0 {
408*4882a593Smuzhiyun	ti,edma-reserved-slot-ranges = <32 50>;
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun&edma1 {
412*4882a593Smuzhiyun	ti,edma-reserved-slot-ranges = <32 90>;
413*4882a593Smuzhiyun};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun&aemif {
416*4882a593Smuzhiyun	pinctrl-names = "default";
417*4882a593Smuzhiyun	pinctrl-0 = <&nand_pins>;
418*4882a593Smuzhiyun	status = "ok";
419*4882a593Smuzhiyun	cs3 {
420*4882a593Smuzhiyun		#address-cells = <2>;
421*4882a593Smuzhiyun		#size-cells = <1>;
422*4882a593Smuzhiyun		clock-ranges;
423*4882a593Smuzhiyun		ranges;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun		ti,cs-chipselect = <3>;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun		nand@2000000,0 {
428*4882a593Smuzhiyun			compatible = "ti,davinci-nand";
429*4882a593Smuzhiyun			#address-cells = <1>;
430*4882a593Smuzhiyun			#size-cells = <1>;
431*4882a593Smuzhiyun			reg = <0 0x02000000 0x02000000
432*4882a593Smuzhiyun			       1 0x00000000 0x00008000>;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun			ti,davinci-chipselect = <1>;
435*4882a593Smuzhiyun			ti,davinci-mask-ale = <0>;
436*4882a593Smuzhiyun			ti,davinci-mask-cle = <0>;
437*4882a593Smuzhiyun			ti,davinci-mask-chipsel = <0>;
438*4882a593Smuzhiyun			ti,davinci-ecc-mode = "hw";
439*4882a593Smuzhiyun			ti,davinci-ecc-bits = <4>;
440*4882a593Smuzhiyun			ti,davinci-nand-use-bbt;
441*4882a593Smuzhiyun		};
442*4882a593Smuzhiyun	};
443*4882a593Smuzhiyun};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun&usb_phy {
446*4882a593Smuzhiyun	status = "okay";
447*4882a593Smuzhiyun};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun&usb0 {
450*4882a593Smuzhiyun	status = "okay";
451*4882a593Smuzhiyun};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun&usb1 {
454*4882a593Smuzhiyun	status = "okay";
455*4882a593Smuzhiyun};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun&vpif {
458*4882a593Smuzhiyun	pinctrl-names = "default";
459*4882a593Smuzhiyun	pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
460*4882a593Smuzhiyun	/*
461*4882a593Smuzhiyun	 * The vpif and the LCD are mutually exclusive.
462*4882a593Smuzhiyun	 * To enable VPIF, disable the ti,tilcdc,panel then
463*4882a593Smuzhiyun	 * change the status below to 'okay'
464*4882a593Smuzhiyun	 */
465*4882a593Smuzhiyun	status = "disabled";
466*4882a593Smuzhiyun};
467