1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2005 Simtec Electronics 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/ 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * ANUBIS - CPLD control constants 8*4882a593Smuzhiyun * ANUBIS - IRQ Number definitions 9*4882a593Smuzhiyun * ANUBIS - Memory map definitions 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __MACH_S3C24XX_ANUBIS_H 13*4882a593Smuzhiyun #define __MACH_S3C24XX_ANUBIS_H __FILE__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* CTRL2 - NAND WP control, IDE Reset assert/check */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ANUBIS_CTRL1_NANDSEL (0x3) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* IDREG - revision */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define ANUBIS_IDREG_REVMASK (0x7) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* irq */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ANUBIS_IRQ_IDE0 IRQ_EINT2 26*4882a593Smuzhiyun #define ANUBIS_IRQ_IDE1 IRQ_EINT3 27*4882a593Smuzhiyun #define ANUBIS_IRQ_ASIX IRQ_EINT1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* map */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* start peripherals off after the S3C2410 */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* we put the CPLD registers next, to get them out of the way */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) 40*4882a593Smuzhiyun #define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) 43*4882a593Smuzhiyun #define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) 46*4882a593Smuzhiyun #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) 47*4882a593Smuzhiyun #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) 48*4882a593Smuzhiyun #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* __MACH_S3C24XX_ANUBIS_H */ 51