1 /* 2 * Copyright 2013-2015 Arcturus Networks, Inc. 3 * http://www.arcturusnetworks.com/products/ucp1020/ 4 * based on include/configs/p1_p2_rdb_pc.h 5 * original copyright follows: 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * QorIQ uCP1020-xx boards configuration file 13 */ 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 18 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 19 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 20 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 21 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 22 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 23 24 #if defined(CONFIG_TARTGET_UCP1020T1) 25 26 #define CONFIG_UCP1020_REV_1_3 27 28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" 29 30 #define CONFIG_TSEC_ENET 31 #define CONFIG_TSEC1 32 #define CONFIG_TSEC3 33 #define CONFIG_HAS_ETH0 34 #define CONFIG_HAS_ETH1 35 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF 36 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE 37 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD 38 #define CONFIG_IPADDR 10.80.41.229 39 #define CONFIG_SERVERIP 10.80.41.227 40 #define CONFIG_NETMASK 255.255.252.0 41 #define CONFIG_ETHPRIME "eTSEC3" 42 43 #ifndef CONFIG_SPI_FLASH 44 #endif 45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 46 47 #define CONFIG_SYS_L2_SIZE (256 << 10) 48 49 #define CONFIG_LAST_STAGE_INIT 50 51 #endif 52 53 #if defined(CONFIG_TARGET_UCP1020) 54 55 #define CONFIG_UCP1020 56 #define CONFIG_UCP1020_REV_1_3 57 58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" 59 60 #define CONFIG_TSEC_ENET 61 #define CONFIG_TSEC1 62 #define CONFIG_TSEC2 63 #define CONFIG_TSEC3 64 #define CONFIG_HAS_ETH0 65 #define CONFIG_HAS_ETH1 66 #define CONFIG_HAS_ETH2 67 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF 68 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE 69 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD 70 #define CONFIG_IPADDR 192.168.1.81 71 #define CONFIG_IPADDR1 192.168.1.82 72 #define CONFIG_IPADDR2 192.168.1.83 73 #define CONFIG_SERVERIP 192.168.1.80 74 #define CONFIG_GATEWAYIP 102.168.1.1 75 #define CONFIG_NETMASK 255.255.255.0 76 #define CONFIG_ETHPRIME "eTSEC1" 77 78 #ifndef CONFIG_SPI_FLASH 79 #endif 80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 81 82 #define CONFIG_SYS_L2_SIZE (256 << 10) 83 84 #define CONFIG_LAST_STAGE_INIT 85 86 #endif 87 88 #ifdef CONFIG_SDCARD 89 #define CONFIG_RAMBOOT_SDCARD 90 #define CONFIG_SYS_RAMBOOT 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_TEXT_BASE 0x11000000 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 94 #endif 95 96 #ifdef CONFIG_SPIFLASH 97 #define CONFIG_RAMBOOT_SPIFLASH 98 #define CONFIG_SYS_RAMBOOT 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_SYS_TEXT_BASE 0x11000000 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 102 #endif 103 104 #ifndef CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_TEXT_BASE 0xeff80000 106 #endif 107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 108 109 #ifndef CONFIG_RESET_VECTOR_ADDRESS 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 111 #endif 112 113 #ifndef CONFIG_SYS_MONITOR_BASE 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 115 #endif 116 117 #define CONFIG_MP 118 119 #define CONFIG_ENV_OVERWRITE 120 121 #define CONFIG_SATA_SIL 122 #define CONFIG_SYS_SATA_MAX_DEVICE 2 123 #define CONFIG_LIBATA 124 #define CONFIG_LBA48 125 126 #define CONFIG_SYS_CLK_FREQ 66666666 127 #define CONFIG_DDR_CLK_FREQ 66666666 128 129 #define CONFIG_HWCONFIG 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_L2_CACHE 135 #define CONFIG_BTB 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 141 142 #define CONFIG_SYS_CCSRBAR 0xffe00000 143 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 144 145 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 146 SPL code*/ 147 #ifdef CONFIG_SPL_BUILD 148 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 149 #endif 150 151 /* DDR Setup */ 152 #define CONFIG_DDR_ECC_ENABLE 153 #ifndef CONFIG_DDR_ECC_ENABLE 154 #define CONFIG_SYS_DDR_RAW_TIMING 155 #define CONFIG_DDR_SPD 156 #endif 157 #define CONFIG_SYS_SPD_BUS_NUM 1 158 #undef CONFIG_FSL_DDR_INTERACTIVE 159 160 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 161 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 162 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 163 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 166 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 167 168 /* Default settings for DDR3 */ 169 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 170 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 171 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 172 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 173 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 174 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 175 176 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 177 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 178 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 179 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 180 181 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 182 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 183 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 184 #define CONFIG_SYS_DDR_RCW_1 0x00000000 185 #define CONFIG_SYS_DDR_RCW_2 0x00000000 186 #ifdef CONFIG_DDR_ECC_ENABLE 187 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ 188 #else 189 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 190 #endif 191 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 192 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 193 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 194 195 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 196 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 197 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 198 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 199 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 200 #define CONFIG_SYS_DDR_MODE_1 0x40461520 201 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 202 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 203 204 #undef CONFIG_CLOCKS_IN_MHZ 205 206 /* 207 * Memory map 208 * 209 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 210 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) 211 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 212 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable 213 * (early boot only) 214 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 215 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 216 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 217 */ 218 219 /* 220 * Local Bus Definitions 221 */ 222 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 223 #define CONFIG_SYS_FLASH_BASE 0xec000000 224 225 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 226 227 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 228 | BR_PS_16 | BR_V) 229 230 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 231 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 233 #define CONFIG_SYS_FLASH_QUIET_TEST 234 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 235 236 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 237 238 #undef CONFIG_SYS_FLASH_CHECKSUM 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 242 #define CONFIG_FLASH_CFI_DRIVER 243 #define CONFIG_SYS_FLASH_CFI 244 #define CONFIG_SYS_FLASH_EMPTY_INFO 245 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 246 247 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 248 249 #define CONFIG_SYS_INIT_RAM_LOCK 250 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 251 /* Initial L1 address */ 252 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 254 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 255 /* Size of used area in RAM */ 256 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 257 258 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 259 GENERATED_GBL_DATA_SIZE) 260 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 261 262 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ 263 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 264 265 #define CONFIG_SYS_PMC_BASE 0xff980000 266 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 267 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 268 BR_PS_8 | BR_V) 269 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 270 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 271 OR_GPCM_EAD) 272 273 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 274 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 275 #ifdef CONFIG_NAND_FSL_ELBC 276 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 277 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 278 #endif 279 280 /* Serial Port - controlled on board with jumper J8 281 * open - index 2 282 * shorted - index 1 283 */ 284 #define CONFIG_CONS_INDEX 1 285 #undef CONFIG_SERIAL_SOFTWARE_FIFO 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 290 #define CONFIG_NS16550_MIN_FUNCTIONS 291 #endif 292 293 #define CONFIG_SYS_BAUDRATE_TABLE \ 294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 295 296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 298 299 /* I2C */ 300 #define CONFIG_SYS_I2C 301 #define CONFIG_SYS_I2C_FSL 302 #define CONFIG_SYS_FSL_I2C_SPEED 400000 303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 305 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 306 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 307 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 308 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 309 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 310 311 #define CONFIG_RTC_DS1337 312 #define CONFIG_RTC_DS1337_NOOSC 313 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 314 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 315 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C 316 #define CONFIG_SYS_I2C_IDT6V49205B 0x69 317 318 /* 319 * eSPI - Enhanced SPI 320 */ 321 #define CONFIG_HARD_SPI 322 323 #define CONFIG_SF_DEFAULT_SPEED 10000000 324 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 325 326 #if defined(CONFIG_PCI) 327 /* 328 * General PCI 329 * Memory space is mapped 1-1, but I/O space must start from 0. 330 */ 331 332 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 333 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" 334 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 335 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 336 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 337 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 338 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 339 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 340 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 341 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 342 343 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 344 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" 345 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 346 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 347 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 348 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 349 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 350 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 351 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 352 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 353 354 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 355 #endif /* CONFIG_PCI */ 356 357 /* 358 * Environment 359 */ 360 #ifdef CONFIG_ENV_FIT_UCBOOT 361 362 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) 363 #define CONFIG_ENV_SIZE 0x20000 364 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 365 366 #else 367 368 #define CONFIG_ENV_SPI_BUS 0 369 #define CONFIG_ENV_SPI_CS 0 370 #define CONFIG_ENV_SPI_MAX_HZ 10000000 371 #define CONFIG_ENV_SPI_MODE 0 372 373 #ifdef CONFIG_RAMBOOT_SPIFLASH 374 375 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */ 376 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ 377 #define CONFIG_ENV_SECT_SIZE 0x1000 378 379 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 380 /* Address and size of Redundant Environment Sector */ 381 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 382 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 383 #endif 384 385 #elif defined(CONFIG_RAMBOOT_SDCARD) 386 #define CONFIG_FSL_FIXED_MMC_LOCATION 387 #define CONFIG_ENV_SIZE 0x2000 388 #define CONFIG_SYS_MMC_ENV_DEV 0 389 390 #elif defined(CONFIG_SYS_RAMBOOT) 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 392 #define CONFIG_ENV_SIZE 0x2000 393 394 #else 395 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) 396 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 397 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 398 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) 399 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) 400 /* Address and size of Redundant Environment Sector */ 401 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 402 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 403 #endif 404 405 #endif 406 407 #endif /* CONFIG_ENV_FIT_UCBOOT */ 408 409 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 410 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 411 412 /* 413 * USB 414 */ 415 #define CONFIG_HAS_FSL_DR_USB 416 417 #if defined(CONFIG_HAS_FSL_DR_USB) 418 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 419 420 #ifdef CONFIG_USB_EHCI_HCD 421 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 422 #define CONFIG_USB_EHCI_FSL 423 #endif 424 #endif 425 426 #undef CONFIG_WATCHDOG /* watchdog disabled */ 427 428 #ifdef CONFIG_MMC 429 #define CONFIG_FSL_ESDHC 430 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 431 #define CONFIG_MMC_SPI 432 #endif 433 434 /* Misc Extra Settings */ 435 #undef CONFIG_WATCHDOG /* watchdog disabled */ 436 437 /* 438 * Miscellaneous configurable options 439 */ 440 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 441 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 442 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 443 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ 444 445 /* 446 * For booting Linux, the board info and command line data 447 * have to be in the first 64 MB of memory, since this is 448 * the maximum mapped by the Linux kernel during initialization. 449 */ 450 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 451 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 452 453 #if defined(CONFIG_CMD_KGDB) 454 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 455 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 456 #endif 457 458 /* 459 * Environment Configuration 460 */ 461 462 #if defined(CONFIG_TSEC_ENET) 463 464 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) 465 #else 466 #error "UCP1020 module revision is not defined !!!" 467 #endif 468 469 #define CONFIG_BOOTP_SERVERIP 470 471 #define CONFIG_MII /* MII PHY management */ 472 #define CONFIG_TSEC1_NAME "eTSEC1" 473 #define CONFIG_TSEC2_NAME "eTSEC2" 474 #define CONFIG_TSEC3_NAME "eTSEC3" 475 476 #define TSEC1_PHY_ADDR 4 477 #define TSEC2_PHY_ADDR 0 478 #define TSEC2_PHY_ADDR_SGMII 0x00 479 #define TSEC3_PHY_ADDR 6 480 481 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 482 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 483 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 484 485 #define TSEC1_PHYIDX 0 486 #define TSEC2_PHYIDX 0 487 #define TSEC3_PHYIDX 0 488 489 #endif 490 491 #define CONFIG_HOSTNAME UCP1020 492 #define CONFIG_ROOTPATH "/opt/nfsroot" 493 #define CONFIG_BOOTFILE "uImage" 494 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 495 496 /* default location for tftp and bootm */ 497 #define CONFIG_LOADADDR 1000000 498 499 #if defined(CONFIG_DONGLE) 500 501 #define CONFIG_EXTRA_ENV_SETTINGS \ 502 "bootcmd=run prog_spi_mbrbootcramfs\0" \ 503 "bootfile=uImage\0" \ 504 "consoledev=ttyS0\0" \ 505 "cramfsfile=image.cramfs\0" \ 506 "dtbaddr=0x00c00000\0" \ 507 "dtbfile=image.dtb\0" \ 508 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 509 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 510 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 511 "fileaddr=0x01000000\0" \ 512 "filesize=0x00080000\0" \ 513 "flashmbr=sf probe 0; " \ 514 "tftp $loadaddr $mbr; " \ 515 "sf erase $mbr_offset +$filesize; " \ 516 "sf write $loadaddr $mbr_offset $filesize\0" \ 517 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 518 "protect off $nor_recoveryaddr +$filesize; " \ 519 "erase $nor_recoveryaddr +$filesize; " \ 520 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 521 "protect on $nor_recoveryaddr +$filesize\0 " \ 522 "flashuboot=tftp $ubootaddr $ubootfile; " \ 523 "protect off $nor_ubootaddr +$filesize; " \ 524 "erase $nor_ubootaddr +$filesize; " \ 525 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 526 "protect on $nor_ubootaddr +$filesize\0 " \ 527 "flashworking=tftp $workingaddr $cramfsfile; " \ 528 "protect off $nor_workingaddr +$filesize; " \ 529 "erase $nor_workingaddr +$filesize; " \ 530 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 531 "protect on $nor_workingaddr +$filesize\0 " \ 532 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 533 "kerneladdr=0x01100000\0" \ 534 "kernelfile=uImage\0" \ 535 "loadaddr=0x01000000\0" \ 536 "mbr=uCP1020d.mbr\0" \ 537 "mbr_offset=0x00000000\0" \ 538 "mmbr=uCP1020Quiet.mbr\0" \ 539 "mmcpart=0:2\0" \ 540 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 541 "mmc erase 1 1; " \ 542 "mmc write $loadaddr 1 1\0" \ 543 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ 544 "mmc erase 0x40 0x400; " \ 545 "mmc write $loadaddr 0x40 0x400\0" \ 546 "netdev=eth0\0" \ 547 "nor_recoveryaddr=0xEC0A0000\0" \ 548 "nor_ubootaddr=0xEFF80000\0" \ 549 "nor_workingaddr=0xECFA0000\0" \ 550 "norbootrecovery=setenv bootargs $recoverybootargs" \ 551 " console=$consoledev,$baudrate $othbootargs; " \ 552 "run norloadrecovery; " \ 553 "bootm $kerneladdr - $dtbaddr\0" \ 554 "norbootworking=setenv bootargs $workingbootargs" \ 555 " console=$consoledev,$baudrate $othbootargs; " \ 556 "run norloadworking; " \ 557 "bootm $kerneladdr - $dtbaddr\0" \ 558 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 559 "setenv cramfsaddr $nor_recoveryaddr; " \ 560 "cramfsload $dtbaddr $dtbfile; " \ 561 "cramfsload $kerneladdr $kernelfile\0" \ 562 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 563 "setenv cramfsaddr $nor_workingaddr; " \ 564 "cramfsload $dtbaddr $dtbfile; " \ 565 "cramfsload $kerneladdr $kernelfile\0" \ 566 "prog_spi_mbr=run spi__mbr\0" \ 567 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ 568 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ 569 "run spi__cramfs\0" \ 570 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 571 " console=$consoledev,$baudrate $othbootargs; " \ 572 "tftp $rootfsaddr $rootfsfile; " \ 573 "tftp $loadaddr $kernelfile; " \ 574 "tftp $dtbaddr $dtbfile; " \ 575 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 576 "ramdisk_size=120000\0" \ 577 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 578 "recoveryaddr=0x02F00000\0" \ 579 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 580 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 581 "mw.l 0xffe0f008 0x00400000\0" \ 582 "rootfsaddr=0x02F00000\0" \ 583 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 584 "rootpath=/opt/nfsroot\0" \ 585 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 586 "protect off 0xeC000000 +$filesize; " \ 587 "erase 0xEC000000 +$filesize; " \ 588 "cp.b $loadaddr 0xEC000000 $filesize; " \ 589 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 590 "protect on 0xeC000000 +$filesize\0" \ 591 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 592 "protect off 0xeFF80000 +$filesize; " \ 593 "erase 0xEFF80000 +$filesize; " \ 594 "cp.b $loadaddr 0xEFF80000 $filesize; " \ 595 "cmp.b $loadaddr 0xEFF80000 $filesize; " \ 596 "protect on 0xeFF80000 +$filesize\0" \ 597 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ 598 "sf probe 0; sf erase 0x8000 +$filesize; " \ 599 "sf write $loadaddr 0x8000 $filesize\0" \ 600 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ 601 "protect off 0xec0a0000 +$filesize; " \ 602 "erase 0xeC0A0000 +$filesize; " \ 603 "cp.b $loadaddr 0xeC0A0000 $filesize; " \ 604 "protect on 0xec0a0000 +$filesize\0" \ 605 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 606 "sf probe 1; sf erase 0 +$filesize; " \ 607 "sf write $loadaddr 0 $filesize\0" \ 608 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ 609 "sf probe 0; sf erase 0 +$filesize; " \ 610 "sf write $loadaddr 0 $filesize\0" \ 611 "tftpflash=tftpboot $loadaddr $uboot; " \ 612 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 613 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 614 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 615 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 616 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 617 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 618 "ubootaddr=0x01000000\0" \ 619 "ubootfile=u-boot.bin\0" \ 620 "ubootd=u-boot4dongle.bin\0" \ 621 "upgrade=run flashworking\0" \ 622 "usb_phy_type=ulpi\0 " \ 623 "workingaddr=0x02F00000\0" \ 624 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 625 626 #else 627 628 #if defined(CONFIG_UCP1020T1) 629 630 #define CONFIG_EXTRA_ENV_SETTINGS \ 631 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ 632 "bootfile=uImage\0" \ 633 "consoledev=ttyS0\0" \ 634 "cramfsfile=image.cramfs\0" \ 635 "dtbaddr=0x00c00000\0" \ 636 "dtbfile=image.dtb\0" \ 637 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 638 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 639 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 640 "fileaddr=0x01000000\0" \ 641 "filesize=0x00080000\0" \ 642 "flashmbr=sf probe 0; " \ 643 "tftp $loadaddr $mbr; " \ 644 "sf erase $mbr_offset +$filesize; " \ 645 "sf write $loadaddr $mbr_offset $filesize\0" \ 646 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \ 647 "protect off $nor_recoveryaddr +$filesize; " \ 648 "erase $nor_recoveryaddr +$filesize; " \ 649 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ 650 "protect on $nor_recoveryaddr +$filesize\0 " \ 651 "flashuboot=tftp $ubootaddr $ubootfile; " \ 652 "protect off $nor_ubootaddr +$filesize; " \ 653 "erase $nor_ubootaddr +$filesize; " \ 654 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ 655 "protect on $nor_ubootaddr +$filesize\0 " \ 656 "flashworking=tftp $workingaddr $cramfsfile; " \ 657 "protect off $nor_workingaddr +$filesize; " \ 658 "erase $nor_workingaddr +$filesize; " \ 659 "cp.b $workingaddr $nor_workingaddr $filesize; " \ 660 "protect on $nor_workingaddr +$filesize\0 " \ 661 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 662 "kerneladdr=0x01100000\0" \ 663 "kernelfile=uImage\0" \ 664 "loadaddr=0x01000000\0" \ 665 "mbr=uCP1020.mbr\0" \ 666 "mbr_offset=0x00000000\0" \ 667 "netdev=eth0\0" \ 668 "nor_recoveryaddr=0xEC0A0000\0" \ 669 "nor_ubootaddr=0xEFF80000\0" \ 670 "nor_workingaddr=0xECFA0000\0" \ 671 "norbootrecovery=setenv bootargs $recoverybootargs" \ 672 " console=$consoledev,$baudrate $othbootargs; " \ 673 "run norloadrecovery; " \ 674 "bootm $kerneladdr - $dtbaddr\0" \ 675 "norbootworking=setenv bootargs $workingbootargs" \ 676 " console=$consoledev,$baudrate $othbootargs; " \ 677 "run norloadworking; " \ 678 "bootm $kerneladdr - $dtbaddr\0" \ 679 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ 680 "setenv cramfsaddr $nor_recoveryaddr; " \ 681 "cramfsload $dtbaddr $dtbfile; " \ 682 "cramfsload $kerneladdr $kernelfile\0" \ 683 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ 684 "setenv cramfsaddr $nor_workingaddr; " \ 685 "cramfsload $dtbaddr $dtbfile; " \ 686 "cramfsload $kerneladdr $kernelfile\0" \ 687 "othbootargs=quiet\0" \ 688 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 689 " console=$consoledev,$baudrate $othbootargs; " \ 690 "tftp $rootfsaddr $rootfsfile; " \ 691 "tftp $loadaddr $kernelfile; " \ 692 "tftp $dtbaddr $dtbfile; " \ 693 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 694 "ramdisk_size=120000\0" \ 695 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 696 "recoveryaddr=0x02F00000\0" \ 697 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ 698 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 699 "mw.l 0xffe0f008 0x00400000\0" \ 700 "rootfsaddr=0x02F00000\0" \ 701 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 702 "rootpath=/opt/nfsroot\0" \ 703 "silent=1\0" \ 704 "tftpflash=tftpboot $loadaddr $uboot; " \ 705 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 706 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 707 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 708 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 709 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 710 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 711 "ubootaddr=0x01000000\0" \ 712 "ubootfile=u-boot.bin\0" \ 713 "upgrade=run flashworking\0" \ 714 "workingaddr=0x02F00000\0" \ 715 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" 716 717 #else /* For Arcturus Modules */ 718 719 #define CONFIG_EXTRA_ENV_SETTINGS \ 720 "bootcmd=run norkernel\0" \ 721 "bootfile=uImage\0" \ 722 "consoledev=ttyS0\0" \ 723 "dtbaddr=0x00c00000\0" \ 724 "dtbfile=image.dtb\0" \ 725 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ 726 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ 727 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ 728 "fileaddr=0x01000000\0" \ 729 "filesize=0x00080000\0" \ 730 "flashmbr=sf probe 0; " \ 731 "tftp $loadaddr $mbr; " \ 732 "sf erase $mbr_offset +$filesize; " \ 733 "sf write $loadaddr $mbr_offset $filesize\0" \ 734 "flashuboot=tftp $loadaddr $ubootfile; " \ 735 "protect off $nor_ubootaddr0 +$filesize; " \ 736 "erase $nor_ubootaddr0 +$filesize; " \ 737 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ 738 "protect on $nor_ubootaddr0 +$filesize; " \ 739 "protect off $nor_ubootaddr1 +$filesize; " \ 740 "erase $nor_ubootaddr1 +$filesize; " \ 741 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ 742 "protect on $nor_ubootaddr1 +$filesize\0 " \ 743 "format0=protect off $part0base +$part0size; " \ 744 "erase $part0base +$part0size\0" \ 745 "format1=protect off $part1base +$part1size; " \ 746 "erase $part1base +$part1size\0" \ 747 "format2=protect off $part2base +$part2size; " \ 748 "erase $part2base +$part2size\0" \ 749 "format3=protect off $part3base +$part3size; " \ 750 "erase $part3base +$part3size\0" \ 751 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ 752 "kerneladdr=0x01100000\0" \ 753 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ 754 "kernelfile=uImage\0" \ 755 "loadaddr=0x01000000\0" \ 756 "mbr=uCP1020.mbr\0" \ 757 "mbr_offset=0x00000000\0" \ 758 "netdev=eth0\0" \ 759 "nor_ubootaddr0=0xEC000000\0" \ 760 "nor_ubootaddr1=0xEFF80000\0" \ 761 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ 762 "run norkernelload; " \ 763 "bootm $kerneladdr - $dtbaddr\0" \ 764 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ 765 "setenv cramfsaddr $part0base; " \ 766 "cramfsload $dtbaddr $dtbfile; " \ 767 "cramfsload $kerneladdr $kernelfile\0" \ 768 "part0base=0xEC100000\0" \ 769 "part0size=0x00700000\0" \ 770 "part1base=0xEC800000\0" \ 771 "part1size=0x02000000\0" \ 772 "part2base=0xEE800000\0" \ 773 "part2size=0x00800000\0" \ 774 "part3base=0xEF000000\0" \ 775 "part3size=0x00F80000\0" \ 776 "partENVbase=0xEC080000\0" \ 777 "partENVsize=0x00080000\0" \ 778 "program0=tftp part0-000000.bin; " \ 779 "protect off $part0base +$filesize; " \ 780 "erase $part0base +$filesize; " \ 781 "cp.b $loadaddr $part0base $filesize; " \ 782 "echo Verifying...; " \ 783 "cmp.b $loadaddr $part0base $filesize\0" \ 784 "program1=tftp part1-000000.bin; " \ 785 "protect off $part1base +$filesize; " \ 786 "erase $part1base +$filesize; " \ 787 "cp.b $loadaddr $part1base $filesize; " \ 788 "echo Verifying...; " \ 789 "cmp.b $loadaddr $part1base $filesize\0" \ 790 "program2=tftp part2-000000.bin; " \ 791 "protect off $part2base +$filesize; " \ 792 "erase $part2base +$filesize; " \ 793 "cp.b $loadaddr $part2base $filesize; " \ 794 "echo Verifying...; " \ 795 "cmp.b $loadaddr $part2base $filesize\0" \ 796 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ 797 " console=$consoledev,$baudrate $othbootargs; " \ 798 "tftp $rootfsaddr $rootfsfile; " \ 799 "tftp $loadaddr $kernelfile; " \ 800 "tftp $dtbaddr $dtbfile; " \ 801 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ 802 "ramdisk_size=120000\0" \ 803 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 804 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ 805 "mw.l 0xffe0f008 0x00400000\0" \ 806 "rootfsaddr=0x02F00000\0" \ 807 "rootfsfile=rootfs.ext2.gz.uboot\0" \ 808 "rootpath=/opt/nfsroot\0" \ 809 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ 810 "sf probe 0; sf erase 0 +$filesize; " \ 811 "sf write $loadaddr 0 $filesize\0" \ 812 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ 813 "protect off 0xeC000000 +$filesize; " \ 814 "erase 0xEC000000 +$filesize; " \ 815 "cp.b $loadaddr 0xEC000000 $filesize; " \ 816 "cmp.b $loadaddr 0xEC000000 $filesize; " \ 817 "protect on 0xeC000000 +$filesize\0" \ 818 "tftpflash=tftpboot $loadaddr $uboot; " \ 819 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 820 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 821 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ 822 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ 823 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ 824 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ 825 "ubootfile=u-boot.bin\0" \ 826 "upgrade=run flashuboot\0" \ 827 "usb_phy_type=ulpi\0 " \ 828 "boot_nfs= " \ 829 "setenv bootargs root=/dev/nfs rw " \ 830 "nfsroot=$serverip:$rootpath " \ 831 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $loadaddr $bootfile;" \ 834 "tftp $fdtaddr $fdtfile;" \ 835 "bootm $loadaddr - $fdtaddr\0" \ 836 "boot_hd = " \ 837 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "usb start;" \ 840 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 841 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 842 "bootm $loadaddr - $fdtaddr\0" \ 843 "boot_usb_fat = " \ 844 "setenv bootargs root=/dev/ram rw " \ 845 "console=$consoledev,$baudrate $othbootargs " \ 846 "ramdisk_size=$ramdisk_size;" \ 847 "usb start;" \ 848 "fatload usb 0:2 $loadaddr $bootfile;" \ 849 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 850 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 851 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 852 "boot_usb_ext2 = " \ 853 "setenv bootargs root=/dev/ram rw " \ 854 "console=$consoledev,$baudrate $othbootargs " \ 855 "ramdisk_size=$ramdisk_size;" \ 856 "usb start;" \ 857 "ext2load usb 0:4 $loadaddr $bootfile;" \ 858 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 859 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 860 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ 861 "boot_nor = " \ 862 "setenv bootargs root=/dev/$jffs2nor rw " \ 863 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 864 "bootm $norbootaddr - $norfdtaddr\0 " \ 865 "boot_ram = " \ 866 "setenv bootargs root=/dev/ram rw " \ 867 "console=$consoledev,$baudrate $othbootargs " \ 868 "ramdisk_size=$ramdisk_size;" \ 869 "tftp $ramdiskaddr $ramdiskfile;" \ 870 "tftp $loadaddr $bootfile;" \ 871 "tftp $fdtaddr $fdtfile;" \ 872 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" 873 874 #endif 875 #endif 876 877 #endif /* __CONFIG_H */ 878