feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to

feat(fvp): scale SP_MIN max size based on SRAM size

The maximum size for SP_MIN in the FVP is currently
fixed and does not scale with the SRAM size.
This update adjusts the SP_MIN size according to
the SRAM size used to build the FVP platform.

Change-Id: I95527e8ae6f8a73c336ed4fe05ace5de86d8991d
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(checkpatch): detect issues in commit message" into integration

Merge "feat(mediatek): change log level from INFO to VERBOSE" into integration

fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source

Currently, PMC_GPIO device node was not mapped with interrupt number
during the setup of wakeup source while suspending. As a res

fix(xilinx): map PMC_GPIO device node to interrupt for wakeup source

Currently, PMC_GPIO device node was not mapped with interrupt number
during the setup of wakeup source while suspending. As a result,
system cannot resume using PMC_GPIO as wakeup source.

To address this issue, add an entry for PMC_GPIO node to map with its
corresponding interrupt number.

Change-Id: Ic681b7b2e7c0b3bd542c8e4664a2129e4b91c459
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(mediatek): change log level from INFO to VERBOSE

This change aims to reduce unnecessary information in the default log
output, so change to use VERBOSE.

Change-Id: I80ea57cd4164bdcef915db5392a

feat(mediatek): change log level from INFO to VERBOSE

This change aims to reduce unnecessary information in the default log
output, so change to use VERBOSE.

Change-Id: I80ea57cd4164bdcef915db5392a63ae8982a634f
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge changes If374b491,I6b63b9c6 into integration

* changes:
fix(qemu): exclude GPT reserve from BL32_MEM_SIZE
fix(qemu): fix L0 GPT page table mapping

build: allow multiple toolchain defaults

This change enables a fairly commonly-requested use-case, which is to
fall back to the host system's native toolchain when building on AArch64
if the bare-me

build: allow multiple toolchain defaults

This change enables a fairly commonly-requested use-case, which is to
fall back to the host system's native toolchain when building on AArch64
if the bare-metal toolchain is not available.

In this situation, if the `aarch64-none-elf` GCC toolchain cannot be
located, the build system will look for `aarch64-linux-gnu` before
giving up.

Change-Id: I39d2a8837b651b28cf0eafa92f6003a7f66767a0
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: determine toolchain tools dynamically

Since the introduction of the toolchain detection framework into the
build system, we have done determination and identification of the
toolchain(s) used

build: determine toolchain tools dynamically

Since the introduction of the toolchain detection framework into the
build system, we have done determination and identification of the
toolchain(s) used for the build at the initialization of the build
system.

This incurs a large cost to the build every time - for every toolchain
that has been requested by the current makefile, we try to identify each
tool in the list of known tool classes, even if that tool doesn't
actually see any use.

For the clean and check-like targets we worked around this by disabling
most of the toolchains if we detect these targets, but this is
inflexible and not very reliable, and it still means that when building
normal targets we are incurring that cost for all tools whether they are
used or not.

This change instead modifies the toolchain detection framework to only
initialize a tool for a given toolchain when it is first used. This does
mean that we can no longer warn about an incorrectly-configured
toolchain at the beginning of build system invocation, but it has the
advantage of substantially reducing build time and the complexity of
*using* the framework (at the cost of an increase in complexity in the
framework itself).

Change-Id: I7f3d06b2eb58c1b26a846791a13b0037f32c8013
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(arm): add extra hash config to validate ROTPK" into integration

fix(arm): add extra hash config to validate ROTPK

The default mbedTLS configuration enables hash algorithms based on
the HASH_ALG or MBOOT_EL_HASH_ALG selected. However, the Arm ROTPK
is always embe

fix(arm): add extra hash config to validate ROTPK

The default mbedTLS configuration enables hash algorithms based on
the HASH_ALG or MBOOT_EL_HASH_ALG selected. However, the Arm ROTPK
is always embedded as a SHA256 hash in BL1 and BL2. In the future,
we may need to adjust this to use the HASH_ALG algorithm for
embedding the ROTPK hash.

As a temporary workaround, a separate mbedTLS configuration has
been created for Arm platforms to explicitly set SHA256 defines,
rather than relying on the default configuration. This adjustment
is reflected in the mbedTLS configuration file for the TC platform
as well as in the PSA Crypto configuration file.

Change-Id: Ib3128ce7b0fb5c0858624ecbc998d456968beddf
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(versal2): implement USB_SET_STATE dummy IOCTL" into integration

Merge "fix(gicv3): fix GITS_CTLR.Quiescent bit definition" into integration

fix(gicv3): fix GITS_CTLR.Quiescent bit definition

GITS_CTLR.Quiescent is bit31, not bit1.
So fix GITS_CTLR_QUIESCENT_BIT to BIT32(31).

Change-Id: Ic16a52e0c4e557d68a8128ccc7e7a0f1a316a23b
Signed-o

fix(gicv3): fix GITS_CTLR.Quiescent bit definition

GITS_CTLR.Quiescent is bit31, not bit1.
So fix GITS_CTLR_QUIESCENT_BIT to BIT32(31).

Change-Id: Ic16a52e0c4e557d68a8128ccc7e7a0f1a316a23b
Signed-off-by: Joe Yang <magicse7en@outlook.com>

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feat(st-regulator): support regulator_set_voltage for fixed regulator

Always support the regulator_set_voltage operation for the same voltage.
This patch prepares the DDR power configuration when th

feat(st-regulator): support regulator_set_voltage for fixed regulator

Always support the regulator_set_voltage operation for the same voltage.
This patch prepares the DDR power configuration when the power supplies
are fixed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Idf032b03c6f0c95f997dec3ed8a0d38c54a3de15

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feat(st-regulator): add enable ramp-delay

Permit to override enable ramp-delay value from
the device tree in BL2.

Change-Id: Id8e803b368055a50fbd14d4527917c449b958ad9
Signed-off-by: Pascal Paillet

feat(st-regulator): add enable ramp-delay

Permit to override enable ramp-delay value from
the device tree in BL2.

Change-Id: Id8e803b368055a50fbd14d4527917c449b958ad9
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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build: properly namespace `toolchain.mk` variables

This is a simple change to ensure that everything in the `toolchain.mk`
makefile is adequately namespaced to avoid collisions.

Change-Id: I0b45966

build: properly namespace `toolchain.mk` variables

This is a simple change to ensure that everything in the `toolchain.mk`
makefile is adequately namespaced to avoid collisions.

Change-Id: I0b45966527e1a03200bbc6694fd6c7133e349314
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(st): manage BL31 FCONF load_info struct

As the file is common with STM32MP1, which is AARCH32, the BL31 entry
is put under __aarch64__ flag.

Change-Id: I1efc406717842235264dc6cc3605229659364b0

feat(st): manage BL31 FCONF load_info struct

As the file is common with STM32MP1, which is AARCH32, the BL31 entry
is put under __aarch64__ flag.

Change-Id: I1efc406717842235264dc6cc3605229659364b02
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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Merge "build: use `ar` over `gcc-ar`" into integration

Merge changes from topic "jc/tcr2_asymmetric_support" into integration

* changes:
feat(cm): handle asymmetry for FEAT_TCR2
feat(tc): make TCR2 feature asymmetric

feat(cm): handle asymmetry for FEAT_TCR2

With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. FEAT_TCR2 is one of the features which can be
asymmetric across core

feat(cm): handle asymmetry for FEAT_TCR2

With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores
can be handled. FEAT_TCR2 is one of the features which can be
asymmetric across cores and the respective support is added here.

Adding a function to handle this asymmetry by re-visting the
feature presence on running core.
There are two possible cases:
- If the primary core has the feature and secondary does not have it
then the feature is disabled.
- If the primary does not have the feature and secondary has it then,
the feature need to be enabled in secondary cores.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I73a70891d52268ddfa4effe40edf04115f5821ca

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feat(tc): make TCR2 feature asymmetric

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I6209dc46ddecaa09cc1220fe9488b3771ea6dc38

feat(versal2): implement USB_SET_STATE dummy IOCTL

USB DWC3 driver calls firmware API to set USB D0/D3 power states.
In absence of firmware driver probe these PM APIs return -ENODEV
and DWC3 driver

feat(versal2): implement USB_SET_STATE dummy IOCTL

USB DWC3 driver calls firmware API to set USB D0/D3 power states.
In absence of firmware driver probe these PM APIs return -ENODEV
and DWC3 driver probe fails. Till PLM implement these PM APIs as
a temporary workaround add dummy PM implementation in TFA.

Change-Id: I8768301524ffdc2f275221296feaa2a3ad0ad4f6
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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Merge "fix(spmd): remove spmd_handle_spmc_message" into integration

build: use `ar` over `gcc-ar`

It has been a sufficiently long time since the last release of binutils
did not automatically enable the LTO plugin. Migrate to `ar` rather than
using the `gcc-ar` buil

build: use `ar` over `gcc-ar`

It has been a sufficiently long time since the last release of binutils
did not automatically enable the LTO plugin. Migrate to `ar` rather than
using the `gcc-ar` build wrapper, which saves us some pain trying to
locate the proper archiver.

Change-Id: I6f8b895d6a470d2b7cd5b98ccb23c54b35d7ad12
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(xilinx): optimize logic to read IPI response" into integration