1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CLOCKMANAGER_H 9 #define CLOCKMANAGER_H 10 11 #include "socfpga_handoff.h" 12 13 /* Clock Manager Registers */ 14 #define CLKMGR_OFFSET 0x10d10000 15 16 #define CLKMGR_CTRL 0x0 17 #define CLKMGR_STAT 0x4 18 #define CLKMGR_TESTIOCTROL 0x8 19 #define CLKMGR_INTRGEN 0xc 20 #define CLKMGR_INTRMSK 0x10 21 #define CLKMGR_INTRCLR 0x14 22 #define CLKMGR_INTRSTS 0x18 23 #define CLKMGR_INTRSTK 0x1c 24 #define CLKMGR_INTRRAW 0x20 25 26 /* Main PLL Group */ 27 #define CLKMGR_MAINPLL 0x10d10024 28 #define CLKMGR_MAINPLL_EN 0x0 29 #define CLKMGR_MAINPLL_ENS 0x4 30 #define CLKMGR_MAINPLL_BYPASS 0xc 31 #define CLKMGR_MAINPLL_BYPASSS 0x10 32 #define CLKMGR_MAINPLL_BYPASSR 0x14 33 #define CLKMGR_MAINPLL_NOCCLK 0x1c 34 #define CLKMGR_MAINPLL_NOCDIV 0x20 35 #define CLKMGR_MAINPLL_PLLGLOB 0x24 36 #define CLKMGR_MAINPLL_FDBCK 0x28 37 #define CLKMGR_MAINPLL_MEM 0x2c 38 #define CLKMGR_MAINPLL_MEMSTAT 0x30 39 #define CLKMGR_MAINPLL_VCOCALIB 0x34 40 #define CLKMGR_MAINPLL_PLLC0 0x38 41 #define CLKMGR_MAINPLL_PLLC1 0x3c 42 #define CLKMGR_MAINPLL_PLLC2 0x40 43 #define CLKMGR_MAINPLL_PLLC3 0x44 44 #define CLKMGR_MAINPLL_PLLM 0x48 45 #define CLKMGR_MAINPLL_FHOP 0x4c 46 #define CLKMGR_MAINPLL_SSC 0x50 47 #define CLKMGR_MAINPLL_LOSTLOCK 0x54 48 49 /* Peripheral PLL Group */ 50 #define CLKMGR_PERPLL 0x10d1007c 51 #define CLKMGR_PERPLL_EN 0x0 52 #define CLKMGR_PERPLL_ENS 0x4 53 #define CLKMGR_PERPLL_BYPASS 0xc 54 #define CLKMGR_PERPLL_EMACCTL 0x18 55 #define CLKMGR_PERPLL_GPIODIV 0x1c 56 #define CLKMGR_PERPLL_PLLGLOB 0x20 57 #define CLKMGR_PERPLL_FDBCK 0x24 58 #define CLKMGR_PERPLL_MEM 0x28 59 #define CLKMGR_PERPLL_MEMSTAT 0x2c 60 #define CLKMGR_PERPLL_PLLC0 0x30 61 #define CLKMGR_PERPLL_PLLC1 0x34 62 #define CLKMGR_PERPLL_VCOCALIB 0x38 63 #define CLKMGR_PERPLL_PLLC2 0x3c 64 #define CLKMGR_PERPLL_PLLC3 0x40 65 #define CLKMGR_PERPLL_PLLM 0x44 66 #define CLKMGR_PERPLL_LOSTLOCK 0x50 67 68 /* Altera Group */ 69 #define CLKMGR_ALTERA 0x10d100d0 70 #define CLKMGR_ALTERA_JTAG 0x0 71 #define CLKMGR_ALTERA_EMACACTR 0x4 72 #define CLKMGR_ALTERA_EMACBCTR 0x8 73 #define CLKMGR_ALTERA_EMACPTPCTR 0xc 74 #define CLKMGR_ALTERA_GPIODBCTR 0x10 75 #define CLKMGR_ALTERA_S2FUSER0CTR 0x18 76 #define CLKMGR_ALTERA_S2FUSER1CTR 0x1c 77 #define CLKMGR_ALTERA_PSIREFCTR 0x20 78 #define CLKMGR_ALTERA_EXTCNTRST 0x24 79 #define CLKMGR_ALTERA_USB31CTR 0x28 80 #define CLKMGR_ALTERA_DSUCTR 0x2c 81 #define CLKMGR_ALTERA_CORE01CTR 0x30 82 #define CLKMGR_ALTERA_CORE23CTR 0x34 83 #define CLKMGR_ALTERA_CORE2CTR 0x38 84 #define CLKMGR_ALTERA_CORE3CTR 0x3c 85 86 /* Membus */ 87 #define CLKMGR_MEM_REQ BIT(24) 88 #define CLKMGR_MEM_WR BIT(25) 89 #define CLKMGR_MEM_ERR BIT(26) 90 #define CLKMGR_MEM_WDAT_OFFSET 16 91 #define CLKMGR_MEM_ADDR 0x4027 92 #define CLKMGR_MEM_WDAT 0x80 93 94 /* Clock Manager Macros */ 95 #define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 96 #define CLKMGR_STAT_BUSY_E_BUSY 0x1 97 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) 98 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) 99 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) 100 #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 101 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 102 #define CLKMGR_INTOSC_HZ 460000000 103 104 /* Main PLL Macros */ 105 #define CLKMGR_MAINPLL_EN_RESET 0x0000005e 106 #define CLKMGR_MAINPLL_ENS_RESET 0x0000005e 107 108 /* Peripheral PLL Macros */ 109 #define CLKMGR_PERPLL_EN_RESET 0x040007FF 110 #define CLKMGR_PERPLL_ENS_RESET 0x040007FF 111 112 #define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) 113 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) 114 115 /* Altera Macros */ 116 #define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff 117 118 /* Shared Macros */ 119 #define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) 120 #define CLKMGR_PSRC_MAIN 0 121 #define CLKMGR_PSRC_PER 1 122 123 #define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 124 #define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 125 #define CLKMGR_PLLGLOB_PSRC_F2S 0x2 126 127 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) 128 #define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 129 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 130 131 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) 132 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) 133 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) 134 135 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) 136 #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) 137 138 #define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 139 140 typedef struct { 141 uint32_t clk_freq_of_eosc1; 142 uint32_t clk_freq_of_f2h_free; 143 uint32_t clk_freq_of_cb_intosc_ls; 144 } CLOCK_SOURCE_CONFIG; 145 146 int config_clkmgr_handoff(handoff *hoff_ptr); 147 uint32_t get_wdt_clk(void); 148 uint32_t get_uart_clk(void); 149 uint32_t get_mmc_clk(void); 150 151 #endif 152