clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear

clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear the PWRC.PWKUPR.WEN bit. Not doing so causes problems if: a cpu
is suspended, woken from suspend, powered down through a cpu_off call
& receives a spurious interrupt. Since the WEN bit is not cleared
after the cpu woke up from suspend, the spurious wakeup will power the
cpu on. Since the cpu_off call clears the jump address in the mailbox
this spurious wakeup will cause the cpu to crash.

This patch fixes this issue by clearing the WEN bit whenever a cpu is
powered up.

Change-Id: Ic91f5dffe1ed01d76bc7fc807acf0ecd3e38ce5b

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rework general purpose registers save and restore

The runtime exception handling assembler code used magic numbers for
saving and restoring the general purpose register context on stack
memory. The

rework general purpose registers save and restore

The runtime exception handling assembler code used magic numbers for
saving and restoring the general purpose register context on stack
memory. The memory is interpreted as a 'gp_regs' structure and the
magic numbers are offsets to members of this structure. This patch
replaces the magic number offsets with constants. It also adds compile
time assertions to prevent an incorrect assembler view of this
structure.

Change-Id: Ibf125bfdd62ba3a33e58c5f1d71f8c229720781c

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Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c8

Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5

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Update user guide further to linker scripts changes

This patch updates the user guide section about the memory layout.
- Explain the verifications that the linker scripts does on the
global me

Update user guide further to linker scripts changes

This patch updates the user guide section about the memory layout.
- Explain the verifications that the linker scripts does on the
global memory layout.
- Refer to the new linker symbols.
- Describe the linker symbols exported to the trusted firmware code.

Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286

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Properly initialise the C runtime environment

This patch makes sure the C runtime environment is properly
initialised before executing any C code.

- Zero-initialise NOBITS sections (e.g. the bss

Properly initialise the C runtime environment

This patch makes sure the C runtime environment is properly
initialised before executing any C code.

- Zero-initialise NOBITS sections (e.g. the bss section).
- Relocate BL1 data from ROM to RAM.

Change-Id: I0da81b417b2f0d1f7ef667cc5131b1e47e22571f

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Various improvements/cleanups on the linker scripts

- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodat

Various improvements/cleanups on the linker scripts

- Check at link-time that bootloader images will fit in memory
at run time and that they won't overlap each other.
- Remove text and rodata orphan sections.
- Define new linker symbols to remove the need for platform setup
code to know the order of sections.
- Reduce the size of the raw binary images by cutting some sections
out of the disk image and allocating them at load time, whenever
possible.
- Rework alignment constraints on sections.
- Remove unused linker symbols.
- Homogenize linker symbols names across all BLs.
- Add some comments in the linker scripts.

Change-Id: I47a328af0ccc7c8ab47fcc0dc6e7dd26160610b9

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Treat compiler, assembler and linker warnings as errors

Change-Id: I56284ebf63bef99de1beb4fd86e2d8b6a7962ac0

Generate build products in sub-directories

A single binary can be compiled using a command such as:
make CROSS_COMPILE=aarch64-none-elf- bl1

Also make use of brackets consistent in the Makefile.

Generate build products in sub-directories

A single binary can be compiled using a command such as:
make CROSS_COMPILE=aarch64-none-elf- bl1

Also make use of brackets consistent in the Makefile.

Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e

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Increase default amount of RAM for Base FVPs in FDTs

- Large RAM-disks may have trouble starting with 2GB of memory.
- Increase from 2GB to 4GB in FDT.

Change-Id: I12c1b8e5db41114b88c69c48621cb2124

Increase default amount of RAM for Base FVPs in FDTs

- Large RAM-disks may have trouble starting with 2GB of memory.
- Increase from 2GB to 4GB in FDT.

Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7

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fvp: Remove call to bl2_get_ns_mem_layout() function

On FVP platforms, for now it is assumed that the normal-world
bootloader is already sitting in its final memory location.
Therefore, BL2 doesn't

fvp: Remove call to bl2_get_ns_mem_layout() function

On FVP platforms, for now it is assumed that the normal-world
bootloader is already sitting in its final memory location.
Therefore, BL2 doesn't need to load it and so it doesn't need
to know the extents of the non-trusted DRAM.

Change-Id: I33177ab43ca242edc8958f2fa8d994e7cf3e0843

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AArch64: Remove EL-agnostic TLB helper functions

Also, don't invalidate the TLBs in disable_mmu() function, it's better
to do it in enable_mmu() function just before actually enabling the
MMU.

Chan

AArch64: Remove EL-agnostic TLB helper functions

Also, don't invalidate the TLBs in disable_mmu() function, it's better
to do it in enable_mmu() function just before actually enabling the
MMU.

Change-Id: Ib32d6660019b0b2c17254156aad4be67ab4970e1

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Unmask SError and Debug exceptions.

Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on

Unmask SError and Debug exceptions.

Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on all boot paths. Also route external
abort and SError interrupts to EL3, otherwise they will target EL1.

Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092

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fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initia

fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initialisations of such variables.

It fixes a compilation warning at the same time:
plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around
initializer [-Wmissing-braces]
section("tzfw_coherent_mem"))) = {0};
^
plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for
‘ns_entry_info[0]’) [-Wmissing-braces]

Note that GCC should not have emitted this warning message in the
first place. The C Standard permits braces to be elided around
subaggregate initializers. See this GCC bug report:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119

Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35

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Fix inlining of GIC helper functions

Change-Id: I27aad560a5da21c0439f3ccc9dc07b026e7c6022

Move generic architectural setup out of blx_plat_arch_setup().

blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU. This patch moves
generic archi

Move generic architectural setup out of blx_plat_arch_setup().

blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU. This patch moves
generic architectural setup code out of blx_plat_arch_setup().

Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6

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Fix documentation issues in v0.2 release

Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16

Add Foundation FVP documentation

Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66

Add GICv3 ITS to FDTs

- The interrupt addresses need to be updated to work.

Change-Id: Icdd00177095ae9e4eb7b13718762f92e29b1465c

Do not enable CCI on Foundation FVP

- The Foundation FVP only has one cluster and does not have
CCI.

Change-Id: If91e81ff72c52e448150089c4cfea3e4d6ae1232

FDTs for v5.2 Foundation model

- The Foundation FVP is a cut down version of the Base FVP and as
such lacks some components.
- Three FDTs are provided.
fvp-foundation-gicv2legacy-psci:
Use t

FDTs for v5.2 Foundation model

- The Foundation FVP is a cut down version of the Base FVP and as
such lacks some components.
- Three FDTs are provided.
fvp-foundation-gicv2legacy-psci:
Use this when setting the Foundation FVP to use GICv2. In this
mode the GIC is located at the VE location, as described in the
VE platform memory map.
fvp-foundation-gicv3-psci :
Use this when setting the Foundation FVP to use GICv3. In this
mode the GIC is located at the Base location, as described in the
Base platform memory map.
fvp-foundation-gicv2-psci :
Use this when setting the Foundation FVP to use GICv3, but Linux
is expected to use GICv2 emulation mode. In this mode the GIC is
located at the Base location, but the GICv3 is used in GICv2
emulation mode.

Change-Id: I9d69bcef35c64cc8f16550efe077f578e55aaae5

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Writing to the FVP LED register should be a 32bit access.

- Writing to this register with a 64bit access can cause a
Systen Error Exception on some models.

Change-Id: Ibcf5bdf7ab55707db61c16298f2

Writing to the FVP LED register should be a 32bit access.

- Writing to this register with a 64bit access can cause a
Systen Error Exception on some models.

Change-Id: Ibcf5bdf7ab55707db61c16298f25caff50e1ff7e

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ARMv8 Trusted Firmware release v0.2