1 /* 2 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <platform.h> 33 #include <assert.h> 34 35 /******************************************************************************* 36 * Function that does the first bit of architectural setup that affects 37 * execution in the non-secure address space. 38 ******************************************************************************/ 39 void bl1_arch_setup(void) 40 { 41 unsigned long tmp_reg = 0; 42 unsigned int counter_base_frequency; 43 44 /* Enable alignment checks and set the exception endianess to LE */ 45 tmp_reg = read_sctlr(); 46 tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); 47 tmp_reg &= ~SCTLR_EE_BIT; 48 write_sctlr(tmp_reg); 49 50 /* 51 * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route 52 * external abort and SError interrupts to EL3 53 */ 54 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT | 55 SCR_FIQ_BIT; 56 write_scr(tmp_reg); 57 58 /* 59 * Enable SError and Debug exceptions 60 */ 61 enable_serror(); 62 enable_debug_exceptions(); 63 64 /* Do not trap coprocessor accesses from lower ELs to EL3 */ 65 write_cptr_el3(0); 66 67 /* Read the frequency from Frequency modes table */ 68 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); 69 /* The first entry of the frequency modes table must not be 0 */ 70 assert(counter_base_frequency != 0); 71 72 /* Program the counter frequency */ 73 write_cntfrq_el0(counter_base_frequency); 74 return; 75 } 76 77 /******************************************************************************* 78 * Set the Secure EL1 required architectural state 79 ******************************************************************************/ 80 void bl1_arch_next_el_setup(void) { 81 unsigned long current_sctlr, next_sctlr; 82 83 /* Use the same endianness than the current BL */ 84 current_sctlr = read_sctlr(); 85 next_sctlr = (current_sctlr & SCTLR_EE_BIT); 86 87 /* Set SCTLR Secure EL1 */ 88 next_sctlr |= SCTLR_EL1_RES1; 89 90 write_sctlr_el1(next_sctlr); 91 } 92