1/* 2 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32 33 .globl reset_handler 34 35 36 .section .text, "ax"; .align 3 37 38 /* ----------------------------------------------------- 39 * reset_handler() is the entry point into the trusted 40 * firmware code when a cpu is released from warm or 41 * cold reset. 42 * ----------------------------------------------------- 43 */ 44 45reset_handler:; .type reset_handler, %function 46 /* --------------------------------------------- 47 * Perform any processor specific actions upon 48 * reset e.g. cache, tlb invalidations etc. 49 * --------------------------------------------- 50 */ 51 bl cpu_reset_handler 52 53 /* --------------------------------------------- 54 * Set the exception vector to something sane. 55 * --------------------------------------------- 56 */ 57 adr x0, early_exceptions 58 msr vbar_el3, x0 59 60 /* --------------------------------------------- 61 * Enable the instruction cache. 62 * --------------------------------------------- 63 */ 64 mrs x0, sctlr_el3 65 orr x0, x0, #SCTLR_I_BIT 66 msr sctlr_el3, x0 67 68 isb 69 70_wait_for_entrypoint: 71 /* --------------------------------------------- 72 * Find the type of reset and jump to handler 73 * if present. If the handler is null then it is 74 * a cold boot. The primary cpu will set up the 75 * platform while the secondaries wait for 76 * their turn to be woken up 77 * --------------------------------------------- 78 */ 79 bl read_mpidr 80 bl platform_get_entrypoint 81 cbnz x0, _do_warm_boot 82 bl read_mpidr 83 bl platform_is_primary_cpu 84 cbnz x0, _do_cold_boot 85 86 /* --------------------------------------------- 87 * Perform any platform specific secondary cpu 88 * actions 89 * --------------------------------------------- 90 */ 91 bl plat_secondary_cold_boot_setup 92 b _wait_for_entrypoint 93 94_do_cold_boot: 95 /* --------------------------------------------- 96 * Init C runtime environment. 97 * - Zero-initialise the NOBITS sections. 98 * There are 2 of them: 99 * - the .bss section; 100 * - the coherent memory section. 101 * - Copy the data section from BL1 image 102 * (stored in ROM) to the correct location 103 * in RAM. 104 * --------------------------------------------- 105 */ 106 ldr x0, =__BSS_START__ 107 ldr x1, =__BSS_SIZE__ 108 bl zeromem16 109 110 ldr x0, =__COHERENT_RAM_START__ 111 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 112 bl zeromem16 113 114 ldr x0, =__DATA_RAM_START__ 115 ldr x1, =__DATA_ROM_START__ 116 ldr x2, =__DATA_SIZE__ 117 bl memcpy16 118 119 /* --------------------------------------------- 120 * Initialize platform and jump to our c-entry 121 * point for this type of reset 122 * --------------------------------------------- 123 */ 124 adr x0, bl1_main 125 bl platform_cold_boot_init 126 b _panic 127 128_do_warm_boot: 129 /* --------------------------------------------- 130 * Jump to BL31 for all warm boot init. 131 * --------------------------------------------- 132 */ 133 blr x0 134_panic: 135 b _panic 136