xref: /rk3399_ARM-atf/bl1/bl1.ld.S (revision ab2d31edbd9dea69bd1ca495e3fce0511c9d42ff) 
1/*
2 * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36MEMORY {
37    ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
38    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
39}
40
41SECTIONS
42{
43    ro : {
44        __RO_START__ = .;
45        *bl1_entrypoint.o(.text)
46        *(.text)
47        *(.rodata*)
48        __RO_END__ = .;
49    } >ROM
50
51    /*
52     * The .data section gets copied from ROM to RAM at runtime.
53     * Its LMA and VMA must be 16-byte aligned.
54     */
55    . = NEXT(16);        /* Align LMA */
56    .data : ALIGN(16) {  /* Align VMA */
57        __DATA_RAM_START__ = .;
58        *(.data)
59        __DATA_RAM_END__ = .;
60    } >RAM AT>ROM
61
62    stacks (NOLOAD) : {
63        __STACKS_START__ = .;
64        *(tzfw_normal_stacks)
65        __STACKS_END__ = .;
66    } >RAM
67
68    /*
69     * The .bss section gets initialised to 0 at runtime.
70     * Its base address must be 16-byte aligned.
71     */
72    .bss : ALIGN(16) {
73        __BSS_START__ = .;
74        *(.bss)
75        *(COMMON)
76        __BSS_END__ = .;
77    } >RAM
78
79    /*
80     * The base address of the coherent memory section must be page-aligned (4K)
81     * to guarantee that the coherent data are stored on their own pages and
82     * are not mixed with normal data.  This is required to set up the correct
83     * memory attributes for the coherent data page tables.
84     */
85    coherent_ram (NOLOAD) : ALIGN(4096) {
86        __COHERENT_RAM_START__ = .;
87        *(tzfw_coherent_mem)
88        __COHERENT_RAM_END_UNALIGNED__ = .;
89        /*
90         * Memory page(s) mapped to this section will be marked
91         * as device memory.  No other unexpected data must creep in.
92         * Ensure the rest of the current memory page is unused.
93         */
94        . = NEXT(4096);
95        __COHERENT_RAM_END__ = .;
96    } >RAM
97
98    __BL1_RAM_START__ = ADDR(.data);
99    __BL1_RAM_END__ = .;
100
101    __DATA_ROM_START__ = LOADADDR(.data);
102    __DATA_SIZE__ = SIZEOF(.data);
103
104    __BSS_SIZE__ = SIZEOF(.bss);
105
106    __COHERENT_RAM_UNALIGNED_SIZE__ =
107        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
108
109    ASSERT(. <= BL31_BASE, "BL31 image overlaps BL1 image.")
110}
111