xref: /rk3399_ARM-atf/bl2/bl2.ld.S (revision 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56) 
1/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36MEMORY {
37    /* RAM is read/write and Initialised */
38    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
39}
40
41
42SECTIONS
43{
44    . = BL2_BASE;
45
46    BL2_RO NEXT (4096): {
47        *(entry_code)
48        *(.text .rodata)
49    } >RAM
50
51    BL2_STACKS NEXT (4096): {
52        *(tzfw_normal_stacks)
53    } >RAM
54
55    BL2_COHERENT_RAM NEXT (4096): {
56        *(tzfw_coherent_mem)
57        /*       . += 0x1000;*/
58        /* Do we need to ensure at least 4k here? */
59         . = NEXT(4096);
60    } >RAM
61
62    __BL2_DATA_START__ = .;
63    .bss NEXT (4096): {
64        *(SORT_BY_ALIGNMENT(.bss))
65        *(COMMON)
66    } >RAM
67
68    .data : {
69        *(.data)
70    } >RAM
71    __BL2_DATA_STOP__ = .;
72
73
74    __BL2_RO_BASE__ = LOADADDR(BL2_RO);
75    __BL2_RO_SIZE__ = SIZEOF(BL2_RO);
76
77    __BL2_STACKS_BASE__ = LOADADDR(BL2_STACKS);
78    __BL2_STACKS_SIZE__ = SIZEOF(BL2_STACKS);
79
80    __BL2_COHERENT_RAM_BASE__ = LOADADDR(BL2_COHERENT_RAM);
81    __BL2_COHERENT_RAM_SIZE__ = SIZEOF(BL2_COHERENT_RAM);
82
83    __BL2_RW_BASE__ = __BL2_DATA_START__;
84    __BL2_RW_SIZE__ = __BL2_DATA_STOP__ - __BL2_DATA_START__;
85}
86