xref: /rk3399_ARM-atf/bl31/bl31.ld.S (revision 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56) 
1/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36
37MEMORY {
38    /* RAM is read/write and Initialised */
39    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
40}
41
42
43SECTIONS
44{
45   . = BL31_BASE;
46
47    BL31_RO ALIGN (4096): {
48        *(entry_code)
49        *(.text)
50        *(.rodata)
51    } >RAM
52
53    BL31_STACKS ALIGN (4096): {
54        . += 0x1000;
55        *(tzfw_normal_stacks)
56    } >RAM
57
58    BL31_COHERENT_RAM ALIGN (4096): {
59        *(tzfw_coherent_mem)
60        /*       . += 0x1000;*/
61        /* Do we need to ensure at least 4k here? */
62         . = ALIGN(4096);
63    } >RAM
64
65    __BL31_DATA_START__ = .;
66    .bss  ALIGN (4096): {
67        *(.bss)
68        *(COMMON)
69    } >RAM
70
71    .data : {
72        *(.data)
73    } >RAM
74    __BL31_DATA_STOP__ = .;
75
76
77    __BL31_RO_BASE__ = LOADADDR(BL31_RO);
78    __BL31_RO_SIZE__ = SIZEOF(BL31_RO);
79
80    __BL31_STACKS_BASE__ = LOADADDR(BL31_STACKS);
81    __BL31_STACKS_SIZE__ = SIZEOF(BL31_STACKS);
82
83    __BL31_COHERENT_RAM_BASE__ = LOADADDR(BL31_COHERENT_RAM);
84    __BL31_COHERENT_RAM_SIZE__ = SIZEOF(BL31_COHERENT_RAM);
85
86    __BL31_RW_BASE__ = __BL31_DATA_START__;
87    __BL31_RW_SIZE__ = __BL31_DATA_STOP__ - __BL31_DATA_START__;
88}
89