xref: /rk3399_ARM-atf/bl31/aarch64/bl31_entrypoint.S (revision 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56)
1/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl1.h>
32#include <bl_common.h>
33#include <platform.h>
34
35
36	.globl	bl31_entrypoint
37
38
39	.section	entry_code, "ax"; .align 3
40
41	/* -----------------------------------------------------
42	 * bl31_entrypoint() is the cold boot entrypoint,
43	 * executed only by the primary cpu.
44	 * -----------------------------------------------------
45	 */
46
47bl31_entrypoint:; .type bl31_entrypoint, %function
48	/* ---------------------------------------------
49	 * BL2 has populated x0,x3,x4 with the opcode
50	 * indicating BL31 should be run, memory layout
51	 * of the trusted SRAM available to BL31 and
52	 * information about running the non-trusted
53	 * software already loaded by BL2. Check the
54	 * opcode out of paranoia.
55	 * ---------------------------------------------
56	 */
57	mov	x19, #RUN_IMAGE
58	cmp	x0, x19
59	b.ne	_panic
60	mov	x20, x3
61	mov	x21, x4
62
63	/* ---------------------------------------------
64	 * This is BL31 which is expected to be executed
65	 * only by the primary cpu (at least for now).
66	 * So, make sure no secondary has lost its way.
67	 * ---------------------------------------------
68	 */
69	bl	read_mpidr
70	mov	x19, x0
71	bl	platform_is_primary_cpu
72	cbz	x0, _panic
73
74	/* --------------------------------------------
75	 * Give ourselves a small coherent stack to
76	 * ease the pain of initializing the MMU
77	 * --------------------------------------------
78	 */
79	mov	x0, x19
80	bl	platform_set_coherent_stack
81
82	/* ---------------------------------------------
83	 * Perform platform specific early arch. setup
84	 * ---------------------------------------------
85	 */
86	mov	x0, x20
87	mov	x1, x21
88	mov	x2, x19
89	bl	bl31_early_platform_setup
90	bl	bl31_plat_arch_setup
91
92	/* ---------------------------------------------
93	 * Give ourselves a stack allocated in Normal
94	 * -IS-WBWA memory
95	 * ---------------------------------------------
96	 */
97	mov	x0, x19
98	bl	platform_set_stack
99
100	/* ---------------------------------------------
101	 * Use SP_EL0 to initialize BL31. It allows us
102	 * to jump to the next image without having to
103	 * come back here to ensure all of the stack's
104	 * been popped out. run_image() is not nice
105	 * enough to reset the stack pointer before
106	 * handing control to the next stage.
107	 * ---------------------------------------------
108	 */
109	mov	x0, sp
110	msr	sp_el0, x0
111	msr	spsel, #0
112	isb
113
114	/* ---------------------------------------------
115	 * Jump to main function.
116	 * ---------------------------------------------
117	 */
118	bl	bl31_main
119
120_panic:
121	b	_panic
122