1/* 2 * Copyright (c) 2013, ARM Limited. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 32 .globl reset_handler 33 34 35 .section reset_code, "ax"; .align 3 36 37 /* ----------------------------------------------------- 38 * reset_handler() is the entry point into the trusted 39 * firmware code when a cpu is released from warm or 40 * cold reset. 41 * ----------------------------------------------------- 42 */ 43 44reset_handler:; .type reset_handler, %function 45 /* --------------------------------------------- 46 * Perform any processor specific actions upon 47 * reset e.g. cache, tlb invalidations etc. 48 * --------------------------------------------- 49 */ 50 bl cpu_reset_handler 51 52_wait_for_entrypoint: 53 /* --------------------------------------------- 54 * Find the type of reset and jump to handler 55 * if present. If the handler is null then it is 56 * a cold boot. The primary cpu will set up the 57 * platform while the secondaries wait for 58 * their turn to be woken up 59 * --------------------------------------------- 60 */ 61 bl read_mpidr 62 bl platform_get_entrypoint 63 cbnz x0, _do_warm_boot 64 bl read_mpidr 65 bl platform_is_primary_cpu 66 cbnz x0, _do_cold_boot 67 68 /* --------------------------------------------- 69 * Perform any platform specific secondary cpu 70 * actions 71 * --------------------------------------------- 72 */ 73 bl plat_secondary_cold_boot_setup 74 b _wait_for_entrypoint 75 76_do_cold_boot: 77 /* --------------------------------------------- 78 * Initialize platform and jump to our c-entry 79 * point for this type of reset 80 * --------------------------------------------- 81 */ 82 adr x0, bl1_main 83 bl platform_cold_boot_init 84 b _panic 85 86_do_warm_boot: 87 /* --------------------------------------------- 88 * Jump to BL31 for all warm boot init. 89 * --------------------------------------------- 90 */ 91 blr x0 92_panic: 93 b _panic 94