Merge changes from topic "gr/cpu_lib" into integration

* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
fe

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
feat(build): allow full LTO builds with clang
refactor(build): make sorting of sections generic
feat(build): use clang as a linker
fix(build): correctly detect that an option is missing with ld_option
feat(build): pass cflags to the linker when LTO is enabled

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Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Corte

Merge changes from topic "gr/spectre_bhb_updates" into integration

* changes:
fix(security): fix Neoverse V2 CVE-2022-23960
fix(security): fix Cortex-X3 CVE-2022-23960
fix(security): fix Cortex-A715 CVE-2022-23960
fix(security): fix spectre bhb loop count for Cortex-A720

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fix(cm): correctly restore BL2's context

We have a single context management library but two BLs that use it very
differently - BL1 and BL31. Configuring it correctly is quite tricky as
in the BL1 +

fix(cm): correctly restore BL2's context

We have a single context management library but two BLs that use it very
differently - BL1 and BL31. Configuring it correctly is quite tricky as
in the BL1 + BL2 + BL31 + spmd case we have it operate on both EL1 and
EL2 context (for BL1 and BL31 respectively).

Welp, we've got that wrong - BL1 will skip EL1's register initialisation
leaving it at the mercy of UNKNOWN registers' values. If they aren't as
we expect, things don't go well.

This is not the end of the world as BL1 is expected to be the first
thing to run and UNKNOWN values generally reset to things we find
acceptable. But add the correct BL1 carveouts so they are set up
correctly.

Change-Id: Ia0d5522ac0c9f4616dd124b10f0c2fdc823a0d87
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cm): deprecate use of NS_TIMER_SWITCH" into integration

feat(cpus): add support for caddo cpu

Add basic CPU library code to support Caddo CPU

Change-Id: I4b431771ebe6f23eb02f3301ff656cfcd4956f81
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(cpus): add support for veymont cpu

Add basic CPU library code to support Veymont CPU

Change-Id: I44db5650e7c9cf8fcc368c935574f4702c373dae
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "refactor(build): avoid implicit pattern rules" into integration

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies code quite a bit as the gcc/clang different is much
smaller. Support for ld/lld (if overriden with LD) is maintained.

This is a good time to convert tabs to spaces to conform to make's
expectations on syntax.

Change-Id: I6c529c1393f7e9e8046ed537f871fc3ad91d599a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pa

feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pass the same flags to the compilation and linking stages when we enable
LTO. This is crucial for things like the undefined behaviour sanitiser.
Anecdotally, in working on this, there have been a fair few errors that
the compiler has only been able to catch due to warning flags being
passed to the linker and building with LTO.

This patch puts the contents of TF_CFLAGS into TF_LDFLAGS when LTO is
enabled. This is easier said than done, however, as we support building
with clang and linking with gcc (or vice versa), so CFLAGS that are
discovered for one will not work for the other. This patch works around
this by splitting all flags into a per-compiler variable. Then CFLAGS
and LDFLAGS get the contents of the correct one.

Some notable side effects: CPPFLAGS and TF_CFLAGS_$(ARCH) become empty
and are removed, although expanding them is kept as platforms set them.
Some flags become duplicate and are removed form TF_LDFLAGS (eg -O1).

The errata (--fix) flags are kept as-is but moved to cpu-ops.mk for
consistency. This is because they currently don't work with LTO and will
be addressed in a later patch.

Finally, ERROR_DEPRECATED's flags are also identical on all compilers so
don't maintain a difference.

Change-Id: I3630729ee5f474c09d4722cd0ede6845e1725d95
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those system registers are trapped by the SCR_EL3.AIEn bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_AIE build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: Iba2011719013a89f9cb3a4317bde18254f45cd25
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

$(OBJS): %.o: %.s
...

These behave similarly, but have some subtle differences. The former
defines a rule "for any target matching %.o where there is not a more
specific rule", whereas the latter defines a rule "for these targets,
which match %.o".

Where possible it is better to use a static pattern rule as it reduces
the rule space that Make needs to search.

Change-Id: Ifba4f44bcecf4e74980c31347e192cdf1e42003e
Signed-off-by: Chris Kay <chris.kay@arm.com>

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refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e83

refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e839
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2729604

Cortex-A720 erratum 2729604 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This workaround might impact perf

fix(cpus): workaround for Cortex-A720 erratum 2729604

Cortex-A720 erratum 2729604 is a Cat B erratum that applies to
revisions r0p0 and r0p1, and is fixed in r0p2.

This workaround might impact performance of workloads heavily
relying on floating point division or square root operations.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: I4567d75ba9f17146d0d7bc5cdb622bb63efadc3c
Signed-off-by: John Powell <john.powell@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(cm): remove unused macro" into integration

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

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fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281f

fix(security): fix Neoverse V2 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Neoverse V2, revision r0p0 only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I859012281fc67243f050d27e364f27434389c0cf
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d

fix(security): fix Cortex-X3 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-X3, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: I3d46fa70c80129ca0085d8245ee013f11a8842e3
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id:

fix(security): fix Cortex-A715 CVE-2022-23960

Apply CVE-2022-23960 mitigation to Cortex-A715, revision r1p0 and earlier only.
Ref - https://developer.arm.com/documentation/110280/latest/

Change-Id: Ib6b704733e474824772cb27bd048b1e179d90da9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

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Merge "fix(gpt): fix fill_l1_cont_desc() function" into integration

Merge "refactor(el3-runtime): move context security states to context.h" into integration

fix(cm): remove unused macro

It is never referenced.

Change-Id: I538b1f3d8660426faf5bafa68ecda2d637b0bc50
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

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