feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- P

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- Platform definitions and memory map for R-Car X5H
(Cortex-A720AE, 8 clusters x 4 cores)
- Platform-specific PSCI power management and topology
- SCMI-based power domain and system power management
- GICv4/Fainlight-AE interrupt controller initialization and support
- Trusted SRAM, shared memory, and crash log region setup
- SCIF console support
- Stack protector implementation for enhanced security
- Platform-specific linker script and build integration
- Various helper and initialization routines for MMU, GIC, and SCMI
- Platform-specific mailbox and boot flow handling
- Basic suspend implementation via SCP-FW
- AMU counters, SVE, PAUTH accessible to EL1

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04be48a55a618fe952b28283d2f85f48f7761c9a

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fix(rcar4): assure SCIF and HSCIF clock are always enabled

Prior stages before TFA BL31 may shut down the SCIF or HSCIF clock.
Enable the SCIF or HSCIF clock again during console initialization,
to

fix(rcar4): assure SCIF and HSCIF clock are always enabled

Prior stages before TFA BL31 may shut down the SCIF or HSCIF clock.
Enable the SCIF or HSCIF clock again during console initialization,
to make sure those clock are running and prints can be produced on
serial console if necessary.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I9461e72888a939c0bbe5795087a76f1a71c7151d

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feat(rcar): split common SCIF code

Move common SCIF code into drivers/renesas/common/scif/scif-common.c
and retain only SoC-specific console_rcar_init() in
drivers/renesas/rcar_gen4/scif/scif.c. Thi

feat(rcar): split common SCIF code

Move common SCIF code into drivers/renesas/common/scif/scif-common.c
and retain only SoC-specific console_rcar_init() in
drivers/renesas/rcar_gen4/scif/scif.c. This allows other SoCs to
reuse the common code and add only SoC specific glue code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ie970984ea551e482479af91524974b281923f813

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feat(rcar): replace static rcar_putc pointer with static register offsets

Replace static rcar_putc pointer with static register offsets to make
the driver more generic for future Renesas R-Car SoCs.

feat(rcar): replace static rcar_putc pointer with static register offsets

Replace static rcar_putc pointer with static register offsets to make
the driver more generic for future Renesas R-Car SoCs. Introduce new
function scif_console_set_regs() to assign SCIF registers into static
variables, and call scif_console_set_regs() based on MODEMR register
settings. Other SoCs might simply call scif_console_set_regs() with
fixed register offsets.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ia13f8e098b2776b520d24daf7acb7538b1ef3feb

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feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by

feat(rcar): deduplicate SCIF console_rcar_register

The console_rcar_register assembler macro is functionally identical
between Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Ib498832dbed9063efdb9979e89e53d119303d9df

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feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mai

feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Id50a730ea58faedaa24380fd3171be171ecd7269

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feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <mar

feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I24209ac0277fa12898bbeea69d93a8f057e76ed4

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fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+re

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Icdb5188cba97be5dfccb240f773288a54662e977

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feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU p

feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU power driver, Gen4 (H)SCIF driver, and function to get canary for
stack protector. Unlike Gen3, the Gen4 uses only TFA BL31 during boot.

Change-Id: Ic0eb8638a85757f997f29fc524c118c3e5d5135a
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Jing Dan <jing.dan.nx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Masashi Ozaki <masashi.ozaki.te@renesas.com>
Signed-off-by: Taichiro Yokoyama <taichiro.yokoyama.ns@hitachi.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Tsukasa Kawaguchi <tsukasa.kawaguchi.aw@hitachi.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
---
NOTE: This patch is squashed and cleaned up from large stack of patches
from multiple authors. SoB line from each author is included here,
the author of this commit is set to myself although that is most
certainly not accurate.

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fix(rcar): use platform_def

The definitions are duplicate and cause compilation errors when includes
change.

Change-Id: Iadc45e053918b5e13fa12f0b371e5e77b56aef22
Signed-off-by: Boyan Karatotev <boy

fix(rcar): use platform_def

The definitions are duplicate and cause compilation errors when includes
change.

Change-Id: Iadc45e053918b5e13fa12f0b371e5e77b56aef22
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fi

fix(rcar3-drivers): disable A/B loader support by default

The A/B loader [1] meant to be used for convenient CI testing.
The tool is installed into the same location as SA0, where it
conveniently fits due to its size, and where it makes use of
non-volatile PMIC registers to alternate between loading and
starting A or B copy of the BL2. The PMIC registers are used
because CPU registers are lost across reset.

In case the B copy is loaded, it is loaded from 8 MiB offset
from start of HF. In case the B copy fails to boot, a simple
reset of the system will switch back to booting previously
known working A copy and allow recovery.

The A/B loader sets MFIS bit MFISBTSTSR_BOOT_PARTITION to
pass the information which A/B copy is currently booting on
to TFA, which then loads the follow up components from 0 MiB
or 8 MiB offset, depending on whether the A or B copy is being
booted.

The MFISBTSTSR_BOOT_PARTITION interferes with regular A/B
switching during boot from eMMC as the boot media, where
the BootROM also sets MFISBTSTSR_BOOT_PARTITION bit in case
the system boots from SECOND eMMC HW BOOT partition.

Since the A/B loader is meant as a development and CI tool,
isolate the A/B loader use to RPC HF only and furthermore
isolate it behind new RCAR_RPC_HYPERFLASH_ABLOADER option
which is disabled by default.

[1] https://github.com/marex/abloader

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04ecd50fa1405b78e1ba3949d54029034d4f22d8

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feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3

In the high system load situation, bus latency increase was observed
and it made impact to other feature (e.g. audio dropouts). T

feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3

In the high system load situation, bus latency increase was observed
and it made impact to other feature (e.g. audio dropouts). This is
because some modules push as much as possible traffic into the DBSC4
CAM for execution, and make increasing bus latency. Re-defining swap
priorities reduce this situation. This advice has been confirmed by
hardware developer.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Change-Id: Ifebafa883d5a997de6894198327a6025b64e4ee5

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