| 50fba2db | 05-Jul-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
This patch documents the support for the newly introduced CTX_INCLUDE_SVE_REGS build flag. Since this build flag is influenced by other build fl
docs(simd): introduce CTX_INCLUDE_SVE_REGS build flag
This patch documents the support for the newly introduced CTX_INCLUDE_SVE_REGS build flag. Since this build flag is influenced by other build flags, the relevant sections have been updated with proper guidance.
This patch also documents the SEPARATE_SIMD_SECTION build flag.
Change-Id: I07852c4a65239c6a9c6de18a95c61aac429bec1c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 553b70c3 | 19-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ar/asymmetricSupport" into integration
* changes: feat(tc): enable trbe errata flags for Cortex-A520 and X4 feat(cm): asymmetric feature support for trbe refactor(err
Merge changes from topic "ar/asymmetricSupport" into integration
* changes: feat(tc): enable trbe errata flags for Cortex-A520 and X4 feat(cm): asymmetric feature support for trbe refactor(errata-abi): move EXTRACT_PARTNUM to arch.h feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228) feat(tc): make SPE feature asymmetric feat(cm): handle asymmetry for SPE feature feat(cm): support for asymmetric feature among cores feat(cpufeat): add new feature state for asymmetric features
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| 4a97ff51 | 05-Aug-2024 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them disable TRBE as a workaround. This patch doesn't have funct
feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228)
This patch implements errata functions for two errata, both of them disable TRBE as a workaround. This patch doesn't have functions that disable TRBE but only implemented helper functions that are used to detect cores affected by Errata 2938996(Cortex-A520) & 2726228(Cortex-X4)
Cortex-X4 SDEN documentation: https://developer.arm.com/documentation/SDEN2432808/latest
Cortex-A520 SDEN Documentation: https://developer.arm.com/documentation/SDEN-2444153/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I8f886a1c21698f546a0996c719cc27dc0a23633a
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| 43d1d951 | 18-Jul-2024 |
Manish Pandey <manish.pandey2@arm.com> |
feat(cpufeat): add new feature state for asymmetric features
Introduce a new feature state CHECK_ASYMMETRIC to cater for the features which are asymmetric across cores. This state is useful for plat
feat(cpufeat): add new feature state for asymmetric features
Introduce a new feature state CHECK_ASYMMETRIC to cater for the features which are asymmetric across cores. This state is useful for platforms which has architectural asymmetric cores (A feature is only present in one type of core e.g. big). This state is similar to FEAT_STATE_CHECK (dynamic detection) except that feature state is also checked on each core during warmboot path and override the context (just for asymmetric features) which was setup by core executing CPU_ON call.
Only Non-secure context will be re-checked as secure and realm context is created on same core.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ic78a0b6ca996e0d7881c43da1a6a0c422f528ef3
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| 2d4f264b | 17-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "romlib-fixes" into integration
* changes: fix(romlib): wrap indirectly included functions fix(arm): remove duplicate jumptable entry |
| abeb8ad6 | 16-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(cpus): workaround for Cortex-A720 erratum 2844092" into integration |
| 28e4ec1b | 16-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(cpus): workaround for Cortex-X4 erratum 2816013" into integration |
| a0c7bee6 | 16-Aug-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs(maintainers): update Corstone-1000 maintainers" into integration |
| 4c720e12 | 16-Aug-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(docs): add RMM option in build-options.rst" into integration |
| d95d56bd | 22-Jul-2024 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(romlib): wrap indirectly included functions
The problem that this resolves is a bit involved; the following must be met at the same time for some function <to_be_wrapped>:
* to_be_wrapped must
fix(romlib): wrap indirectly included functions
The problem that this resolves is a bit involved; the following must be met at the same time for some function <to_be_wrapped>:
* to_be_wrapped must be specified as part of the romlib * to_be_wrapped must _not_ be referenced by any translation unit in TF-A * to_be_wrapped must be referenced by a translation unit in a dependent library, mbedtls for example.
Under these circumstances, to_be_wrapped will not be wrapped, and will instead reference its original definition while simultaneously residing in romlib.
This is a side effect of two issues with romlib prior to this patch:
1 to_be_wrapped is expected to wrap by duplicating its definition. This causes any condition that links against both the base and wrapper functions to be a link error (duplicate symbol definition). 2 to_be_wrapped is in its own translation unit This causes the wrappers to be used by TF-A in an as needed.
The duplicate function definitions can be worked around using the linker's `--wrap` flag, which redirects all references to a symbol to resolve to `__wrap_<symbol>` and the original symbol to be available as `__real_<symbol>`. Most of the changes handle creating this arguments and passing them to the linker.
Further, once you use the linker's wrap, you will encounter another issue: if TF-A does not use a function, its wrapper is not present. This causes link issues when a library and not TF-A uses the wrapper. Note that this issue would have been resolved previously by ignoring the wrapper and using the base definition.
This further issue is worked around by concatenating the assembly for all of the wrappers into a single translation unit. It's possible to work around this issue in a few other ways, including reordering the libraries passed to the linker to place libwrapper.a last or grouping the libraries so that symbols from later libraries may be resolved with prior libraries.
I chose the translation unit concatenation approach as it revealed that a jumptable has duplicate symbols within it.
Change-Id: Ie57b5ae69bde2fc8705bdc7a93fae3ddb5341ed9 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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| deb7210d | 06-Aug-2024 |
Hugues Kamba-Mpiana <hugues.kambampiana@arm.com> |
docs(maintainers): update Corstone-1000 maintainers
* Add new maintainers: Hugues Kamba Mpiana * Remove maintainers: Xueliang Zhong * Update contact information for existing maintainers
Change-Id:
docs(maintainers): update Corstone-1000 maintainers
* Add new maintainers: Hugues Kamba Mpiana * Remove maintainers: Xueliang Zhong * Update contact information for existing maintainers
Change-Id: Ie4b7e7a1a179e3bf6f8d8e6c8e7ff0ad788e9f8f Signed-off-by: Hugues Kamba-Mpiana <hugues.kambampiana@arm.com>
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| 26f2f24c | 14-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "cot-dt2c" into integration
* changes: feat(arm): update documentation for cot-dt2c feat(arm): remove the bl2 static c file feat(arm): generate tbbr c file CoT dt2c
Merge changes from topic "cot-dt2c" into integration
* changes: feat(arm): update documentation for cot-dt2c feat(arm): remove the bl2 static c file feat(arm): generate tbbr c file CoT dt2c feat(arm): makefile invoke CoT dt2c feat(auth): standalone CoT dt2c tool refactor(auth): separate bl1 and bl2 CoT refactor(st): align the NV counter naming refactor(fvp): align the NV counter naming
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| 2c1a116f | 13-Aug-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "mp/ffa_bindings_update" into integration
* changes: docs: add binding for vm availability messages docs: fix discrepancies in value type of manifest fields docs: upda
Merge changes from topic "mp/ffa_bindings_update" into integration
* changes: docs: add binding for vm availability messages docs: fix discrepancies in value type of manifest fields docs: update ff-a manifest bindings chore(docs): remove hafnium specific documentation
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| e3ec6ff4 | 26-Jun-2023 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
feat(rk3588): support rk3588
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4
feat(rk3588): support rk3588
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
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| a22f84f0 | 10-Jul-2024 |
Balint Dobszay <balint.dobszay@arm.com> |
docs: add binding for vm availability messages
SPs can subscribe to get notified when a VM is created or destroyed. This patch adds a binding to the SP manifest to represent this.
Signed-off-by: Ba
docs: add binding for vm availability messages
SPs can subscribe to get notified when a VM is created or destroyed. This patch adds a binding to the SP manifest to represent this.
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Change-Id: Ib23655575f471a22bcf261f70f2c4124a3f292c3
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| 2e1db2b4 | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal): deprecate build time arg VERSAL_PLATFORM" into integration |
| 778e2452 | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes: docs(xilinx): update SMC documentation in TF-A feat(xilinx): add feature check function for TF-A specific
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes: docs(xilinx): update SMC documentation in TF-A feat(xilinx): add feature check function for TF-A specific APIs feat(xilinx): update SiP SVC version number feat(xilinx): update TF-A to passthrough all PLM commands fix(xilinx): fix logic to read ipi response
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| 9a01089d | 25-Jul-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs: fix discrepancies in value type of manifest fields
In order to avoid the complexity of supporting value types smaller than u32 and avoid discrepancies for the various manifest fields among dif
docs: fix discrepancies in value type of manifest fields
In order to avoid the complexity of supporting value types smaller than u32 and avoid discrepancies for the various manifest fields among different projects, the value type for relevant fields are upgraded to u32.
Change-Id: Ib033019b3b8c26bf4b8b50f89b7a6d1a772e5e51 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 3b63eef9 | 25-Jul-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
docs: update ff-a manifest bindings
Various SPMC projects within trustefirmware.org have decided to adhere to a common FF-A manifest binding document. The one hosted in the readthedocs portal of TF-
docs: update ff-a manifest bindings
Various SPMC projects within trustefirmware.org have decided to adhere to a common FF-A manifest binding document. The one hosted in the readthedocs portal of TF-A project will be considered as the reference.
Hence, this binding document is updated to reflect new additions made to binding document hosted in Hafnium project. Eventually, all other binding document are going to be removed.
Also, few fields were incorrectly identified as mandatory. Necessary corrections are made in this patch.
Change-Id: I2eadd77487c770e49605285bbd72027c5e72e385 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 65e573fc | 25-Jul-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
chore(docs): remove hafnium specific documentation
All the relevant documentation for Hafnium as the chosen Secure Partition Manager has been moved to hafnium project[1].
This patch removes the red
chore(docs): remove hafnium specific documentation
All the relevant documentation for Hafnium as the chosen Secure Partition Manager has been moved to hafnium project[1].
This patch removes the redundant sections without any loss of information.
This patch adds links to documentation of each of the SPM projects.
[1] https://hafnium.readthedocs.io/en/latest/secure-partition-manager/index.html
Change-Id: I52caf7dc50f4aa253c68309cac0915b7d368939d Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| b95f398e | 29-Jul-2024 |
Xialin Liu <Xialin.Liu@ARM.com> |
feat(arm): update documentation for cot-dt2c
Add documentation for the cot-dt2c feature
Change-Id: I27383882b639e39217d09ca76e316098cc4753d0 Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com> |
| 1b7f51ea | 02-Aug-2024 |
Jaylyn Ren <Jaylyn.Ren2@arm.com> |
feat(docs): add RMM option in build-options.rst
Add the RMM option description in the build-options document.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com> Change-Id: Idb884e2707a2bdc686f676d16f0
feat(docs): add RMM option in build-options.rst
Add the RMM option description in the build-options document.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com> Change-Id: Idb884e2707a2bdc686f676d16f0ff2f0e001a17d
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| 4dcbba98 | 20-Jun-2024 |
Charlie Bareham <charlie.bareham@arm.com> |
feat: add option to input attr as string of flag names
Change-Id: I56f0364ef43c9d415a335474e15b68e79db37f5d Signed-off-by: Charlie Bareham <charlie.bareham@arm.com> |
| 792e8e89 | 20-Jun-2024 |
Charlie Bareham <charlie.bareham@arm.com> |
feat: add option to input text instead of tag id number
Change-Id: I6d1b1a20d1cd5b073d7d614da102b9e6bd8ea522 Signed-off-by: Charlie Bareham <charlie.bareham@arm.com> |
| 31120993 | 17-Jun-2024 |
Charlie Bareham <charlie.bareham@arm.com> |
feat: add creating transfer lists from yaml files
This commit adds a command create-from-yaml to tlc, which creates a transfer list from a yaml file. It also changes the files structure of the fixtu
feat: add creating transfer lists from yaml files
This commit adds a command create-from-yaml to tlc, which creates a transfer list from a yaml file. It also changes the files structure of the fixtures in the unit tests so they are in a directory called trusted-firmware-a. This is necessary because blob file paths in the yaml file are relative to the root of TF-A.
The blob files are not verified by TLC, so it can be used to load arbitrary binary information into the transfer list. The authenticity of the transfer list must be ensured by the loader.
Change-Id: Idf704ce5d9b7e28b31f471ac337e4aef33d0ad8a Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
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