1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41- ``WORKAROUND_CVE_2024_7881``: Enables mitigation for `CVE-2024-7881`. 42 This build option should be set to 1 if the target platform contains at 43 least 1 CPU that requires this mitigation. Defaults to 1. 44 45.. _arm_cpu_macros_errata_workarounds: 46 47CPU Errata Workarounds 48---------------------- 49 50TF-A exports a series of build flags which control the errata workarounds that 51are applied to each CPU by the reset handler. The errata details can be found 52in the CPU specific errata documents published by Arm: 53 54- `Cortex-A53 MPCore Software Developers Errata Notice`_ 55- `Cortex-A57 MPCore Software Developers Errata Notice`_ 56- `Cortex-A72 MPCore Software Developers Errata Notice`_ 57 58The errata workarounds are implemented for a particular revision or a set of 59processor revisions. This is checked by the reset handler at runtime. Each 60errata workaround is identified by its ``ID`` as specified in the processor's 61errata notice document. The format of the define used to enable/disable the 62errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 63is for example ``A57`` for the ``Cortex_A57`` CPU. 64 65Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 66write errata workaround functions. 67 68All workarounds are disabled by default. The platform is responsible for 69enabling these workarounds according to its requirement by defining the 70errata workaround build flags in the platform specific makefile. In case 71these workarounds are enabled for the wrong CPU revision then the errata 72workaround is not applied. In the DEBUG build, this is indicated by 73printing a warning to the crash console. 74 75In the current implementation, a platform which has more than 1 variant 76with different revisions of a processor has no runtime mechanism available 77for it to specify which errata workarounds should be enabled or not. 78 79The value of the build flags is 0 by default, that is, disabled. A value of 1 80will enable it. 81 82For Cortex-A9, the following errata build flags are defined : 83 84- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 85 CPU. This needs to be enabled for all revisions of the CPU. 86 87For Cortex-A15, the following errata build flags are defined : 88 89- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 90 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 91 92- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 93 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 94 95For Cortex-A17, the following errata build flags are defined : 96 97- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 98 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 99 100- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 101 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 102 103For Cortex-A35, the following errata build flags are defined : 104 105- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 106 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 107 108For Cortex-A53, the following errata build flags are defined : 109 110- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 112 113- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 114 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 115 116- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 117 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 118 119- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 120 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 121 122- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 123 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 124 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 125 sections. 126 127- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 128 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 129 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 130 ``A53_DISABLE_NON_TEMPORAL_HINT``. 131 132- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 133 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 134 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 135 which are 4kB aligned. 136 137- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 138 CPUs. Though the erratum is present in every revision of the CPU, 139 this workaround is only applied to CPUs from r0p3 onwards, which feature 140 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 141 Earlier revisions of the CPU have other errata which require the same 142 workaround in software, so they should be covered anyway. 143 144- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 145 revisions of Cortex-A53 CPU. 146 147For Cortex-A55, the following errata build flags are defined : 148 149- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 150 CPU. This needs to be enabled only for revision r0p0 of the CPU. 151 152- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 153 CPU. This needs to be enabled only for revision r0p0 of the CPU. 154 155- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 156 CPU. This needs to be enabled only for revision r0p0 of the CPU. 157 158- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 159 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 160 161- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 162 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 163 164- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 165 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 166 167- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 168 revisions of Cortex-A55 CPU. 169 170For Cortex-A57, the following errata build flags are defined : 171 172- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 173 CPU. This needs to be enabled only for revision r0p0 of the CPU. 174 175- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 176 CPU. This needs to be enabled only for revision r0p0 of the CPU. 177 178- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 179 CPU. This needs to be enabled only for revision r0p0 of the CPU. 180 181- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 182 CPU. This needs to be enabled only for revision r0p0 of the CPU. 183 184- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 185 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 186 187- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 188 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 189 190- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 191 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 192 193- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 194 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 195 196- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 197 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 198 199- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 200 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 201 202- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 203 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 204 205- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 206 revisions of Cortex-A57 CPU. 207 208For Cortex-A72, the following errata build flags are defined : 209 210- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 211 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 212 213- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 214 revisions of Cortex-A72 CPU. 215 216For Cortex-A73, the following errata build flags are defined : 217 218- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 219 CPU. This needs to be enabled only for revision r0p0 of the CPU. 220 221- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 222 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 223 224For Cortex-A75, the following errata build flags are defined : 225 226- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 227 CPU. This needs to be enabled only for revision r0p0 of the CPU. 228 229- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 230 CPU. This needs to be enabled only for revision r0p0 of the CPU. 231 232For Cortex-A76, the following errata build flags are defined : 233 234- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 235 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 236 237- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 238 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 239 240- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 241 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 242 243- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 245 246- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 247 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 248 249- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 250 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 251 252- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 253 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 254 255- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 256 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 257 258- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 259 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 260 limitation of errata framework this errata is applied to all revisions 261 of Cortex-A76 CPU. 262 263- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 264 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 265 266- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 267 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 268 269- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 270 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 271 still open. 272 273For Cortex-A77, the following errata build flags are defined : 274 275- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 276 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 277 278- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 279 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 280 281- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 282 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 283 284- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 286 287- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 288 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 289 290 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 291 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 292 293 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 294 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 295 296For Cortex-A78, the following errata build flags are defined : 297 298- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 299 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 300 301- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 302 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 303 304- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 305 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 306 issue but there is no workaround for that revision. 307 308- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 309 CPU. This needs to be enabled for revisions r0p0 and r1p0. 310 311- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 312 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 313 314- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 315 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 316 is still open. 317 318- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 319 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 320 is present in r0p0 but there is no workaround. It is still open. 321 322- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 323 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 324 it is still open. 325 326- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 327 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 328 it is still open. 329 330- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 331 CPU, this erratum affects system configurations that do not use an ARM 332 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 333 and r1p2 and it is still open. 334 335- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 336 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 337 it is still open. 338 339- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 340 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 341 it is still open. 342 343- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 344 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 345 it is still open. 346 347For Cortex-A78AE, the following errata build flags are defined : 348 349- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 350 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 351 This erratum is still open. 352 353- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 354 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 355 erratum is still open. 356 357- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 358 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 359 This erratum is still open. 360 361- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 362 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 363 erratum is still open. 364 365- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 366 Cortex-A78AE CPU. This erratum affects system configurations that do not use 367 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 368 r0p2. This erratum is still open. 369 370For Cortex-A78C, the following errata build flags are defined : 371 372- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 373 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 374 fixed in r0p1. 375 376- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 377 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 378 fixed in r0p1. 379 380- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 381 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 382 it is still open. 383 384- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 385 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 386 it is still open. 387 388- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 389 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 390 erratum is still open. 391 392- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 393 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 394 erratum is still open. 395 396- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 397 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 398 erratum is still open. 399 400- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 401 Cortex-A78C CPU, this erratum affects system configurations that do not use 402 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 403 and is still open. 404 405- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 406 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 407 This erratum is still open. 408 409- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 410 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 411 This erratum is still open. 412 413- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 414 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 415 This erratum is still open. 416 417For Cortex-X1 CPU, the following errata build flags are defined: 418 419- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 420 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 421 422- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 423 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 424 425- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 426 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 427 428For Neoverse N1, the following errata build flags are defined : 429 430- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 431 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 432 433- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 434 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 435 436- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 437 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 438 439- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 440 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 441 442- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 443 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 444 445- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 446 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 447 448- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 449 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 450 451- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 452 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 453 454- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 455 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 456 457- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 458 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 459 460- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 461 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 462 463- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 464 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 465 466- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 467 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 468 revisions r0p0, r1p0, and r2p0 there is no workaround. 469 470- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 471 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 472 still open. 473 474For Neoverse V1, the following errata build flags are defined : 475 476- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 477 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 478 r1p0. 479 480- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 481 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 482 in r1p1. 483 484- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 485 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 486 in r1p1. 487 488- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 489 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 490 in r1p1. 491 492- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 493 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 494 495- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 496 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 497 CPU. 498 499- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 500 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 501 issue is present in r0p0 as well but there is no workaround for that 502 revision. It is still open. 503 504- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 505 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 506 CPU. It is still open. 507 508- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 509 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 510 It is still open. 511 512- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 513 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 514 issue is present in r0p0 as well but there is no workaround for that 515 revision. It is still open. 516 517- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 518 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 519 the CPU. 520 521- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 522 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 523 It has been fixed in r1p2. 524 525- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 526 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 527 It is still open. 528 529- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 530 CPU, this erratum affects system configurations that do not use an ARM 531 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 532 It has been fixed in r1p2. 533 534- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 535 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 536 CPU. It is still open. 537 538- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 539 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 540 CPU. It is still open. 541 542- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 543 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 544 CPU. It is still open. 545 546For Neoverse V2, the following errata build flags are defined : 547 548- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 549 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still 550 open. 551 552- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 553 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 554 r0p2. 555 556- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 557 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 558 r0p2. 559 560- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 561 CPU, this affects system configurations that do not use and ARM interconnect 562 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 563 in r0p2. 564 565- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 566 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 567 r0p2. 568 569- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 570 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 571 r0p2. 572 573- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 574 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 575 r0p2. 576 577- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 578 CPU, this affects all configurations. This needs to be enabled for revisions 579 r0p0 and r0p1. It has been fixed in r0p2. 580 581For Cortex-A710, the following errata build flags are defined : 582 583- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 584 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 585 r2p0 of the CPU. It is still open. 586 587- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 588 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 589 r2p0 of the CPU. It is still open. 590 591- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 592 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 593 and is still open. 594 595- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 596 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 597 of the CPU and is still open. 598 599- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 600 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 601 is still open. 602 603- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 604 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 605 and r2p1 of the CPU and is still open. 606 607- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 608 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 609 of the CPU and is fixed in r2p1. 610 611- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 612 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 613 of the CPU and is fixed in r2p1. 614 615- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 616 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 617 and is fixed in r2p1. 618 619- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 620 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 621 of the CPU and is fixed in r2p1. 622 623- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 624 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 625 r2p1 of the CPU and is still open. 626 627- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 628 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 629 of the CPU and is fixed in r2p1. 630 631- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 632 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 633 of the CPU and is fixed in r2p1. 634 635- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 636 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 637 of the CPU and is fixed in r2p1. 638 639- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 640 CPU, and applies to system configurations that do not use and ARM 641 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 642 is still open. 643 644- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 645 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 646 r2p1 of the CPU and is still open. 647 648- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 649 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 650 r2p1 of the CPU and is still open. 651 652- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 653 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 654 CPU and is still open. 655 656For Neoverse N2, the following errata build flags are defined : 657 658- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 659 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 660 661- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 662 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 663 664- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 665 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 666 667- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 668 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 669 670- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 671 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 672 673- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 674 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 675 676- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 677 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 678 679- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 680 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 681 682- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 683 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 684 685- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 686 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 687 688- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 689 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 690 691- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 692 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 693 r0p1. 694 695- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 696 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 697 r0p1. 698 699- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 700 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 701 it is fixed in r0p3. 702 703- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 704 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 705 706- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 707 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 708 r0p1. 709 710- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 711 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 712 in r0p3. 713 714- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 715 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 716 in r0p3. 717 718- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 719 CPU, this erratum affects system configurations that do not use and ARM 720 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 721 It is fixed in r0p3. 722 723- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 724 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 725 in r0p3. 726 727For Cortex-X2, the following errata build flags are defined : 728 729- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 730 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 731 it is still open. 732 733- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 734 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, 735 it is still open. 736 737- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 738 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 739 740- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 741 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 742 CPU, it is fixed in r2p1. 743 744- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 745 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 746 CPU, it is fixed in r2p1. 747 748- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 749 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 750 CPU, it is fixed in r2p1. 751 752- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 753 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 754 in r2p1. 755 756- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 757 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 758 CPU and is still open. 759 760- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 761 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 762 and is fixed in r2p1. 763 764- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 765 CPU and affects system configurations that do not use an ARM interconnect IP. 766 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 767 still open. 768 769- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 770 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 771 CPU and is still open. 772 773- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 774 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 775 CPU and is still open. 776 777- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 778 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 779 CPU and it is still open. 780 781For Cortex-X3, the following errata build flags are defined : 782 783- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 784 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of 785 the CPU and is still open. 786 787- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 788 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 789 is fixed in r1p1. 790 791- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 792 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 793 fixed in r1p2. 794 795- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 796 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 797 of the CPU, it is fixed in r1p1. 798 799- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 800 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 801 of the CPU, it is fixed in r1p1. 802 803- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 804 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 805 CPU, it is fixed in r1p2. 806 807- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 808 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 809 It is fixed in r1p1. 810 811- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 812 CPU and affects system configurations that do not use an ARM interconnect 813 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 814 in r1p2. 815 816- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 817 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 818 r1p1. It is fixed in r1p2. 819 820- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 821 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 822 fixed in r1p2. 823 824- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 825 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 826 CPU. It is fixed in r1p2. 827 828For Cortex-X4, the following errata build flags are defined : 829 830- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 831 CPU and affects system configurations that do not use an Arm interconnect IP. 832 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 833 The workaround for this erratum is not implemented in EL3, but the flag can 834 be enabled/disabled at the platform level. The flag is used when the errata ABI 835 feature is enabled and can assist the Kernel in the process of 836 mitigation of the erratum. 837 838- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 839 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 840 r0p2. 841 842- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 843 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 844 in r0p2. 845 846- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 847 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 848 849- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 850 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 851 852- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 853 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 854 855- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 856 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 857 858- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 859 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 860 861For Cortex-A510, the following errata build flags are defined : 862 863- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 864 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 865 fixed in r0p1. 866 867- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 868 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 869 r0p2, r0p3 and r1p0, it is fixed in r1p1. 870 871- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 872 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 873 r0p2, it is fixed in r0p3. 874 875- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 876 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 877 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 878 workaround for those revisions. 879 880- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 881 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 882 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 883 workaround for those revisions. 884 885- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 886 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 887 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 888 ENABLE_MPMM=1. 889 890- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 891 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 892 r0p3 and r1p0, it is fixed in r1p1. 893 894- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 895 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 896 r0p3 and r1p0, it is fixed in r1p1. 897 898- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 899 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 900 r0p3, r1p0 and r1p1. It is fixed in r1p2. 901 902- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 903 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 904 r0p3, r1p0, r1p1, and is fixed in r1p2. 905 906- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 907 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 908 r0p3, r1p0, r1p1. It is fixed in r1p2. 909 910- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 911 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 912 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 913 914For Cortex-A520, the following errata build flags are defined : 915 916- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 917 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 918 CPU and is still open. 919 920- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 921 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 922 It is still open. 923 924- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 925 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 926 It is fixed in r0p2. 927 928For Cortex-A715, the following errata build flags are defined : 929 930- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 931 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 932 It is fixed in r1p1. 933 934- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 935 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 936 fixed in r1p1. 937 938- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 939 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 940 when SPE(Statistical profiling extension)=True. The errata is fixed 941 in r1p1. 942 943- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 944 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 945 It is fixed in r1p1. 946 947- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 948 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 949 workaround for revision r0p0. It is fixed in r1p1. 950 951- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 952 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 953 It is fixed in r1p1. 954 955- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 956 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 957 and r1p1. It is fixed in r1p2. 958 959For Cortex-A720, the following errata build flags are defined : 960 961- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 962 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 963 It is fixed in r0p2. 964 965- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 966 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 967 It is fixed in r0p2. 968 969- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 970 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 971 It is fixed in r0p2. 972 973- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 974 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 975 It is fixed in r0p2. 976 977DSU Errata Workarounds 978---------------------- 979 980Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 981Shared Unit) errata. The DSU errata details can be found in the respective Arm 982documentation: 983 984- `Arm DSU Software Developers Errata Notice`_. 985 986Each erratum is identified by an ``ID``, as defined in the DSU errata notice 987document. Thus, the build flags which enable/disable the errata workarounds 988have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 989of DSU errata workarounds are similar to `CPU errata workarounds`_. 990 991For DSU errata, the following build flags are defined: 992 993- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 994 affected DSU configurations. This errata applies only for those DSUs that 995 revision is r0p0 (on r0p1 it is fixed). However, please note that this 996 workaround results in increased DSU power consumption on idle. 997 998- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 999 affected DSU configurations. This errata applies only for those DSUs that 1000 contain the ACP interface **and** the DSU revision is older than r2p0 (on 1001 r2p0 it is fixed). However, please note that this workaround results in 1002 increased DSU power consumption on idle. 1003 1004- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1005 affected DSU configurations. This errata applies for those DSUs with 1006 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1007 please note that this workaround results in increased DSU power consumption 1008 on idle. 1009 1010CPU Specific optimizations 1011-------------------------- 1012 1013This section describes some of the optimizations allowed by the CPU micro 1014architecture that can be enabled by the platform as desired. 1015 1016- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1017 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1018 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1019 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1020 is a known safe deviation from the Cortex-A57 TRM defined power down 1021 sequence. Each Cortex-A57 based platform must make its own decision on 1022 whether to use the optimization. 1023 1024- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1025 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1026 in a way most programmers expect, and will most probably result in a 1027 significant speed degradation to any code that employs them. The Armv8-A 1028 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1029 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1030 flag enforces this behaviour. This needs to be enabled only for revisions 1031 <= r0p3 of the CPU and is enabled by default. 1032 1033- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1034 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1035 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1036 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1037 `Cortex-A57 Software Optimization Guide`_. 1038 1039- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1040 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1041 this bit only if their memory system meets the requirement that cache 1042 line fill requests from the Cortex-A57 processor are atomic. Each 1043 Cortex-A57 based platform must make its own decision on whether to use 1044 the optimization. This flag is disabled by default. 1045 1046- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1047 level cache(LLC) is present in the system, and that the DataSource field 1048 on the master CHI interface indicates when data is returned from the LLC. 1049 This is used to control how the LL_CACHE* PMU events count. 1050 Default value is 0 (Disabled). 1051 1052GIC Errata Workarounds 1053---------------------- 1054- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1055 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1056 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1057 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1058 then this flag is enabled; otherwise, it is 0 (Disabled). 1059 1060-------------- 1061 1062*Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.* 1063 1064.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1065.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1066.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1067.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 1068.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 1069.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 1070.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 1071.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 1072