1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <cortex_a75.h> 12 #include <cortex_a520.h> 13 #include <cortex_a710.h> 14 #include <cortex_a715.h> 15 #include <cortex_a720.h> 16 #include <cortex_a720_ae.h> 17 #include <cortex_x4.h> 18 #include <lib/cpus/cpu_ops.h> 19 #include <lib/cpus/errata.h> 20 21 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 22 unsigned int check_if_affected_core(void) 23 { 24 uint32_t midr_val = read_midr(); 25 long rev_var = cpu_get_rev_var(); 26 27 if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) { 28 return check_erratum_cortex_a520_2938996(rev_var); 29 } else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) { 30 return check_erratum_cortex_x4_2726228(rev_var); 31 } 32 33 return ERRATA_NOT_APPLIES; 34 } 35 #endif 36 37 #if ERRATA_A75_764081 38 bool errata_a75_764081_applies(void) 39 { 40 long rev_var = cpu_get_rev_var(); 41 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 42 return true; 43 } 44 return false; 45 } 46 #endif /* ERRATA_A75_764081 */ 47 48 bool errata_ich_vmcr_el2_applies(void) 49 { 50 switch (EXTRACT_PARTNUM(read_midr())) { 51 #if ERRATA_A710_3701772 52 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 53 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 54 return true; 55 break; 56 #endif /* ERRATA_A710_3701772 */ 57 58 #if ERRATA_A715_3699560 59 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 60 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 61 return true; 62 break; 63 #endif /* ERRATA_A715_3699560 */ 64 65 #if ERRATA_A720_3699561 66 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 67 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 68 return true;; 69 break; 70 #endif /* ERRATA_A720_3699561 */ 71 72 #if ERRATA_A720_AE_3699562 73 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 74 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 75 return true; 76 break; 77 #endif /* ERRATA_A720_AE_3699562 */ 78 79 default: 80 break; 81 } 82 83 return false; 84 } 85