1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <cortex_a75.h> 12 #include <cortex_a520.h> 13 #include <cortex_a710.h> 14 #include <cortex_a715.h> 15 #include <cortex_a720.h> 16 #include <cortex_a720_ae.h> 17 #include <cortex_a725.h> 18 #include <cortex_x2.h> 19 #include <cortex_x3.h> 20 #include <cortex_x4.h> 21 #include <cortex_x925.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <neoverse_n2.h> 25 26 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 27 unsigned int check_if_affected_core(void) 28 { 29 uint32_t midr_val = read_midr(); 30 long rev_var = cpu_get_rev_var(); 31 32 if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) { 33 return check_erratum_cortex_a520_2938996(rev_var); 34 } else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) { 35 return check_erratum_cortex_x4_2726228(rev_var); 36 } 37 38 return ERRATA_NOT_APPLIES; 39 } 40 #endif 41 42 #if ERRATA_A75_764081 43 bool errata_a75_764081_applies(void) 44 { 45 long rev_var = cpu_get_rev_var(); 46 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 47 return true; 48 } 49 return false; 50 } 51 #endif /* ERRATA_A75_764081 */ 52 53 bool errata_ich_vmcr_el2_applies(void) 54 { 55 switch (EXTRACT_PARTNUM(read_midr())) { 56 #if ERRATA_A710_3701772 57 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 58 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 59 return true; 60 break; 61 #endif /* ERRATA_A710_3701772 */ 62 63 #if ERRATA_A715_3699560 64 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 65 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 66 return true; 67 break; 68 #endif /* ERRATA_A715_3699560 */ 69 70 #if ERRATA_A720_3699561 71 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 72 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 73 return true;; 74 break; 75 #endif /* ERRATA_A720_3699561 */ 76 77 #if ERRATA_A720_AE_3699562 78 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 79 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 80 return true; 81 break; 82 #endif /* ERRATA_A720_AE_3699562 */ 83 84 #if ERRATA_A725_3699564 85 case EXTRACT_PARTNUM(CORTEX_A725_MIDR): 86 if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) 87 return true; 88 break; 89 #endif /* ERRATA_A725_3699564 */ 90 91 #if ERRATA_X2_3701772 92 case EXTRACT_PARTNUM(CORTEX_X2_MIDR): 93 if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 94 return true; 95 break; 96 #endif /* ERRATA_X2_3701772 */ 97 98 #if ERRATA_X3_3701769 99 case EXTRACT_PARTNUM(CORTEX_X3_MIDR): 100 if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) 101 return true; 102 break; 103 #endif /* ERRATA_X3_3701769 */ 104 105 #if ERRATA_X4_3701758 106 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 107 if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) 108 return true; 109 break; 110 #endif /* ERRATA_X4_3701758 */ 111 112 #if ERRATA_X925_3701747 113 case EXTRACT_PARTNUM(CORTEX_X925_MIDR): 114 if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES) 115 return true; 116 break; 117 #endif /* ERRATA_X925_3701747 */ 118 119 #if ERRATA_N2_3701773 120 case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR): 121 if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES) 122 return true; 123 break; 124 #endif /* ERRATA_N2_3701773 */ 125 126 default: 127 break; 128 } 129 130 return false; 131 } 132