1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x4_2726228 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR 32workaround_runtime_end cortex_x4, ERRATUM(2726228) 33 34check_erratum_custom_start cortex_x4, ERRATUM(2726228) 35 36 /* This erratum needs to be enabled for r0p0 and r0p1. 37 * Check if revision is less than or equal to r0p1. 38 */ 39 40#if ERRATA_X4_2726228 41 mov x1, #1 42 b cpu_rev_var_ls 43#else 44 mov x0, #ERRATA_MISSING 45#endif 46 ret 47check_erratum_custom_end cortex_x4, ERRATUM(2726228) 48 49/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 50workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 51 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 52workaround_reset_end cortex_x4, CVE(2024, 5660) 53 54check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 55 56workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 57 /* dsb before isb of power down sequence */ 58 dsb sy 59workaround_runtime_end cortex_x4, ERRATUM(2740089) 60 61check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 62 63workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 64 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 65workaround_reset_end cortex_x4, ERRATUM(2763018) 66 67check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 68 69workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 70 mrs x1, id_aa64pfr1_el1 71 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 72 cbz x2, #1f 73 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 741: 75workaround_reset_end cortex_x4, ERRATUM(2816013) 76 77check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 78 79workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 80 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 81workaround_reset_end cortex_x4, ERRATUM(2897503) 82 83check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 84 85workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 86 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 87workaround_reset_end cortex_x4, ERRATUM(2923985) 88 89check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 90 91workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 92 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 93 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 94 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 95workaround_reset_end cortex_x4, ERRATUM(3076789) 96 97check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 98 99workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 100#if IMAGE_BL31 101 /* 102 * The Cortex X4 generic vectors are overridden to apply errata 103 * mitigation on exception entry from lower ELs. 104 */ 105 override_vector_table wa_cve_vbar_cortex_x4 106#endif /* IMAGE_BL31 */ 107workaround_reset_end cortex_x4, CVE(2022, 23960) 108 109check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 110 111workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 112 /* --------------------------------- 113 * Sets BIT41 of CPUACTLR6_EL1 which 114 * disables L1 Data cache prefetcher 115 * --------------------------------- 116 */ 117 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 118workaround_reset_end cortex_x4, CVE(2024, 7881) 119 120check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 121 122cpu_reset_func_start cortex_x4 123 /* Disable speculative loads */ 124 msr SSBS, xzr 125cpu_reset_func_end cortex_x4 126 127 /* ---------------------------------------------------- 128 * HW will do the cache maintenance while powering down 129 * ---------------------------------------------------- 130 */ 131func cortex_x4_core_pwr_dwn 132 /* --------------------------------------------------- 133 * Enable CPU power down bit in power control register 134 * --------------------------------------------------- 135 */ 136 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 137 138 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV 139 140 isb 141 ret 142endfunc cortex_x4_core_pwr_dwn 143 144 /* --------------------------------------------- 145 * This function provides Cortex X4-specific 146 * register information for crash reporting. 147 * It needs to return with x6 pointing to 148 * a list of register names in ascii and 149 * x8 - x15 having values of registers to be 150 * reported. 151 * --------------------------------------------- 152 */ 153.section .rodata.cortex_x4_regs, "aS" 154cortex_x4_regs: /* The ascii list of register names to be reported */ 155 .asciz "cpuectlr_el1", "" 156 157func cortex_x4_cpu_reg_dump 158 adr x6, cortex_x4_regs 159 mrs x8, CORTEX_X4_CPUECTLR_EL1 160 ret 161endfunc cortex_x4_cpu_reg_dump 162 163declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \ 164 cortex_x4_reset_func, \ 165 CPU_NO_EXTRA1_FUNC, \ 166 CPU_NO_EXTRA2_FUNC, \ 167 CPU_NO_EXTRA3_FUNC, \ 168 check_erratum_cortex_x4_7881, \ 169 cortex_x4_core_pwr_dwn 170