1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <cortex_a75.h> 12 #include <cortex_a520.h> 13 #include <cortex_a710.h> 14 #include <cortex_a715.h> 15 #include <cortex_a720.h> 16 #include <cortex_a720_ae.h> 17 #include <cortex_a725.h> 18 #include <cortex_x2.h> 19 #include <cortex_x3.h> 20 #include <cortex_x4.h> 21 #include <cortex_x925.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <neoverse_n2.h> 25 #include <neoverse_n3.h> 26 27 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 28 unsigned int check_if_affected_core(void) 29 { 30 uint32_t midr_val = read_midr(); 31 long rev_var = cpu_get_rev_var(); 32 33 if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) { 34 return check_erratum_cortex_a520_2938996(rev_var); 35 } else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) { 36 return check_erratum_cortex_x4_2726228(rev_var); 37 } 38 39 return ERRATA_NOT_APPLIES; 40 } 41 #endif 42 43 #if ERRATA_A75_764081 44 bool errata_a75_764081_applies(void) 45 { 46 long rev_var = cpu_get_rev_var(); 47 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 48 return true; 49 } 50 return false; 51 } 52 #endif /* ERRATA_A75_764081 */ 53 54 bool errata_ich_vmcr_el2_applies(void) 55 { 56 switch (EXTRACT_PARTNUM(read_midr())) { 57 #if ERRATA_A710_3701772 58 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 59 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 60 return true; 61 break; 62 #endif /* ERRATA_A710_3701772 */ 63 64 #if ERRATA_A715_3699560 65 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 66 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 67 return true; 68 break; 69 #endif /* ERRATA_A715_3699560 */ 70 71 #if ERRATA_A720_3699561 72 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 73 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 74 return true;; 75 break; 76 #endif /* ERRATA_A720_3699561 */ 77 78 #if ERRATA_A720_AE_3699562 79 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 80 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 81 return true; 82 break; 83 #endif /* ERRATA_A720_AE_3699562 */ 84 85 #if ERRATA_A725_3699564 86 case EXTRACT_PARTNUM(CORTEX_A725_MIDR): 87 if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) 88 return true; 89 break; 90 #endif /* ERRATA_A725_3699564 */ 91 92 #if ERRATA_X2_3701772 93 case EXTRACT_PARTNUM(CORTEX_X2_MIDR): 94 if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 95 return true; 96 break; 97 #endif /* ERRATA_X2_3701772 */ 98 99 #if ERRATA_X3_3701769 100 case EXTRACT_PARTNUM(CORTEX_X3_MIDR): 101 if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) 102 return true; 103 break; 104 #endif /* ERRATA_X3_3701769 */ 105 106 #if ERRATA_X4_3701758 107 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 108 if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) 109 return true; 110 break; 111 #endif /* ERRATA_X4_3701758 */ 112 113 #if ERRATA_X925_3701747 114 case EXTRACT_PARTNUM(CORTEX_X925_MIDR): 115 if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES) 116 return true; 117 break; 118 #endif /* ERRATA_X925_3701747 */ 119 120 #if ERRATA_N2_3701773 121 case EXTRACT_PARTNUM(NEOVERSE_N2_MIDR): 122 if (check_erratum_neoverse_n2_3701773(cpu_get_rev_var()) == ERRATA_APPLIES) 123 return true; 124 break; 125 #endif /* ERRATA_N2_3701773 */ 126 127 #if ERRATA_N3_3699563 128 case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR): 129 if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES) 130 return true; 131 break; 132 #endif /* ERRATA_N3_3699563 */ 133 default: 134 break; 135 } 136 137 return false; 138 } 139