1 /* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* Runtime C routines for errata workarounds and common routines */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <cortex_a75.h> 12 #include <cortex_a520.h> 13 #include <cortex_a710.h> 14 #include <cortex_a715.h> 15 #include <cortex_a720.h> 16 #include <cortex_a720_ae.h> 17 #include <cortex_a725.h> 18 #include <cortex_x2.h> 19 #include <cortex_x3.h> 20 #include <cortex_x4.h> 21 #include <lib/cpus/cpu_ops.h> 22 #include <lib/cpus/errata.h> 23 24 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 25 unsigned int check_if_affected_core(void) 26 { 27 uint32_t midr_val = read_midr(); 28 long rev_var = cpu_get_rev_var(); 29 30 if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) { 31 return check_erratum_cortex_a520_2938996(rev_var); 32 } else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) { 33 return check_erratum_cortex_x4_2726228(rev_var); 34 } 35 36 return ERRATA_NOT_APPLIES; 37 } 38 #endif 39 40 #if ERRATA_A75_764081 41 bool errata_a75_764081_applies(void) 42 { 43 long rev_var = cpu_get_rev_var(); 44 if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) { 45 return true; 46 } 47 return false; 48 } 49 #endif /* ERRATA_A75_764081 */ 50 51 bool errata_ich_vmcr_el2_applies(void) 52 { 53 switch (EXTRACT_PARTNUM(read_midr())) { 54 #if ERRATA_A710_3701772 55 case EXTRACT_PARTNUM(CORTEX_A710_MIDR): 56 if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 57 return true; 58 break; 59 #endif /* ERRATA_A710_3701772 */ 60 61 #if ERRATA_A715_3699560 62 case EXTRACT_PARTNUM(CORTEX_A715_MIDR): 63 if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES) 64 return true; 65 break; 66 #endif /* ERRATA_A715_3699560 */ 67 68 #if ERRATA_A720_3699561 69 case EXTRACT_PARTNUM(CORTEX_A720_MIDR): 70 if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) 71 return true;; 72 break; 73 #endif /* ERRATA_A720_3699561 */ 74 75 #if ERRATA_A720_AE_3699562 76 case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR): 77 if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES) 78 return true; 79 break; 80 #endif /* ERRATA_A720_AE_3699562 */ 81 82 #if ERRATA_A725_3699564 83 case EXTRACT_PARTNUM(CORTEX_A725_MIDR): 84 if (check_erratum_cortex_a725_3699564(cpu_get_rev_var()) == ERRATA_APPLIES) 85 return true; 86 break; 87 #endif /* ERRATA_A725_3699564 */ 88 89 #if ERRATA_X2_3701772 90 case EXTRACT_PARTNUM(CORTEX_X2_MIDR): 91 if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES) 92 return true; 93 break; 94 #endif /* ERRATA_X2_3701772 */ 95 96 #if ERRATA_X3_3701769 97 case EXTRACT_PARTNUM(CORTEX_X3_MIDR): 98 if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES) 99 return true; 100 break; 101 #endif /* ERRATA_X3_3701769 */ 102 103 #if ERRATA_X4_3701758 104 case EXTRACT_PARTNUM(CORTEX_X4_MIDR): 105 if (check_erratum_cortex_x4_3701758(cpu_get_rev_var()) == ERRATA_APPLIES) 106 return true; 107 break; 108 #endif /* ERRATA_X4_3701758 */ 109 110 default: 111 break; 112 } 113 114 return false; 115 } 116