1 /* 2 * Copyright (c) 2022-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_features.h> 8 #include <common/debug.h> 9 #include <common/feat_detect.h> 10 #include <plat/common/platform.h> 11 12 static bool detection_done[PLATFORM_CORE_COUNT] = { false }; 13 14 /******************************************************************************* 15 * Function : check_feature 16 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and 17 * feature availability on the hardware. <min> is the smallest feature 18 * ID field value that is required for that feature. 19 * Triggers a panic later if a feature is forcefully enabled, but not 20 * available on the PE. Also will panic if the hardware feature ID field 21 * is larger than the maximum known and supported number, specified by <max>. 22 * 23 * We force inlining here to let the compiler optimise away the whole check 24 * if the feature is disabled at build time (FEAT_STATE_DISABLED). 25 ******************************************************************************/ 26 static inline bool __attribute((__always_inline__)) 27 check_feature(int state, unsigned long field, const char *feat_name, 28 unsigned int min, unsigned int max) 29 { 30 if (state == FEAT_STATE_ALWAYS && field < min) { 31 ERROR("FEAT_%s not supported by the PE\n", feat_name); 32 return true; 33 } 34 if (state >= FEAT_STATE_ALWAYS && field > max) { 35 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n", 36 feat_name, field, max); 37 return true; 38 } 39 40 return false; 41 } 42 43 static unsigned int read_feat_rng_trap_id_field(void) 44 { 45 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 46 ID_AA64PFR1_EL1_RNDR_TRAP_MASK); 47 } 48 49 static unsigned int read_feat_bti_id_field(void) 50 { 51 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, 52 ID_AA64PFR1_EL1_BT_MASK); 53 } 54 55 static unsigned int read_feat_sb_id_field(void) 56 { 57 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, 58 ID_AA64ISAR1_SB_MASK); 59 } 60 61 static unsigned int read_feat_csv2_id_field(void) 62 { 63 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, 64 ID_AA64PFR0_CSV2_MASK); 65 } 66 67 static unsigned int read_feat_debugv8p9_id_field(void) 68 { 69 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT, 70 ID_AA64DFR0_DEBUGVER_MASK); 71 } 72 73 static unsigned int read_feat_pmuv3_id_field(void) 74 { 75 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, 76 ID_AA64DFR0_PMUVER_MASK); 77 } 78 79 static unsigned int read_feat_vhe_id_field(void) 80 { 81 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, 82 ID_AA64MMFR1_EL1_VHE_MASK); 83 } 84 85 static unsigned int read_feat_spe_id_field(void) 86 { 87 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS_SHIFT, 88 ID_AA64DFR0_PMS_MASK); 89 } 90 91 static unsigned int read_feat_sve_id_field(void) 92 { 93 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, 94 ID_AA64PFR0_SVE_MASK); 95 } 96 97 static unsigned int read_feat_ras_id_field(void) 98 { 99 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, 100 ID_AA64PFR0_RAS_MASK); 101 } 102 103 static unsigned int read_feat_dit_id_field(void) 104 { 105 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, 106 ID_AA64PFR0_DIT_MASK); 107 } 108 109 static unsigned int read_feat_amu_id_field(void) 110 { 111 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, 112 ID_AA64PFR0_AMU_MASK); 113 } 114 115 static unsigned int read_feat_mpam_version(void) 116 { 117 return (unsigned int)((((read_id_aa64pfr0_el1() >> 118 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 119 ((read_id_aa64pfr1_el1() >> 120 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 121 } 122 123 static unsigned int read_feat_nv_id_field(void) 124 { 125 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, 126 ID_AA64MMFR2_EL1_NV_MASK); 127 } 128 129 static unsigned int read_feat_sel2_id_field(void) 130 { 131 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, 132 ID_AA64PFR0_SEL2_MASK); 133 } 134 135 static unsigned int read_feat_trf_id_field(void) 136 { 137 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, 138 ID_AA64DFR0_TRACEFILT_MASK); 139 } 140 static unsigned int get_armv8_5_mte_support(void) 141 { 142 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, 143 ID_AA64PFR1_EL1_MTE_MASK); 144 } 145 static unsigned int read_feat_rng_id_field(void) 146 { 147 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, 148 ID_AA64ISAR0_RNDR_MASK); 149 } 150 static unsigned int read_feat_fgt_id_field(void) 151 { 152 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, 153 ID_AA64MMFR0_EL1_FGT_MASK); 154 } 155 static unsigned int read_feat_ecv_id_field(void) 156 { 157 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, 158 ID_AA64MMFR0_EL1_ECV_MASK); 159 } 160 static unsigned int read_feat_twed_id_field(void) 161 { 162 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, 163 ID_AA64MMFR1_EL1_TWED_MASK); 164 } 165 166 static unsigned int read_feat_hcx_id_field(void) 167 { 168 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, 169 ID_AA64MMFR1_EL1_HCX_MASK); 170 } 171 static unsigned int read_feat_ls64_id_field(void) 172 { 173 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT, 174 ID_AA64ISAR1_LS64_MASK); 175 } 176 static unsigned int read_feat_aie_id_field(void) 177 { 178 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT, 179 ID_AA64MMFR3_EL1_AIE_MASK); 180 } 181 static unsigned int read_feat_pfar_id_field(void) 182 { 183 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT, 184 ID_AA64PFR1_EL1_PFAR_MASK); 185 } 186 static unsigned int read_feat_tcr2_id_field(void) 187 { 188 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, 189 ID_AA64MMFR3_EL1_TCRX_MASK); 190 } 191 static unsigned int read_feat_s2pie_id_field(void) 192 { 193 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, 194 ID_AA64MMFR3_EL1_S2PIE_MASK); 195 } 196 static unsigned int read_feat_s1pie_id_field(void) 197 { 198 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, 199 ID_AA64MMFR3_EL1_S1PIE_MASK); 200 } 201 static unsigned int read_feat_s2poe_id_field(void) 202 { 203 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, 204 ID_AA64MMFR3_EL1_S2POE_MASK); 205 } 206 static unsigned int read_feat_s1poe_id_field(void) 207 { 208 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, 209 ID_AA64MMFR3_EL1_S1POE_MASK); 210 } 211 static unsigned int read_feat_brbe_id_field(void) 212 { 213 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, 214 ID_AA64DFR0_BRBE_MASK); 215 } 216 static unsigned int read_feat_trbe_id_field(void) 217 { 218 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, 219 ID_AA64DFR0_TRACEBUFFER_MASK); 220 } 221 static unsigned int read_feat_sme_id_field(void) 222 { 223 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, 224 ID_AA64PFR1_EL1_SME_MASK); 225 } 226 static unsigned int read_feat_gcs_id_field(void) 227 { 228 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, 229 ID_AA64PFR1_EL1_GCS_MASK); 230 } 231 232 static unsigned int read_feat_rme_id_field(void) 233 { 234 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, 235 ID_AA64PFR0_FEAT_RME_MASK); 236 } 237 238 static unsigned int read_feat_pan_id_field(void) 239 { 240 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, 241 ID_AA64MMFR1_EL1_PAN_MASK); 242 } 243 244 static unsigned int read_feat_mtpmu_id_field(void) 245 { 246 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 247 ID_AA64DFR0_MTPMU_MASK); 248 249 } 250 251 static unsigned int read_feat_the_id_field(void) 252 { 253 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT, 254 ID_AA64PFR1_EL1_THE_MASK); 255 } 256 257 static unsigned int read_feat_sctlr2_id_field(void) 258 { 259 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 260 ID_AA64MMFR3_EL1_SCTLR2_MASK); 261 } 262 263 static unsigned int read_feat_d128_id_field(void) 264 { 265 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT, 266 ID_AA64MMFR3_EL1_D128_MASK); 267 } 268 static unsigned int read_feat_gcie_id_field(void) 269 { 270 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT, 271 ID_AA64PFR2_EL1_GCIE_MASK); 272 } 273 274 static unsigned int read_feat_ebep_id_field(void) 275 { 276 return ISOLATE_FIELD(read_id_aa64dfr1_el1(), ID_AA64DFR1_EBEP_SHIFT, 277 ID_AA64DFR1_EBEP_MASK); 278 } 279 280 static unsigned int read_feat_fpmr_id_field(void) 281 { 282 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT, 283 ID_AA64PFR2_EL1_FPMR_MASK); 284 } 285 286 static unsigned int read_feat_mops_id_field(void) 287 { 288 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT, 289 ID_AA64ISAR2_EL1_MOPS_MASK); 290 } 291 292 static unsigned int read_feat_fgwte3_id_field(void) 293 { 294 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 295 ID_AA64MMFR4_EL1_FGWTE3_MASK); 296 } 297 298 static unsigned int read_feat_cpa_id_field(void) 299 { 300 return ISOLATE_FIELD(read_id_aa64isar3_el1(), 301 ID_AA64ISAR3_EL1_CPA_SHIFT, 302 ID_AA64ISAR3_EL1_CPA_MASK); 303 } 304 305 static unsigned int read_feat_clrbhb_id_field(void) 306 { 307 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_CLRBHB_SHIFT, 308 ID_AA64ISAR2_CLRBHB_MASK); 309 } 310 311 static unsigned int read_feat_rme_gdi_id_field(void) 312 { 313 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), 314 ID_AA64MMFR4_EL1_RME_GDI_SHIFT, 315 ID_AA64MMFR4_EL1_RME_GDI_MASK); 316 } 317 318 static unsigned int read_feat_idte3_id_field(void) 319 { 320 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_IDS_SHIFT, 321 ID_AA64MMFR2_EL1_IDS_MASK); 322 } 323 324 static unsigned int read_feat_uinj_id_field(void) 325 { 326 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), 327 ID_AA64PFR2_EL1_UINJ_SHIFT, 328 ID_AA64PFR2_EL1_UINJ_MASK); 329 } 330 331 static unsigned int read_feat_lse_id_field(void) 332 { 333 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_ATOMIC_SHIFT, 334 ID_AA64ISAR0_ATOMIC_MASK); 335 } 336 337 static unsigned int read_feat_morello_field(void) 338 { 339 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_CE_SHIFT, 340 ID_AA64PFR1_EL1_CE_MASK); 341 } 342 343 /*********************************************************************************** 344 * TF-A supports many Arm architectural features starting from arch version 345 * (8.0 till 8.7+). These features are mostly enabled through build flags. This 346 * mechanism helps in validating these build flags in the early boot phase 347 * either in BL1 or BL31 depending on the platform and assists in identifying 348 * and notifying the features which are enabled but not supported by the PE. 349 * 350 * It reads all the enabled features ID-registers and ensures the features 351 * are supported by the PE. 352 * In case if they aren't it stops booting at an early phase and logs the error 353 * messages, notifying the platforms about the features that are not supported. 354 * 355 * Further the procedure is implemented with a tri-state approach for each feature: 356 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time 357 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. 358 * There will be panic if feature is not present at cold boot. 359 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime 360 * depending on hardware capability. 361 * 362 * For better readability, state values are defined with macros, namely: 363 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values 364 * { 0, 1, 2 }, respectively, as their naming. 365 **********************************************************************************/ 366 void detect_arch_features(unsigned int core_pos) 367 { 368 /* No need to keep checking after the first time for each core. */ 369 if (detection_done[core_pos]) { 370 return; 371 } 372 373 bool tainted = false; 374 375 /* v8.0 features */ 376 tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), 377 "SB", 1, 1); 378 tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), 379 "CSV2_2", 2, 3); 380 tainted |= check_feature(ENABLE_FEAT_CLRBHB, read_feat_clrbhb_id_field(), 381 "CLRBHB", 1, 1); 382 /* 383 * Even though the PMUv3 is an OPTIONAL feature, it is always 384 * implemented and Arm prescribes so. So assume it will be there and do 385 * away with a flag for it. This is used to check minor PMUv3px 386 * revisions so that we catch them as they come along 387 */ 388 tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), 389 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9); 390 391 tainted |= check_feature(USE_SPINLOCK_CAS, read_feat_lse_id_field(), 392 "LSE", 2, 2); 393 394 /* v8.1 features */ 395 tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), 396 "PAN", 1, 3); 397 tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), 398 "VHE", 1, 1); 399 tainted |= check_feature(ENABLE_SPE_FOR_NS, read_feat_spe_id_field(), 400 "SPE", 1, 4); 401 402 /* v8.2 features */ 403 tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), 404 "SVE", 1, 1); 405 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), 406 "RAS", 1, 2); 407 408 /* v8.3 features */ 409 /* the PAuth fields are very complicated, no min/max is checked */ 410 tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(), 411 "PAUTH", 1, 1); 412 413 /* v8.4 features */ 414 tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), 415 "DIT", 1, 1); 416 tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), 417 "AMUv1", 1, 2); 418 tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(), 419 "MOPS", 1, 1); 420 tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), 421 "MPAM", 1, 17); 422 tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), 423 "NV2", 2, 2); 424 tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), 425 "SEL2", 1, 1); 426 tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), 427 "TRF", 1, 1); 428 429 /* v8.5 features */ 430 tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), 431 "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); 432 tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), 433 "RNG", 1, 1); 434 tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(), 435 "BTI", 1, 1); 436 tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), 437 "RNG_TRAP", 1, 1); 438 439 /* v8.6 features */ 440 tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), 441 "AMUv1p1", 2, 2); 442 tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), 443 "FGT", 1, 2); 444 tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), 445 "FGT2", 2, 2); 446 tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), 447 "ECV", 1, 2); 448 tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), 449 "TWED", 1, 1); 450 451 /* 452 * even though this is a "DISABLE" it does confusingly perform feature 453 * enablement duties like all other flags here. Check it against the HW 454 * feature when we intend to diverge from the default behaviour 455 */ 456 tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), 457 "MTPMU", 1, 1); 458 459 /* v8.7 features */ 460 tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), 461 "HCX", 1, 1); 462 tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), 463 "LS64", 1, 3); 464 465 /* v8.9 features */ 466 tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), 467 "TCR2", 1, 1); 468 tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), 469 "S2PIE", 1, 1); 470 tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), 471 "S1PIE", 1, 1); 472 tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), 473 "S2POE", 1, 1); 474 tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), 475 "S1POE", 1, 1); 476 tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), 477 "CSV2_3", 3, 3); 478 tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(), 479 "DEBUGV8P9", 11, 11); 480 tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(), 481 "THE", 1, 1); 482 tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(), 483 "SCTLR2", 1, 1); 484 tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(), 485 "AIE", 1, 1); 486 tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(), 487 "PFAR", 1, 1); 488 489 /* v9.0 features */ 490 tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), 491 "BRBE", 1, 2); 492 tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), 493 "TRBE", 1, 1); 494 tainted |= check_feature(ENABLE_FEAT_UINJ, read_feat_uinj_id_field(), 495 "UINJ", 1, 1); 496 497 /* v9.2 features */ 498 tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), 499 "SME", 1, 2); 500 tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), 501 "SME2", 2, 2); 502 tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(), 503 "FPMR", 1, 1); 504 505 /* v9.3 features */ 506 tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(), 507 "D128", 1, 1); 508 tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(), 509 "GCIE", 1, 1); 510 tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL, 511 is_feat_mpam_pe_bw_ctrl_present(), 512 "MPAM_PE_BW_CTRL", 1, 1); 513 tainted |= check_feature(ENABLE_FEAT_EBEP, read_feat_ebep_id_field(), 514 "EBEP", 1, 1); 515 516 /* v9.4 features */ 517 tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), 518 "GCS", 1, 1); 519 tainted |= check_feature(ENABLE_RME, read_feat_rme_id_field(), 520 "RME", 1, 2); 521 tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), 522 "PAUTH_LR", 1, 1); 523 tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(), 524 "FGWTE3", 1, 1); 525 tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(), 526 "CPA2", 2, 2); 527 tainted |= check_feature(ENABLE_FEAT_RME_GDI, read_feat_rme_gdi_id_field(), 528 "RME_GDI", 1, 1); 529 tainted |= check_feature(ENABLE_FEAT_IDTE3, read_feat_idte3_id_field(), 530 "IDTE3", 2, 2); 531 532 /* Morello Arch feature */ 533 tainted |= check_feature(ENABLE_FEAT_MORELLO, read_feat_morello_field(), 534 "MORELLO_ARCH", 1, 1); 535 536 if (tainted) { 537 panic(); 538 } 539 540 detection_done[core_pos] = true; 541 } 542