1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 288 extensions. This flag can take the values 0 to 2, to align with the 289 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 290 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 291 and this option can be used to enable this feature on those systems as well. 292 This flag can take the values 0 to 2, the default is 0. 293 294- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 295 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 296 onwards. This flag can take the values 0 to 2, to align with the 297 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 298 299- ``ENABLE_FEAT_CLRBHB``: Numeric value to enable the CLRBHB instruction. 300 Clear Branch History clears the branch history for the current context to 301 the extent that branch history information created before the CLRBHB instruction 302 cannot be used by code. This is an optional architectural feature available on v8.0 303 onwards and is a mandatory feature from v8.9 onwards. 304 This flag can take the values of 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 305 Default value is ``0``. 306 307- ``ENABLE_FEAT_CPA2``: Numeric value to enable the ``FEAT_CPA2`` extension. 308 It enables checked pointer arithmetic in EL3, which will result in address 309 faults in the event that a pointer arithmetic overflow error occurs. This is 310 an optional feature starting from Arm v9.4 and This flag can take values 0 to 311 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 314 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 315 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 316 optional feature available on Arm v8.0 onwards. This flag can take values 317 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 318 Default value is ``0``. 319 320- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 321 extension. This feature is supported in AArch64 state only and is an optional 322 feature available in Arm v8.0 implementations. 323 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 324 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 325 mechanism. Default value is ``0``. 326 327- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 328 extension which allows the ability to implement more than 16 breakpoints 329 and/or watchpoints. This feature is mandatory from v8.9 and is optional 330 from v8.8. This flag can take the values of 0 to 2, to align with the 331 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 332 333- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 334 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 335 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 336 and upwards. This flag can take the values 0 to 2, to align with the 337 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 338 339- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 340 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 341 Physical Offset register) during EL2 to EL3 context save/restore operations. 342 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 343 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 344 mechanism. Default value is ``0``. 345 346- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 347 Mode Register feature, allowing access to the FPMR register. FPMR register 348 controls the behaviors of FP8 instructions. It is an optional architectural 349 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 350 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 351 352- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 353 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 354 Read Trap Register) during EL2 to EL3 context save/restore operations. 355 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 356 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 357 mechanism. Default value is ``0``. 358 359- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 360 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 361 during EL2 to EL3 context save/restore operations. 362 Its an optional architectural feature and is available from v8.8 and upwards. 363 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 364 mechanism. Default value is ``0``. 365 366- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for 367 Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to 368 restrict overwriting certain EL3 registers after boot. 369 This lockdown is established by setting individual trap bits for 370 system registers that are not expected to be overwritten after boot. 371 This feature is an optional architectural feature and is available from 372 Armv9.4 onwards. This flag can take values from 0 to 2, aligning with 373 the ``ENABLE_FEAT`` mechanism. The default value is 0. 374 375 .. note:: 376 This feature currently traps access to all EL3 registers in 377 ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``, 378 ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and 379 ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``). 380 If additional traps need to be disabled for specific platforms, 381 please contact the Arm team on `TF-A public mailing list`_. 382 383- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 384 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 385 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 386 mandatory architectural feature and is enabled from v8.7 and upwards. This 387 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_IDTE3``: Numeric value to set SCR_EL3.TID3/TID5 bits which 391 enables trapping of ID register reads by lower ELs to EL3. This allows EL3 392 to control the feature visibility to lower ELs by returning a sanitized value 393 based on current feature enablement status. Hypervisors are expected to 394 cache ID register during their boot stage. This flag can take the 395 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 396 Default value is ``0``. This feature is EXPERIMENTAL. 397 398 .. note:: 399 This feature traps all lower EL accesses to Group 3 and Group 5 400 ID registers to EL3. This can incur a performance impact and platforms 401 should enable them only if they have a specific need. 402 403- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 404 of memory operations) when INIT_UNUSED_NS_EL2=1. 405 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 406 require any settings from EL3 as the controls are present in EL2 registers 407 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 408 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 409 EL3 should configure the EL2 registers. This flag 410 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 411 Default value is ``0``. 412 413- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 414 if the platform wants to use this feature and MTE2 is enabled at ELX. 415 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 416 mechanism. Default value is ``0``. 417 418- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 419 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 420 permission fault for any privileged data access from EL1/EL2 to virtual 421 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 422 mandatory architectural feature and is enabled from v8.1 and upwards. This 423 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 424 mechanism. Default value is ``0``. 425 426- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 427 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 428 onwards. This feature requires PAUTH to be enabled via the 429 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 430 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 431 432- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 433 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 434 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 435 mechanism. Default value is ``0``. 436 437- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 438 extension. This feature is only supported in AArch64 state. This flag can 439 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 440 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 441 Armv8.5 onwards. 442 443- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 444 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 445 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 446 later CPUs. It is enabled from v8.5 and upwards and if needed can be 447 overidden from platforms explicitly. 448 449- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 450 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 451 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 452 mechanism. Default is ``0``. 453 454- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 455 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 456 available on Arm v8.6. This flag can take values 0 to 2, to align with the 457 ``ENABLE_FEAT`` mechanism. Default is ``0``. 458 459 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 460 delayed by the amount of value in ``TWED_DELAY``. 461 462- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 463 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 464 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 465 architectural feature and is enabled from v8.1 and upwards. It can take 466 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 467 Default value is ``0``. 468 469- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 470 allow access to TCR2_EL2 (extended translation control) from EL2 as 471 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 472 mandatory architectural feature and is enabled from v8.9 and upwards. This 473 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 474 mechanism. Default value is ``0``. 475 476- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 477 at EL2 and below, and context switch relevant registers. This flag 478 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 479 mechanism. Default value is ``0``. 480 481- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 482 at EL2 and below, and context switch relevant registers. This flag 483 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 484 mechanism. Default value is ``0``. 485 486- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 487 at EL2 and below, and context switch relevant registers. This flag 488 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 489 mechanism. Default value is ``0``. 490 491- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 492 at EL2 and below, and context switch relevant registers. This flag 493 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 494 mechanism. Default value is ``0``. 495 496- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 497 allow use of Guarded Control Stack from EL2 as well as adding the GCS 498 registers to the EL2 context save/restore operations. This flag can take 499 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 500 Default value is ``0``. 501 502 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 503 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 504 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 505 Default value is ``0``. 506 507- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 508 (Translation Hardening Extension) at EL2 and below, setting the bit 509 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 510 registers and context switch them. 511 Its an optional architectural feature and is available from v8.8 and upwards. 512 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 513 mechanism. Default value is ``0``. 514 515- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 516 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 517 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 518 context switch them. This feature is OPTIONAL from Armv8.0 implementations 519 and mandatory in Armv8.9 implementations. 520 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 521 mechanism. Default value is ``0``. 522 523- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 524 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 525 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 526 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 527 RCWSMASK_EL1. Its an optional architectural feature and is available from 528 9.3 and upwards. 529 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 530 mechanism. Default value is ``0``. 531 532- ``ENABLE_FEAT_UINJ``: Numerical value to enable FEAT_UINJ support which 533 is hardware based injection of undefined instruction exceptions. 534 The objective of this feature is to provide higher privilege software with a 535 future proofed mechanism to inject an Undefined Instruction exception into 536 lower privilege software. It is an optional architectural feature from v9.0 537 and mandatory from v9.6. This flag can take value of 0 to 2, 538 to align with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 539 540- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 541 support. This option is currently only supported for AArch64. On GCC it only 542 applies to TF-A proper, and not its libraries. If LTO on libraries (except 543 the libc) is desired a platform can pass `-flto -ffat-lto-objects` as long as 544 GCC >= 14 is in use. ``ENABLE_LTO`` is enabled by default on release builds. 545 Default is 0. 546 547- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 548 feature. MPAM is an optional Armv8.4 extension that enables various memory 549 system components and resources to define partitions; software running at 550 various ELs can assign themselves to desired partition to control their 551 performance aspects. 552 553 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 554 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 555 access their own MPAM registers without trapping into EL3. This option 556 doesn't make use of partitioning in EL3, however. Platform initialisation 557 code should configure and use partitions in EL3 as required. This option 558 defaults to ``2`` since MPAM is enabled by default for NS world only. 559 The flag is automatically disabled when the target 560 architecture is AArch32. 561 562- ``ENABLE_FEAT_MPAM_PE_BW_CTRL``: This option enables Armv9.3 MPAM 563 PE-side bandwidth controls and disables traps to EL3/EL2 (when 564 ``INIT_UNUSED_NS_EL2`` = 1). The flag accepts values from 0 to 2, in 565 line with the ``ENABLE_FEAT`` mechanism, and defaults to ``0``. 566 567- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 568 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 569 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 570 Default value is ``0``. 571 572- ``ENABLE_FEAT_AIE``: Numeric value to enable access to the (A)MAIR2 system 573 registers from non-secure world. This flag can take the values 0 to 2, to 574 align with the ``ENABLE_FEAT`` mechanism. 575 Default value is ``0``. 576 577- ``ENABLE_FEAT_PFAR``: Numeric value to enable access to the PFAR system 578 registers from non-secure world. This flag can take the values 0 to 2, to 579 align with the ``ENABLE_FEAT`` mechanism. 580 Default value is ``0``. 581 582- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 583 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 584 firmware to detect and limit high activity events to assist in SoC processor 585 power domain dynamic power budgeting and limit the triggering of whole-rail 586 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 587 588- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 589 support within generic code in TF-A. This option is currently only supported 590 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 591 in BL32 (SP_min) for AARCH32. Default is 0. 592 593- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 594 Measurement Framework(PMF). Default is 0. 595 596- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 597 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 598 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 599 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 600 software. 601 602- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 603 instrumentation which injects timestamp collection points into TF-A to 604 allow runtime performance to be measured. Currently, only PSCI is 605 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 606 as well. Default is 0. 607 608- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 609 extensions. This is an optional architectural feature for AArch64. 610 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 611 mechanism. The default is 2 but is automatically disabled when the target 612 architecture is AArch32. 613 614- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 615 (SVE) for the Non-secure world only. SVE is an optional architectural feature 616 for AArch64. This flag can take the values 0 to 2, to align with the 617 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 618 systems that have SPM_MM enabled. The default value is 2. 619 620 Note that when SVE is enabled for the Non-secure world, access 621 to SVE, SIMD and floating-point functionality from the Secure world is 622 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 623 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 624 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 625 world data in the Z-registers which are aliased by the SIMD and FP registers. 626 627- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 628 for the Secure world. SVE is an optional architectural feature for AArch64. 629 The default is 0 and it is automatically disabled when the target architecture 630 is AArch32. 631 632 .. note:: 633 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 634 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 635 ``CTX_INCLUDE_SVE_REGS`` is also needed. 636 637- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 638 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 639 default value is set to "none". "strong" is the recommended stack protection 640 level if this feature is desired. "none" disables the stack protection. For 641 all values other than "none", the ``plat_get_stack_protector_canary()`` 642 platform hook needs to be implemented. The value is passed as the last 643 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 644 645- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 646 option to enable the workarounds for all errata that TF-A implements. Normally 647 they should be explicitly enabled depending on each platform's needs. Not 648 recommended for release builds. This option is default set to 0. 649 650- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 651 flag depends on ``DECRYPTION_SUPPORT`` build flag. 652 653- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 654 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 655 656- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 657 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 658 on ``DECRYPTION_SUPPORT`` build flag. 659 660- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 661 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 662 build flag. 663 664- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 665 deprecated platform APIs, helper functions or drivers within Trusted 666 Firmware as error. It can take the value 1 (flag the use of deprecated 667 APIs as error) or 0. The default is 0. 668 669- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 670 configure an Arm® Ethos™-N NPU. To use this service the target platform's 671 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 672 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 673 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 674 675- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 676 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 677 ``TRUSTED_BOARD_BOOT`` to be enabled. 678 679- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 680 (```ethosn.bin```). This firmware image will be included in the FIP and 681 loaded at runtime. 682 683- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 684 targeted at EL3. When set ``0`` (default), no exceptions are expected or 685 handled at EL3, and a panic will result. The exception to this rule is when 686 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 687 occuring during normal world execution, are trapped to EL3. Any exception 688 trapped during secure world execution are trapped to the SPMC. This is 689 supported only for AArch64 builds. 690 691- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 692 injection from lower ELs, and this build option enables lower ELs to use 693 Error Records accessed via System Registers to inject faults. This is 694 applicable only to AArch64 builds. 695 696 This feature is intended for testing purposes only, and is advisable to keep 697 disabled for production images. 698 699- ``FIP_NAME``: This is an optional build option which specifies the FIP 700 filename for the ``fip`` target. Default is ``fip.bin``. 701 702- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 703 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 704 705- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 706 707 :: 708 709 0: Encryption is done with Secret Symmetric Key (SSK) which is common 710 for a class of devices. 711 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 712 unique per device. 713 714 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 715 716- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 717 tool to create certificates as per the Chain of Trust described in 718 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 719 include the certificates in the FIP and FWU_FIP. Default value is '0'. 720 721 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 722 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 723 the corresponding certificates, and to include those certificates in the 724 FIP and FWU_FIP. 725 726 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 727 images will not include support for Trusted Board Boot. The FIP will still 728 include the corresponding certificates. This FIP can be used to verify the 729 Chain of Trust on the host machine through other mechanisms. 730 731 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 732 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 733 will not include the corresponding certificates, causing a boot failure. 734 735- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 736 inherent support for specific EL3 type interrupts. Setting this build option 737 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 738 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 739 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 740 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 741 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 742 the Secure Payload interrupts needs to be synchronously handed over to Secure 743 EL1 for handling. The default value of this option is ``0``, which means the 744 Group 0 interrupts are assumed to be handled by Secure EL1. 745 746- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 747 Interrupts, resulting from errors in NS world, will be always trapped in 748 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 749 will be trapped in the current exception level (or in EL1 if the current 750 exception level is EL0). 751 752- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 753 software operations are required for CPUs to enter and exit coherency. 754 However, newer systems exist where CPUs' entry to and exit from coherency 755 is managed in hardware. Such systems require software to only initiate these 756 operations, and the rest is managed in hardware, minimizing active software 757 management. In such systems, this boolean option enables TF-A to carry out 758 build and run-time optimizations during boot and power management operations. 759 This option defaults to 0 and if it is enabled, then it implies 760 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 761 762 If this flag is disabled while the platform which TF-A is compiled for 763 includes cores that manage coherency in hardware, then a compilation error is 764 generated. This is based on the fact that a system cannot have, at the same 765 time, cores that manage coherency in hardware and cores that don't. In other 766 words, a platform cannot have, at the same time, cores that require 767 ``HW_ASSISTED_COHERENCY=1`` and cores that require 768 ``HW_ASSISTED_COHERENCY=0``. 769 770 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 771 translation library (xlat tables v2) must be used; version 1 of translation 772 library is not supported. 773 774- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 775 implementation defined system register accesses from lower ELs. Default 776 value is ``0``. 777 778- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 779 bottom, higher addresses at the top. This build flag can be set to '1' to 780 invert this behavior. Lower addresses will be printed at the top and higher 781 addresses at the bottom. 782 783- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 784 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 785 by default. Platforms without NS-EL2 in use must enable this flag. 786 787- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 788 used for generating the PKCS keys and subsequent signing of the certificate. 789 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 790 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 791 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 792 compatibility. The default value of this flag is ``rsa`` which is the TBBR 793 compliant PKCS#1 RSA 2.1 scheme. 794 795- ``KEY_SIZE``: This build flag enables the user to select the key size for 796 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 797 depend on the chosen algorithm and the cryptographic module. 798 799 +---------------------------+------------------------------------+ 800 | KEY_ALG | Possible key sizes | 801 +===========================+====================================+ 802 | rsa | 1024 , 2048 (default), 3072, 4096 | 803 +---------------------------+------------------------------------+ 804 | ecdsa | 256 (default), 384 | 805 +---------------------------+------------------------------------+ 806 | ecdsa-brainpool-regular | 256 (default) | 807 +---------------------------+------------------------------------+ 808 | ecdsa-brainpool-twisted | 256 (default) | 809 +---------------------------+------------------------------------+ 810 811- ``HASH_ALG``: This build flag enables the user to select the secure hash 812 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 813 The default value of this flag is ``sha256``. 814 815- ``HW_CONFIG_BASE``: This option specifies the location in memory where the DTB 816 should either be loaded by BL2 or can be found by later stages. 817 818- ``LDFLAGS``: Extra user options appended to the linkers' command line in 819 addition to the one set by the build system. 820 821- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 822 output compiled into the build. This should be one of the following: 823 824 :: 825 826 0 (LOG_LEVEL_NONE) 827 10 (LOG_LEVEL_ERROR) 828 20 (LOG_LEVEL_NOTICE) 829 30 (LOG_LEVEL_WARNING) 830 40 (LOG_LEVEL_INFO) 831 50 (LOG_LEVEL_VERBOSE) 832 833 All log output up to and including the selected log level is compiled into 834 the build. The default value is 40 in debug builds and 20 in release builds. 835 836 ``LOG_DEBUG``: Boolean option to enable support for module level internal 837 logs. There can be situation where a module has detail internal debugging 838 logs, these debugging logs may not be required to print even when log level 839 is VERBOSE. Such logs can be put under this flag. This is a file 840 level build flag. By default this should be disabled (``0``) in each file. 841 842- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 843 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 844 provide trust that the code taking the measurements and recording them has 845 not been tampered with. 846 847 This option defaults to 0. 848 849- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 850 851 This option defaults to 0. 852 853- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 854 select the TPM interface. Currently only one interface is supported: 855 856 :: 857 858 FIFO_SPI 859 860- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 861 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 862 863- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 864 options to the compiler. An example usage: 865 866 .. code:: make 867 868 MARCH_DIRECTIVE := -march=armv8.5-a 869 870- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 871 options to the compiler currently supporting only of the options. 872 GCC documentation: 873 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 874 875 An example usage: 876 877 .. code:: make 878 879 HARDEN_SLS := 1 880 881 This option defaults to 0. 882 883- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 884 specifies a file that contains the Non-Trusted World private key in PEM 885 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 886 will be used to save the key. 887 888- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 889 optional. It is only needed if the platform makefile specifies that it 890 is required in order to build the ``fwu_fip`` target. 891 892- ``NS_TIMER_SWITCH``: (deprecated) Enable save and restore for non-secure 893 timer register contents upon world switch. It can take either 0 (don't save 894 and restore) or 1 (do save and restore). 0 is the default. An SPD may set 895 this to 1 if it wants the timer registers to be saved and restored. This 896 option has been deprecated since it breaks Linux preemption model. 897 898- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 899 for the BL image. It can be either 0 (include) or 1 (remove). The default 900 value is 0. 901 902- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 903 the underlying hardware is not a full PL011 UART but a minimally compliant 904 generic UART, which is a subset of the PL011. The driver will not access 905 any register that is not part of the SBSA generic UART specification. 906 Default value is 0 (a full PL011 compliant UART is present). 907 908- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 909 must be subdirectory of any depth under ``plat/``, and must contain a 910 platform makefile named ``platform.mk``. For example, to build TF-A for the 911 Arm Juno board, select PLAT=juno. 912 913- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 914 each core as well as the global context. The data includes the memory used 915 by each world and each privileged exception level. This build option is 916 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 917 918- ``PLAT_EXTRA_LD_SCRIPT``: Allows the platform to include a custom LD script 919 snippet for any custom sections that cannot be expressed otherwise. Defaults 920 to 0. 921 922- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 923 instead of the normal boot flow. When defined, it must specify the entry 924 point address for the preloaded BL33 image. This option is incompatible with 925 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 926 over ``PRELOADED_BL33_BASE``. 927 928- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 929 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 930 registers when the cluster goes through a power cycle. This is disabled by 931 default and platforms that require this feature have to enable them. 932 933- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 934 vector address can be programmed or is fixed on the platform. It can take 935 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 936 programmable reset address, it is expected that a CPU will start executing 937 code directly at the right address, both on a cold and warm reset. In this 938 case, there is no need to identify the entrypoint on boot and the boot path 939 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 940 does not need to be implemented in this case. 941 942- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 943 possible for the PSCI power-state parameter: original and extended State-ID 944 formats. This flag if set to 1, configures the generic PSCI layer to use the 945 extended format. The default value of this flag is 0, which means by default 946 the original power-state format is used by the PSCI implementation. This flag 947 should be specified by the platform makefile and it governs the return value 948 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 949 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 950 set to 1 as well. 951 952- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 953 OS-initiated mode. This option defaults to 0. 954 955- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 956 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 957 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 958 defaults to 0. 959 960- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 961 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 962 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 963 NOTE: This flag enables use of IESB capability to reduce entry latency into 964 EL3 even when RAS error handling is not performed on the platform. Hence this 965 flag is recommended to be turned on Armv8.2 and later CPUs. 966 967- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 968 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 969 entrypoint) or 1 (CPU reset to BL31 entrypoint). 970 The default value is 0. 971 972- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 973 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 974 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 975 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 976 977- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 978- blocks) covered by a single bit of the bitlock structure during RME GPT 979- operations. The lower the block size, the better opportunity for 980- parallelising GPT operations but at the cost of more bits being needed 981- for the bitlock structure. This numeric parameter can take the values 982- from 0 to 512 and must be a power of 2. The value of 0 is special and 983- and it chooses a single spinlock for all GPT L1 table entries. Default 984- value is 1 which corresponds to block size of 512MB per bit of bitlock 985- structure. 986 987- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 988 supported contiguous blocks in GPT Library. This parameter can take the 989 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 990 descriptors. Default value is 512. 991 992- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 993 file that contains the ROT private key in PEM format or a PKCS11 URI and 994 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 995 accepted and it will be used to save the key. 996 997- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 998 certificate generation tool to save the keys used to establish the Chain of 999 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 1000 1001- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 1002 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 1003 target. 1004 1005- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1006 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 1007 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 1008 1009- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 1010 optional. It is only needed if the platform makefile specifies that it 1011 is required in order to build the ``fwu_fip`` target. 1012 1013- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 1014 Delegated Exception Interface to BL31 image. This defaults to ``0``. 1015 1016 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 1017 set to ``1``. 1018 1019- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 1020 isolated on separate memory pages. This is a trade-off between security and 1021 memory usage. See "Isolating code and read-only data on separate memory 1022 pages" section in :ref:`Firmware Design`. This flag is disabled by default 1023 and affects all BL images. 1024 1025- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 1026 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 1027 allocated in RAM discontiguous from the loaded firmware image. When set, the 1028 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 1029 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 1030 sections are placed in RAM immediately following the loaded firmware image. 1031 1032- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 1033 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 1034 discontiguous from loaded firmware images. When set, the platform need to 1035 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 1036 flag is disabled by default and NOLOAD sections are placed in RAM immediately 1037 following the loaded firmware image. 1038 1039- ``SEPARATE_BL2_FIP``: This option enables the separation of the BL2 FIP image 1040 from the main FIP image. When this option is enabled, the BL2 FIP image is built 1041 as a separate FIP image. The default value is 0. 1042 1043- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 1044 data structures to be put in a dedicated memory region as decided by platform 1045 integrator. Default value is ``0`` which means the SIMD context is put in BSS 1046 section of EL3 firmware. 1047 1048- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 1049 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 1050 UEFI+ACPI this can provide a certain amount of OS forward compatibility 1051 with newer platforms that aren't ECAM compliant. 1052 1053- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1054 This build option is only valid if ``ARCH=aarch64``. The value should be 1055 the path to the directory containing the SPD source, relative to 1056 ``services/spd/``; the directory is expected to contain a makefile called 1057 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1058 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1059 cannot be enabled when the ``SPM_MM`` option is enabled. 1060 1061- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1062 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1063 execution in BL1 just before handing over to BL31. At this point, all 1064 firmware images have been loaded in memory, and the MMU and caches are 1065 turned off. Refer to the "Debugging options" section for more details. 1066 1067- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1068 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1069 component runs at the EL3 exception level. The default value is ``0`` ( 1070 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1071 implementing the ``FEAT_SEL2`` extension). 1072 1073- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1074 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1075 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1076 1077- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1078 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1079 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1080 mechanism should be used. 1081 1082- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1083 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1084 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1085 extension. This is the default when enabling the SPM Dispatcher. When 1086 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1087 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1088 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1089 extension). 1090 1091- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1092 Partition Manager (SPM) implementation. The default value is ``0`` 1093 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1094 enabled (``SPD=spmd``). 1095 1096- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1097 description of secure partitions. The build system will parse this file and 1098 package all secure partition blobs into the FIP. This file is not 1099 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1100 1101- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1102 secure interrupts (caught through the FIQ line). Platforms can enable 1103 this directive if they need to handle such interruption. When enabled, 1104 the FIQ are handled in monitor mode and non secure world is not allowed 1105 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1106 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1107 1108- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1109 Platforms can configure this if they need to lower the hardware 1110 limit, for example due to asymmetric configuration or limitations of 1111 software run at lower ELs. The default is the architectural maximum 1112 of 2048 which should be suitable for most configurations, the 1113 hardware will limit the effective VL to the maximum physically supported 1114 VL. 1115 1116- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1117 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1118 1119- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1120 Boot feature. When set to '1', BL1 and BL2 images include support to load 1121 and verify the certificates and images in a FIP, and BL1 includes support 1122 for the Firmware Update. The default value is '0'. Generation and inclusion 1123 of certificates in the FIP and FWU_FIP depends upon the value of the 1124 ``GENERATE_COT`` option. 1125 1126 .. warning:: 1127 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1128 already exist in disk, they will be overwritten without further notice. 1129 1130- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1131 specifies a file that contains the Trusted World private key in PEM 1132 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1133 it will be used to save the key. 1134 1135- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1136 synchronous, (see "Initializing a BL32 Image" section in 1137 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1138 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1139 Default is 0. 1140 1141- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1142 routing model which routes non-secure interrupts asynchronously from TSP 1143 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1144 for saving and restoring the TSP context in this routing model. The 1145 default routing model (when the value is 0) is to route non-secure 1146 interrupts to TSP allowing it to save its context and hand over 1147 synchronously to EL3 via an SMC. 1148 1149 .. note:: 1150 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1151 must also be set to ``1``. 1152 1153- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1154 internal-trusted-storage) as SP in tb_fw_config device tree. 1155 1156- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1157 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1158 this delay. It can take values in the range (0-15). Default value is ``0`` 1159 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1160 Platforms need to explicitly update this value based on their requirements. 1161 1162- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1163 linker. When the ``LINKER`` build variable points to the armlink linker, 1164 this flag is enabled automatically. To enable support for armlink, platforms 1165 will have to provide a scatter file for the BL image. Currently, Tegra 1166 platforms use the armlink support to compile BL3-1 images. 1167 1168- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1169 memory region in the BL memory map or not (see "Use of Coherent memory in 1170 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1171 (Coherent memory region is included) or 0 (Coherent memory region is 1172 excluded). Default is 1. 1173 1174- ``USE_KERNEL_DT_CONVENTION``: When this option is enabled, the hardware 1175 device tree is passed to BL33 using register x0, aligning with the expectations 1176 of the Linux kernel on Arm platforms. If this option is disabled, a different 1177 register, typically x1, may be used instead. This build option is 1178 not necessary when firmware handoff is active (that is, when TRANSFER_LIST=1 1179 is set), and it will be removed once all platforms have transitioned to that 1180 convention. 1181 1182- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver. 1183 The DSU driver allows save/restore of DSU PMU registers through 1184 ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at 1185 EL1 and allows platforms to configure powerdown and power settings of DSU. 1186 1187- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1188 firmware configuration framework. This will move the io_policies into a 1189 configuration device tree, instead of static structure in the code base. 1190 1191- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1192 at runtime using fconf. If this flag is enabled, COT descriptors are 1193 statically captured in tb_fw_config file in the form of device tree nodes 1194 and properties. Currently, COT descriptors used by BL2 are moved to the 1195 device tree and COT descriptors used by BL1 are retained in the code 1196 base statically. 1197 1198- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1199 runtime using firmware configuration framework. The platform specific SDEI 1200 shared and private events configuration is retrieved from device tree rather 1201 than static C structures at compile time. This is only supported if 1202 SDEI_SUPPORT build flag is enabled. 1203 1204- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1205 and Group1 secure interrupts using the firmware configuration framework. The 1206 platform specific secure interrupt property descriptor is retrieved from 1207 device tree in runtime rather than depending on static C structure at compile 1208 time. 1209 1210- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1211 This feature creates a library of functions to be placed in ROM and thus 1212 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1213 is 0. 1214 1215- ``V``: Verbose build. If assigned anything other than 0, the build commands 1216 are printed. Default is 0. 1217 1218- ``VERSION_STRING``: String used in the log output for each TF-A image. 1219 Defaults to a string formed by concatenating the version number, build type 1220 and build string. 1221 1222- ``W``: Warning level. Some compiler warning options of interest have been 1223 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1224 each level enabling more warning options. Default is 0. 1225 1226 This option is closely related to the ``E`` option, which enables 1227 ``-Werror``. 1228 1229 - ``W=0`` (default) 1230 1231 Enables a wide assortment of warnings, most notably ``-Wall`` and 1232 ``-Wextra``, as well as various bad practices and things that are likely to 1233 result in errors. Includes some compiler specific flags. No warnings are 1234 expected at this level for any build. 1235 1236 - ``W=1`` 1237 1238 Enables warnings we want the generic build to include but are too time 1239 consuming to fix at the moment. It re-enables warnings taken out for 1240 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1241 to eventually be merged into ``W=0``. Some warnings are expected on some 1242 builds, but new contributions should not introduce new ones. 1243 1244 - ``W=2`` (recommended) 1245 1246 Enables warnings we want the generic build to include but cannot be enabled 1247 due to external libraries. This level is expected to eventually be merged 1248 into ``W=0``. Lots of warnings are expected, primarily from external 1249 libraries like zlib and compiler-rt, but new controbutions should not 1250 introduce new ones. 1251 1252 - ``W=3`` 1253 1254 Enables warnings that are informative but not necessary and generally too 1255 verbose and frequently ignored. A very large number of warnings are 1256 expected. 1257 1258 The exact set of warning flags depends on the compiler and TF-A warning 1259 level, however they are all succinctly set in the top-level Makefile. Please 1260 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1261 individual flags. 1262 1263- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1264 the CPU after warm boot. This is applicable for platforms which do not 1265 require interconnect programming to enable cache coherency (eg: single 1266 cluster platforms). If this option is enabled, then warm boot path 1267 enables D-caches immediately after enabling MMU. This option defaults to 0. 1268 1269- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1270 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1271 The default value of this flag is ``0``. 1272 1273 ``AT`` speculative errata workaround disables stage1 page table walk for 1274 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1275 produces either the correct result or failure without TLB allocation. 1276 1277 This boolean option enables errata for all below CPUs. 1278 1279 +---------+--------------+-------------------------+ 1280 | Errata | CPU | Workaround Define | 1281 +=========+==============+=========================+ 1282 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1283 +---------+--------------+-------------------------+ 1284 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1285 +---------+--------------+-------------------------+ 1286 | 1541130 | Cortex-A65 | ``ERRATA_A65_1541130`` | 1287 +---------+--------------+-------------------------+ 1288 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1289 +---------+--------------+-------------------------+ 1290 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1291 +---------+--------------+-------------------------+ 1292 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1293 +---------+--------------+-------------------------+ 1294 1295 .. note:: 1296 This option is enabled by build only if platform sets any of above defines 1297 mentioned in ’Workaround Define' column in the table. 1298 If this option is enabled for the EL3 software then EL2 software also must 1299 implement this workaround due to the behaviour of the errata mentioned 1300 in new SDEN document which will get published soon. 1301 1302- ``ERRATA_SME_POWER_DOWN``: Boolean option to disable SME (PSTATE.{ZA,SM}=0) 1303 before power down and downgrade a suspend to power down request to a normal 1304 suspend request. This is necessary when software running at lower ELs requests 1305 power down without first clearing these bits. On affected cores, the CME 1306 connected to it will reject its power down request. The default value is 0. 1307 1308- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1309 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1310 This flag is disabled by default. 1311 1312- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1313 host machine where a custom installation of OpenSSL is located, which is used 1314 to build the certificate generation, firmware encryption and FIP tools. If 1315 this option is not set, the default OS installation will be used. 1316 1317- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1318 functions that wait for an arbitrary time length (udelay and mdelay). The 1319 default value is 0. 1320 1321- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1322 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1323 optional architectural feature for AArch64. This flag can take the values 1324 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1325 and it is automatically disabled when the target architecture is AArch32. 1326 1327- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1328 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1329 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1330 feature for AArch64. This flag can take the values 0 to 2, to align with the 1331 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1332 disabled when the target architecture is AArch32. 1333 1334- ``USE_SPINLOCK_CAS``: Numeric value to use FEAT_LSE atomics instead of 1335 load/store exclusive instructions with spinlocks. FEAT_LSE is a mandatory 1336 feature from v8.1, however it is only architecturally guaranteed to work on 1337 "conventional memory" which may not apply to tightly coupled memory (eg. SRAM, 1338 TF-A's usual place). Platforms must check if TF-A's memory can be targetted 1339 by atomics before enabling this feature. Expected to increase performance on 1340 systems with many cores. This flag can take the values 0 to 2, to align with 1341 the ``ENABLE_FEAT`` mechanism. The default is 0. 1342 1343- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1344 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1345 but unused). This feature is available if trace unit such as ETMv4.x, and 1346 ETE(extending ETM feature) is implemented. This flag can take the values 1347 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1348 1349- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1350 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1351 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1352 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1353 1354- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1355 ``plat_can_cmo`` which will return zero if cache management operations should 1356 be skipped and non-zero otherwise. By default, this option is disabled which 1357 means platform hook won't be checked and CMOs will always be performed when 1358 related functions are called. 1359 1360- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1361 firmware interface for the BL31 image. By default its disabled (``0``). 1362 1363- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1364 errata mitigation for platforms with a non-arm interconnect using the errata 1365 ABI. By default its disabled (``0``). 1366 1367- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1368 driver(s). By default it is disabled (``0``) because it constitutes an attack 1369 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1370 This option should only be enabled on a need basis if there is a use case for 1371 reading characters from the console. 1372 1373GIC driver options 1374-------------------- 1375 1376The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1377a numeric option that can take the following values: 1378 1379 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1380 code. Strongly discouraged for GIC based interrupt controllers. 1381 1382 - ``1``: enable the use of the generic GIC driver but do not include any files 1383 or function definitions. It is then the platform's responsibility to provide 1384 these. This is useful if the platform either has a custom GIC implementation 1385 or an alternative interrupt controller design. Use of this option is strongly 1386 discouraged for standard GIC implementations. 1387 1388 - ``2``: use the GICv2 driver 1389 1390 - ``3``: use the GICv3 driver. See the next section on how to further configure 1391 it. Use this option for GICv4 implementations. Requires calling 1392 ``gic_set_gicr_frames()``. 1393 1394 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1395 1396 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1397 context on a power domain state transition, as well as any GIC actions outside 1398 of the PSCI library's visibility are the platform's responsibility. The driver 1399 provides implementations of all necessary subroutines, they only need to be 1400 called as appropriate. 1401 1402GICv3 driver options 1403~~~~~~~~~~~~~~~~~~~~ 1404 1405``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1406old (deprecated) way of included them is using the directive: 1407``include drivers/arm/gic/v3/gicv3.mk`` 1408 1409The driver can be configured with the following options set in the platform 1410makefile: 1411 1412- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1413 Enabling this option will add runtime detection support for the 1414 GIC-600, so is safe to select even for a GIC500 implementation. 1415 This option defaults to 0. 1416 1417- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1418 for GIC-600 AE. Enabling this option will introduce support to initialize 1419 the FMU. Platforms should call the init function during boot to enable the 1420 FMU and its safety mechanisms. This option defaults to 0. 1421 1422- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1423 functionality. This option defaults to 0 1424 1425- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1426 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1427 functions. This is required for FVP platform which need to simulate GIC save 1428 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1429 1430- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1431 This option defaults to 0. 1432 1433- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1434 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1435 1436Debugging options 1437----------------- 1438 1439To compile a debug version and make the build more verbose use 1440 1441.. code:: shell 1442 1443 make PLAT=<platform> DEBUG=1 V=1 all 1444 1445AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1446(for example Arm-DS) might not support this and may need an older version of 1447DWARF symbols to be emitted by GCC. This can be achieved by using the 1448``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1449the version to 4 is recommended for Arm-DS. 1450 1451When debugging logic problems it might also be useful to disable all compiler 1452optimizations by using ``-O0``. 1453 1454.. warning:: 1455 Using ``-O0`` could cause output images to be larger and base addresses 1456 might need to be recalculated (see the **Memory layout on Arm development 1457 platforms** section in the :ref:`Firmware Design`). 1458 1459Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1460``LDFLAGS``: 1461 1462.. code:: shell 1463 1464 CFLAGS='-O0 -gdwarf-2' \ 1465 make PLAT=<platform> DEBUG=1 V=1 all 1466 1467Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1468ignored as the linker is called directly. 1469 1470It is also possible to introduce an infinite loop to help in debugging the 1471post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1472``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1473section. In this case, the developer may take control of the target using a 1474debugger when indicated by the console output. When using Arm-DS, the following 1475commands can be used: 1476 1477:: 1478 1479 # Stop target execution 1480 interrupt 1481 1482 # 1483 # Prepare your debugging environment, e.g. set breakpoints 1484 # 1485 1486 # Jump over the debug loop 1487 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1488 1489 # Resume execution 1490 continue 1491 1492.. _build_options_experimental: 1493 1494Experimental build options 1495--------------------------- 1496 1497Common build options 1498~~~~~~~~~~~~~~~~~~~~ 1499 1500- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1501 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1502 set to ``1`` then measurements and additional metadata collected during the 1503 measured boot process are sent to the DICE Protection Environment for storage 1504 and processing. A certificate chain, which represents the boot state of the 1505 device, can be queried from the DPE. 1506 1507- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1508 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1509 the measurements and recording them as per `PSA DRTM specification`_. For 1510 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1511 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1512 should have mechanism to authenticate BL31. This option defaults to 0. 1513 1514- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1515 Management Extension. This flag can take the values 0 to 2, to align with 1516 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1517 1518- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1519 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1520 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1521 contexts for Realm security state and only one encryption context for the 1522 rest of the security states. Default value is 0. 1523 1524- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1525 realm attestation token signing requests in EL3. This flag can take the 1526 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1527 enables additional RMMD SMCs to push and pop requests for signing to 1528 EL3 along with platform hooks that must be implemented to service those 1529 requests and responses. 1530 1531- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1532 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1533 registers so are enabled together. Using this option without 1534 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1535 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1536 superset of SVE. SME is an optional architectural feature for AArch64. 1537 At this time, this build option cannot be used on systems that have 1538 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1539 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1540 mechanism. Default is 0. 1541 1542- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1543 version 2 (SME2) for the non-secure world only. SME2 is an optional 1544 architectural feature for AArch64. 1545 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1546 accesses will still be trapped. This flag can take the values 0 to 2, to 1547 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1548 1549- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1550 Extension for secure world. Used along with SVE and FPU/SIMD. 1551 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1552 Default is 0. 1553 1554- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1555 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1556 for logical partitions in EL3, managed by the SPMD as defined in the 1557 FF-A v1.2 specification. This flag is disabled by default. This flag 1558 must not be used if ``SPMC_AT_EL3`` is enabled. 1559 1560- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1561 verification mechanism. This is a debug feature that compares the 1562 architectural features enabled through the feature specific build flags 1563 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1564 and reports any discrepancies. 1565 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1566 1567 It is expected that this feature is only used for flexible platforms like 1568 software emulators, or for hardware platforms at bringup time, to verify 1569 that the configured feature set matches the CPU. 1570 The ``FEATURE_DETECTION`` macro is disabled by default. 1571 1572- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1573 The platform will use PSA compliant Crypto APIs during authentication and 1574 image measurement process by enabling this option. It uses APIs defined as 1575 per the `PSA Crypto API specification`_. This feature is only supported if 1576 using MbedTLS 3.x version. It is disabled (``0``) by default. 1577 1578- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware 1579 activation as per the specification. This option defaults to 0. 1580 1581- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1582 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1583 This defaults to ``0``. Current implementation follows the Firmware Handoff 1584 specification v0.9. 1585 1586- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1587 interface through BL31 as a SiP SMC function. 1588 Default is disabled (0). 1589 1590- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1591 information using HOB defined in `Platform Initialization specification`_. 1592 This defaults to ``0``. 1593 1594- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1595 handler code to handle SMC calls from the Architecture Compliance Suite. The 1596 handler is intentionally empty to reserve the SMC section and allow 1597 project-specific implementations in future ACS use cases. 1598 1599Firmware update options 1600~~~~~~~~~~~~~~~~~~~~~~~ 1601 1602- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1603 `PSA FW update specification`_. The default value is 0. 1604 PSA firmware update implementation has few limitations, such as: 1605 1606 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1607 be updated, then it should be done through another platform-defined 1608 mechanism. 1609 1610 - It assumes the platform's hardware supports CRC32 instructions. 1611 1612- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1613 in defining the firmware update metadata structure. This flag is by default 1614 set to '2'. 1615 1616- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1617 firmware bank. Each firmware bank must have the same number of images as per 1618 the `PSA FW update specification`_. 1619 This flag is used in defining the firmware update metadata structure. This 1620 flag is by default set to '1'. 1621 1622- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1623 metadata contains image description. The default value is 1. 1624 1625 The version 2 of the FWU metadata allows for an opaque metadata 1626 structure where a platform can choose to not include the firmware 1627 store description in the metadata structure. This option indicates 1628 if the firmware store description, which provides information on 1629 the updatable images is part of the structure. 1630 1631-------------- 1632 1633*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 1634 1635.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1636.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1637.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1638.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1639.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1640.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1641.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1642.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1643.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ 1644