1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/idte3.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 PER_CPU_DEFINE(world_amu_regs_t, world_amu_ctx[CPU_CONTEXT_NUM]); 53 54 static void manage_extensions_nonsecure(cpu_context_t *ctx); 55 static void manage_extensions_secure(cpu_context_t *ctx); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 } 154 155 #if ENABLE_RME && IMAGE_BL31 156 /****************************************************************************** 157 * This function performs initializations that are specific to REALM state 158 * and updates the cpu context specified by 'ctx'. 159 * 160 * NOTE: any changes to this function must be verified by an RMMD maintainer. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 el2_sysregs_t *el2_ctx; 167 168 state = get_el3state_ctx(ctx); 169 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 170 el2_ctx = get_el2_sysregs_ctx(ctx); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 175 176 /* CSV2 version 2 and above */ 177 if (is_feat_csv2_2_supported()) { 178 /* Enable access to the SCXTNUM_ELx registers. */ 179 scr_el3 |= SCR_EnSCXT_BIT; 180 } 181 182 if (is_feat_sctlr2_supported()) { 183 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 184 * SCTLR2_ELx registers. 185 */ 186 scr_el3 |= SCR_SCTLR2En_BIT; 187 } 188 189 if (is_feat_d128_supported()) { 190 /* 191 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 192 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 193 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 194 */ 195 scr_el3 |= SCR_D128En_BIT; 196 } 197 198 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 199 200 if (is_feat_fgt2_supported()) { 201 fgt2_enable(ctx); 202 } 203 204 if (is_feat_debugv8p9_supported()) { 205 debugv8p9_extended_bp_wp_enable(ctx); 206 } 207 208 if (is_feat_brbe_supported()) { 209 brbe_enable(ctx); 210 } 211 212 /* 213 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 214 */ 215 if (is_feat_sme_supported()) { 216 sme_enable(ctx); 217 } 218 219 if (is_feat_spe_supported()) { 220 spe_disable_realm(ctx); 221 } 222 223 if (is_feat_trbe_supported()) { 224 trbe_disable_realm(ctx); 225 } 226 } 227 #endif /* ENABLE_RME && IMAGE_BL31 */ 228 229 /****************************************************************************** 230 * This function performs initializations that are specific to NON-SECURE state 231 * and updates the cpu context specified by 'ctx'. 232 *****************************************************************************/ 233 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 234 { 235 u_register_t scr_el3; 236 el3_state_t *state; 237 238 state = get_el3state_ctx(ctx); 239 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 240 241 /* SCR_NS: Set the NS bit */ 242 scr_el3 |= SCR_NS_BIT; 243 244 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 245 if (is_feat_mte2_supported()) { 246 scr_el3 |= SCR_ATA_BIT; 247 } 248 249 /* 250 * Pointer Authentication feature, if present, is always enabled by 251 * default for Non secure lower exception levels. We do not have an 252 * explicit flag to set it. To prevent the leakage between the worlds 253 * during world switch, we enable it only for the non-secure world. 254 * 255 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 256 * exception levels of secure and realm worlds. 257 * 258 * If the Secure/realm world wants to use pointer authentication, 259 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 260 * it will be enabled globally for all the contexts. 261 * 262 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 263 * other than EL3 264 * 265 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 266 * than EL3 267 */ 268 if (!is_ctx_pauth_supported()) { 269 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 270 } 271 272 #if HANDLE_EA_EL3_FIRST_NS 273 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 274 scr_el3 |= SCR_EA_BIT; 275 #endif 276 277 #if RAS_TRAP_NS_ERR_REC_ACCESS 278 /* 279 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 280 * and RAS ERX registers from EL1 and EL2(from any security state) 281 * are trapped to EL3. 282 * Set here to trap only for NS EL1/EL2 283 */ 284 scr_el3 |= SCR_TERR_BIT; 285 #endif 286 287 /* CSV2 version 2 and above */ 288 if (is_feat_csv2_2_supported()) { 289 /* Enable access to the SCXTNUM_ELx registers. */ 290 scr_el3 |= SCR_EnSCXT_BIT; 291 } 292 293 #ifdef IMAGE_BL31 294 /* 295 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 296 * indicated by the interrupt routing model for BL31. 297 */ 298 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 299 #endif 300 301 if (is_feat_the_supported()) { 302 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 303 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 304 */ 305 scr_el3 |= SCR_RCWMASKEn_BIT; 306 } 307 308 if (is_feat_sctlr2_supported()) { 309 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 310 * SCTLR2_ELx registers. 311 */ 312 scr_el3 |= SCR_SCTLR2En_BIT; 313 } 314 315 if (is_feat_d128_supported()) { 316 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 317 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 318 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 319 */ 320 scr_el3 |= SCR_D128En_BIT; 321 } 322 323 if (is_feat_fpmr_supported()) { 324 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 325 * register. 326 */ 327 scr_el3 |= SCR_EnFPM_BIT; 328 } 329 330 if (is_feat_aie_supported()) { 331 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 332 * system registers from NS world. 333 */ 334 scr_el3 |= SCR_AIEn_BIT; 335 } 336 337 if (is_feat_pfar_supported()) { 338 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 339 * system registers from NS world. 340 */ 341 scr_el3 |= SCR_PFAREn_BIT; 342 } 343 344 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 345 346 /* Initialize EL2 context registers */ 347 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 348 if (is_feat_hcx_supported()) { 349 /* 350 * Initialize register HCRX_EL2 with its init value. 351 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 352 * chance that this can lead to unexpected behavior in lower 353 * ELs that have not been updated since the introduction of 354 * this feature if not properly initialized, especially when 355 * it comes to those bits that enable/disable traps. 356 */ 357 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 358 HCRX_EL2_INIT_VAL); 359 } 360 361 if (is_feat_fgt_supported()) { 362 /* 363 * Initialize HFG*_EL2 registers with a default value so legacy 364 * systems unaware of FEAT_FGT do not get trapped due to their lack 365 * of initialization for this feature. 366 */ 367 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 368 HFGITR_EL2_INIT_VAL); 369 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 370 HFGRTR_EL2_INIT_VAL); 371 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 372 HFGWTR_EL2_INIT_VAL); 373 } 374 #else 375 /* Initialize EL1 context registers */ 376 setup_el1_context(ctx, ep); 377 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 378 379 manage_extensions_nonsecure(ctx); 380 } 381 382 static inline ddc_cap_t read_ddc_el0 (void) 383 { 384 ddc_cap_t val = NULL; 385 #if ENABLE_FEAT_MORELLO 386 __asm__ volatile ("msr spsel, #1 \n" 387 "mrs %0, ddc \n" 388 "msr spsel, #0 \n" 389 : "=C"(val) 390 : 391 : "memory" 392 ); 393 #endif 394 return val; 395 } 396 397 /******************************************************************************* 398 * The following function performs initialization of the cpu_context 'ctx' 399 * for first use that is common to all security states, and sets the 400 * initial entrypoint state as specified by the entry_point_info structure. 401 * 402 * The EE and ST attributes are used to configure the endianness and secure 403 * timer availability for the new execution context. 404 ******************************************************************************/ 405 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 406 { 407 u_register_t scr_el3; 408 u_register_t mdcr_el3; 409 el3_state_t *state; 410 gp_regs_t *gp_regs; 411 412 state = get_el3state_ctx(ctx); 413 414 /* Clear any residual register values from the context */ 415 zeromem(ctx, sizeof(*ctx)); 416 417 /* 418 * The lower-EL context is zeroed so that no stale values leak to a world. 419 * It is assumed that an all-zero lower-EL context is good enough for it 420 * to boot correctly. However, there are very few registers where this 421 * is not true and some values need to be recreated. 422 */ 423 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 424 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 425 426 /* 427 * These bits are set in the gicv3 driver. Losing them (especially the 428 * SRE bit) is problematic for all worlds. Henceforth recreate them. 429 */ 430 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 431 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 432 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 433 434 /* 435 * The actlr_el2 register can be initialized in platform's reset handler 436 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 437 */ 438 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 439 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 440 441 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 442 scr_el3 = SCR_RESET_VAL; 443 444 /* 445 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 446 * EL2, EL1 and EL0 are not trapped to EL3. 447 * 448 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 449 * EL2, EL1 and EL0 are not trapped to EL3. 450 * 451 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 452 * both Security states and both Execution states. 453 * 454 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 455 * Non-secure memory. 456 */ 457 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 458 459 scr_el3 |= SCR_SIF_BIT; 460 461 /* 462 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 463 * Exception level as specified by SPSR. 464 */ 465 if (GET_RW(ep->spsr) == MODE_RW_64) { 466 scr_el3 |= SCR_RW_BIT; 467 } 468 469 /* 470 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 471 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 472 * next mode is Hyp. 473 */ 474 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 475 || ((GET_RW(ep->spsr) != MODE_RW_64) 476 && (GET_M32(ep->spsr) == MODE32_hyp))) { 477 scr_el3 |= SCR_HCE_BIT; 478 } 479 480 /* 481 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 482 * Secure timer registers to EL3, from AArch64 state only, if specified 483 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 484 * bit always behaves as 1 (i.e. secure physical timer register access 485 * is not trapped) 486 */ 487 if (EP_GET_ST(ep->h.attr) != 0U) { 488 scr_el3 |= SCR_ST_BIT; 489 } 490 491 /* 492 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 493 * SCR_EL3.HXEn. 494 */ 495 if (is_feat_hcx_supported()) { 496 scr_el3 |= SCR_HXEn_BIT; 497 } 498 499 /* 500 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 501 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 502 * SCR_EL3.EnAS0. 503 */ 504 if (is_feat_ls64_accdata_supported()) { 505 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 506 } 507 508 /* 509 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 510 * registers are trapped to EL3. 511 */ 512 if (is_feat_rng_trap_supported()) { 513 scr_el3 |= SCR_TRNDR_BIT; 514 } 515 516 #if FAULT_INJECTION_SUPPORT 517 /* Enable fault injection from lower ELs */ 518 scr_el3 |= SCR_FIEN_BIT; 519 #endif 520 521 /* 522 * Enable Pointer Authentication globally for all the worlds. 523 * 524 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 525 * other than EL3 526 * 527 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 528 * than EL3 529 */ 530 if (is_ctx_pauth_supported()) { 531 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 532 } 533 534 /* 535 * SCR_EL3.PIEN: Enable permission indirection and overlay 536 * registers for AArch64 if present. 537 */ 538 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 539 scr_el3 |= SCR_PIEN_BIT; 540 } 541 542 /* SCR_EL3.GCSEn: Enable GCS registers. */ 543 if (is_feat_gcs_supported()) { 544 scr_el3 |= SCR_GCSEn_BIT; 545 } 546 547 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */ 548 if (is_feat_fgt_supported()) { 549 scr_el3 |= SCR_FGTEN_BIT; 550 } 551 552 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */ 553 if (is_feat_ecv_supported()) { 554 scr_el3 |= SCR_ECVEN_BIT; 555 } 556 557 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 558 if (is_feat_twed_supported()) { 559 /* Set delay in SCR_EL3 */ 560 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 561 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 562 << SCR_TWEDEL_SHIFT); 563 564 /* Enable WFE delay */ 565 scr_el3 |= SCR_TWEDEn_BIT; 566 } 567 568 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 569 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 570 if (is_feat_sel2_supported()) { 571 scr_el3 |= SCR_EEL2_BIT; 572 } 573 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 574 575 if (is_feat_mec_supported()) { 576 scr_el3 |= SCR_MECEn_BIT; 577 } 578 579 /* 580 * Populate EL3 state so that we've the right context 581 * before doing ERET 582 */ 583 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 584 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 585 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 586 587 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 588 mdcr_el3 = MDCR_EL3_RESET_VAL; 589 590 /* --------------------------------------------------------------------- 591 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 592 * Some fields are architecturally UNKNOWN on reset. 593 * 594 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 595 * Debug exceptions, other than Breakpoint Instruction exceptions, are 596 * disabled from all ELs in Secure state. 597 * 598 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 599 * privileged debug from S-EL1. 600 * 601 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 602 * access to the powerdown debug registers do not trap to EL3. 603 * 604 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 605 * debug registers, other than those registers that are controlled by 606 * MDCR_EL3.TDOSA. 607 */ 608 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 609 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 610 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 611 612 #if IMAGE_BL31 613 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 614 if (is_feat_trf_supported()) { 615 trf_enable(ctx); 616 } 617 618 if (is_feat_tcr2_supported()) { 619 tcr2_enable(ctx); 620 } 621 622 pmuv3_enable(ctx); 623 624 if (is_feat_idte3_supported()) { 625 idte3_enable(ctx); 626 } 627 628 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 629 /* 630 * Initialize SCTLR_EL2 context register with reset value. 631 */ 632 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 633 #endif /* CTX_INCLUDE_EL2_REGS */ 634 #endif /* IMAGE_BL31 */ 635 636 if (is_feat_morello_supported()) { 637 ctx->ddc_el0 = read_ddc_el0(); 638 } 639 640 /* 641 * Store the X0-X7 value from the entrypoint into the context 642 * Use memcpy as we are in control of the layout of the structures 643 */ 644 gp_regs = get_gpregs_ctx(ctx); 645 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 646 } 647 648 /******************************************************************************* 649 * Context management library initialization routine. This library is used by 650 * runtime services to share pointers to 'cpu_context' structures for secure 651 * non-secure and realm states. Management of the structures and their associated 652 * memory is not done by the context management library e.g. the PSCI service 653 * manages the cpu context used for entry from and exit to the non-secure state. 654 * The Secure payload dispatcher service manages the context(s) corresponding to 655 * the secure state. It also uses this library to get access to the non-secure 656 * state cpu context pointers. 657 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 658 * which will be used for programming an entry into a lower EL. The same context 659 * will be used to save state upon exception entry from that EL. 660 ******************************************************************************/ 661 void __init cm_init(void) 662 { 663 /* 664 * The context management library has only global data to initialize, but 665 * that will be done when the BSS is zeroed out. 666 */ 667 } 668 669 /******************************************************************************* 670 * This is the high-level function used to initialize the cpu_context 'ctx' for 671 * first use. It performs initializations that are common to all security states 672 * and initializations specific to the security state specified in 'ep' 673 ******************************************************************************/ 674 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 675 { 676 size_t security_state; 677 678 assert(ctx != NULL); 679 680 /* 681 * Perform initializations that are common 682 * to all security states 683 */ 684 setup_context_common(ctx, ep); 685 686 security_state = GET_SECURITY_STATE(ep->h.attr); 687 688 /* Perform security state specific initializations */ 689 switch (security_state) { 690 case SECURE: 691 setup_secure_context(ctx, ep); 692 break; 693 #if ENABLE_RME && IMAGE_BL31 694 case REALM: 695 setup_realm_context(ctx, ep); 696 break; 697 #endif 698 case NON_SECURE: 699 setup_ns_context(ctx, ep); 700 break; 701 default: 702 ERROR("Invalid security state\n"); 703 panic(); 704 break; 705 } 706 } 707 708 /******************************************************************************* 709 * Enable architecture extensions for EL3 execution. This function only updates 710 * registers in-place which are expected to either never change or be 711 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 712 ******************************************************************************/ 713 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 714 { 715 if (is_feat_pauth_supported()) { 716 pauth_init_enable_el3(); 717 } 718 719 #if IMAGE_BL31 720 if (is_feat_sve_supported()) { 721 sve_init_el3(); 722 } 723 724 if (is_feat_amu_supported()) { 725 amu_init_el3(my_idx); 726 } 727 728 if (is_feat_sme_supported()) { 729 sme_init_el3(); 730 } 731 732 if (is_feat_mpam_supported()) { 733 mpam_init_el3(); 734 } 735 736 if (is_feat_cpa2_supported()) { 737 cpa2_enable_el3(); 738 } 739 740 pmuv3_init_el3(); 741 742 /* NOTE: must be done last, makes the configuration immutable */ 743 if (is_feat_fgwte3_supported()) { 744 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 745 } 746 #endif /* IMAGE_BL31 */ 747 } 748 749 /****************************************************************************** 750 * Function to initialise the registers with the RESET values in the context 751 * memory, which are maintained per world. 752 ******************************************************************************/ 753 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 754 { 755 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL; 756 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 757 } 758 759 /******************************************************************************* 760 * Initialise per_world_context for Non-Secure world. 761 * This function enables the architecture extensions, which have same value 762 * across the cores for the non-secure world. 763 ******************************************************************************/ 764 static void manage_extensions_nonsecure_per_world(void) 765 { 766 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 767 768 #if IMAGE_BL31 769 if (is_feat_sme_supported()) { 770 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 771 } 772 773 if (is_feat_sve_supported()) { 774 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 775 } 776 777 if (is_feat_amu_supported()) { 778 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 779 } 780 781 if (is_feat_sys_reg_trace_supported()) { 782 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 783 } 784 785 if (is_feat_mpam_supported()) { 786 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 787 } 788 789 if (is_feat_idte3_supported()) { 790 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS); 791 } 792 #endif /* IMAGE_BL31 */ 793 } 794 795 /******************************************************************************* 796 * Initialise per_world_context for Secure world. 797 * This function enables the architecture extensions, which have same value 798 * across the cores for the secure world. 799 ******************************************************************************/ 800 static void manage_extensions_secure_per_world(void) 801 { 802 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 803 804 #if IMAGE_BL31 805 if (is_feat_sme_supported()) { 806 807 if (ENABLE_SME_FOR_SWD) { 808 /* 809 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 810 * SME, SVE, and FPU/SIMD context properly managed. 811 */ 812 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 813 } else { 814 /* 815 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 816 * world can safely use the associated registers. 817 */ 818 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 819 } 820 } 821 if (is_feat_sve_supported()) { 822 if (ENABLE_SVE_FOR_SWD) { 823 /* 824 * Enable SVE and FPU in secure context, SPM must ensure 825 * that the SVE and FPU register contexts are properly managed. 826 */ 827 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 828 } else { 829 /* 830 * Disable SVE and FPU in secure context so non-secure world 831 * can safely use them. 832 */ 833 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 834 } 835 } 836 837 /* NS can access this but Secure shouldn't */ 838 if (is_feat_sys_reg_trace_supported()) { 839 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 840 } 841 842 if (is_feat_idte3_supported()) { 843 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE); 844 } 845 #endif /* IMAGE_BL31 */ 846 } 847 848 static void manage_extensions_realm_per_world(void) 849 { 850 #if ENABLE_RME && IMAGE_BL31 851 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 852 853 if (is_feat_sve_supported()) { 854 /* 855 * Enable SVE and FPU in realm context when it is enabled for NS. 856 * Realm manager must ensure that the SVE and FPU register 857 * contexts are properly managed. 858 */ 859 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 860 } 861 862 /* NS can access this but Realm shouldn't */ 863 if (is_feat_sys_reg_trace_supported()) { 864 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 865 } 866 867 /* 868 * If SME/SME2 is supported and enabled for NS world, then disable trapping 869 * of SME instructions for Realm world. RMM will save/restore required 870 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 871 */ 872 if (is_feat_sme_supported()) { 873 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 874 } 875 876 /* 877 * If FEAT_MPAM is supported and enabled, then disable trapping access 878 * to the MPAM registers for Realm world. Instead, RMM will configure 879 * the access to be trapped by itself so it can inject undefined aborts 880 * back to the Realm. 881 */ 882 if (is_feat_mpam_supported()) { 883 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 884 } 885 886 if (is_feat_idte3_supported()) { 887 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); 888 } 889 #endif /* ENABLE_RME && IMAGE_BL31 */ 890 } 891 892 void cm_manage_extensions_per_world(void) 893 { 894 manage_extensions_nonsecure_per_world(); 895 manage_extensions_secure_per_world(); 896 manage_extensions_realm_per_world(); 897 } 898 899 void cm_init_percpu_once_regs(void) 900 { 901 #if IMAGE_BL31 902 if (is_feat_idte3_supported()) { 903 idte3_init_percpu_once_regs(CPU_CONTEXT_NS); 904 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); 905 #if ENABLE_RME 906 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM); 907 #endif /* ENABLE_RME */ 908 } 909 #endif /* IMAGE_BL31 */ 910 } 911 912 /******************************************************************************* 913 * Enable architecture extensions on first entry to Non-secure world. 914 ******************************************************************************/ 915 static void manage_extensions_nonsecure(cpu_context_t *ctx) 916 { 917 #if IMAGE_BL31 918 /* NOTE: registers are not context switched */ 919 if (is_feat_amu_supported()) { 920 amu_enable(ctx); 921 } 922 923 if (is_feat_sme_supported()) { 924 sme_enable(ctx); 925 } 926 927 if (is_feat_fgt2_supported()) { 928 fgt2_enable(ctx); 929 } 930 931 if (is_feat_debugv8p9_supported()) { 932 debugv8p9_extended_bp_wp_enable(ctx); 933 } 934 935 if (is_feat_spe_supported()) { 936 spe_enable_ns(ctx); 937 } 938 939 if (is_feat_trbe_supported()) { 940 if (check_if_trbe_disable_affected_core()) { 941 trbe_disable_ns(ctx); 942 } else { 943 trbe_enable_ns(ctx); 944 } 945 } 946 947 if (is_feat_brbe_supported()) { 948 brbe_enable(ctx); 949 } 950 #endif /* IMAGE_BL31 */ 951 } 952 953 #if INIT_UNUSED_NS_EL2 954 /******************************************************************************* 955 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 956 * world when EL2 is empty and unused. 957 ******************************************************************************/ 958 static void manage_extensions_nonsecure_el2_unused(void) 959 { 960 #if IMAGE_BL31 961 if (is_feat_spe_supported()) { 962 spe_init_el2_unused(); 963 } 964 965 if (is_feat_amu_supported()) { 966 amu_init_el2_unused(); 967 } 968 969 if (is_feat_mpam_supported()) { 970 mpam_init_el2_unused(); 971 } 972 973 if (is_feat_trbe_supported()) { 974 trbe_init_el2_unused(); 975 } 976 977 if (is_feat_sys_reg_trace_supported()) { 978 sys_reg_trace_init_el2_unused(); 979 } 980 981 if (is_feat_trf_supported()) { 982 trf_init_el2_unused(); 983 } 984 985 pmuv3_init_el2_unused(); 986 987 if (is_feat_sve_supported()) { 988 sve_init_el2_unused(); 989 } 990 991 if (is_feat_sme_supported()) { 992 sme_init_el2_unused(); 993 } 994 995 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 996 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 997 } 998 999 if (is_feat_pauth_supported()) { 1000 pauth_enable_el2(); 1001 } 1002 #endif /* IMAGE_BL31 */ 1003 } 1004 #endif /* INIT_UNUSED_NS_EL2 */ 1005 1006 /******************************************************************************* 1007 * Enable architecture extensions on first entry to Secure world. 1008 ******************************************************************************/ 1009 static void manage_extensions_secure(cpu_context_t *ctx) 1010 { 1011 #if IMAGE_BL31 1012 if (is_feat_sme_supported()) { 1013 if (ENABLE_SME_FOR_SWD) { 1014 /* 1015 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 1016 * must ensure SME, SVE, and FPU/SIMD context properly managed. 1017 */ 1018 sme_init_el3(); 1019 sme_enable(ctx); 1020 } else { 1021 /* 1022 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 1023 * world can safely use the associated registers. 1024 */ 1025 sme_disable(ctx); 1026 } 1027 } 1028 1029 if (is_feat_spe_supported()) { 1030 spe_disable_secure(ctx); 1031 } 1032 1033 if (is_feat_trbe_supported()) { 1034 trbe_disable_secure(ctx); 1035 } 1036 #endif /* IMAGE_BL31 */ 1037 } 1038 1039 /******************************************************************************* 1040 * The following function initializes the cpu_context for the current CPU 1041 * for first use, and sets the initial entrypoint state as specified by the 1042 * entry_point_info structure. 1043 ******************************************************************************/ 1044 void cm_init_my_context(const entry_point_info_t *ep) 1045 { 1046 cpu_context_t *ctx; 1047 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1048 cm_setup_context(ctx, ep); 1049 } 1050 1051 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1052 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1053 { 1054 #if INIT_UNUSED_NS_EL2 1055 u_register_t hcr_el2 = HCR_RESET_VAL; 1056 u_register_t mdcr_el2; 1057 u_register_t scr_el3; 1058 1059 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1060 1061 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1062 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1063 hcr_el2 |= HCR_RW_BIT; 1064 } 1065 1066 write_hcr_el2(hcr_el2); 1067 1068 /* 1069 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1070 * All fields have architecturally UNKNOWN reset values. 1071 */ 1072 write_cptr_el2(CPTR_EL2_RESET_VAL); 1073 1074 /* 1075 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1076 * reset and are set to zero except for field(s) listed below. 1077 * 1078 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1079 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1080 * 1081 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1082 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1083 */ 1084 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1085 1086 /* 1087 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1088 * UNKNOWN value. 1089 */ 1090 write_cntvoff_el2(0); 1091 1092 /* 1093 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1094 * respectively. 1095 */ 1096 write_vpidr_el2(read_midr_el1()); 1097 write_vmpidr_el2(read_mpidr_el1()); 1098 1099 /* 1100 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1101 * 1102 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1103 * translation is disabled, cache maintenance operations depend on the 1104 * VMID. 1105 * 1106 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1107 * disabled. 1108 */ 1109 write_vttbr_el2(VTTBR_RESET_VAL & 1110 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1111 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1112 1113 /* 1114 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1115 * Some fields are architecturally UNKNOWN on reset. 1116 * 1117 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1118 * register accesses to the Debug ROM registers are not trapped to EL2. 1119 * 1120 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1121 * accesses to the powerdown debug registers are not trapped to EL2. 1122 * 1123 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1124 * debug registers do not trap to EL2. 1125 * 1126 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1127 * EL2. 1128 */ 1129 mdcr_el2 = MDCR_EL2_RESET_VAL & 1130 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1131 MDCR_EL2_TDE_BIT); 1132 1133 write_mdcr_el2(mdcr_el2); 1134 1135 /* 1136 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1137 * 1138 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1139 * EL1 accesses to System registers do not trap to EL2. 1140 */ 1141 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1142 1143 /* 1144 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1145 * reset. 1146 * 1147 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1148 * and prevent timer interrupts. 1149 */ 1150 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1151 1152 manage_extensions_nonsecure_el2_unused(); 1153 #endif /* INIT_UNUSED_NS_EL2 */ 1154 } 1155 1156 /******************************************************************************* 1157 * Prepare the CPU system registers for first entry into realm, secure, or 1158 * normal world. 1159 * 1160 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1161 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1162 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1163 * For all entries, the EL1 registers are initialized from the cpu_context 1164 ******************************************************************************/ 1165 void cm_prepare_el3_exit(size_t security_state) 1166 { 1167 u_register_t sctlr_el2, scr_el3; 1168 cpu_context_t *ctx = cm_get_context(security_state); 1169 1170 assert(ctx != NULL); 1171 1172 if (security_state == NON_SECURE) { 1173 uint64_t el2_implemented = el_implemented(2); 1174 1175 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1176 CTX_SCR_EL3); 1177 1178 if (el2_implemented != EL_IMPL_NONE) { 1179 1180 /* 1181 * If context is not being used for EL2, initialize 1182 * HCRX_EL2 with its init value here. 1183 */ 1184 if (is_feat_hcx_supported()) { 1185 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1186 } 1187 1188 /* 1189 * Initialize Fine-grained trap registers introduced 1190 * by FEAT_FGT so all traps are initially disabled when 1191 * switching to EL2 or a lower EL, preventing undesired 1192 * behavior. 1193 */ 1194 if (is_feat_fgt_supported()) { 1195 /* 1196 * Initialize HFG*_EL2 registers with a default 1197 * value so legacy systems unaware of FEAT_FGT 1198 * do not get trapped due to their lack of 1199 * initialization for this feature. 1200 */ 1201 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1202 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1203 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1204 } 1205 1206 /* Condition to ensure EL2 is being used. */ 1207 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1208 /* Initialize SCTLR_EL2 register with reset value. */ 1209 sctlr_el2 = SCTLR_EL2_RES1; 1210 1211 /* 1212 * If workaround of errata 764081 for Cortex-A75 1213 * is used then set SCTLR_EL2.IESB to enable 1214 * Implicit Error Synchronization Barrier. 1215 */ 1216 if (errata_a75_764081_applies()) { 1217 sctlr_el2 |= SCTLR_IESB_BIT; 1218 } 1219 1220 write_sctlr_el2(sctlr_el2); 1221 } else { 1222 /* 1223 * (scr_el3 & SCR_HCE_BIT==0) 1224 * EL2 implemented but unused. 1225 */ 1226 init_nonsecure_el2_unused(ctx); 1227 } 1228 } 1229 1230 if (is_feat_fgwte3_supported()) { 1231 /* 1232 * TCR_EL3 and ACTLR_EL3 could be overwritten 1233 * by platforms and hence is locked a bit late. 1234 */ 1235 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1236 } 1237 } 1238 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 1239 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1240 cm_el1_sysregs_context_restore(security_state); 1241 #endif 1242 cm_set_next_eret_context(security_state); 1243 } 1244 1245 /* Assumes prepare_el3_entry() has disabled counters 2 and 3 */ 1246 void cm_sysregs_context_save_amu(unsigned int security_state) 1247 { 1248 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1249 1250 ctx->amevcntr02_el0 = read_amevcntr02_el0(); 1251 ctx->amevcntr03_el0 = read_amevcntr03_el0(); 1252 } 1253 1254 void cm_sysregs_context_restore_amu(unsigned int security_state) 1255 { 1256 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1257 1258 write_amevcntr02_el0(ctx->amevcntr02_el0); 1259 write_amevcntr03_el0(ctx->amevcntr03_el0); 1260 } 1261 1262 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1263 1264 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1265 { 1266 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1267 if (is_feat_amu_supported()) { 1268 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1269 } 1270 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1271 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1272 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1273 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1274 } 1275 1276 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1277 { 1278 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1279 if (is_feat_amu_supported()) { 1280 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1281 } 1282 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1283 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1284 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1285 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1286 } 1287 1288 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1289 { 1290 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1291 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1292 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1293 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1294 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1295 } 1296 1297 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1298 { 1299 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1300 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1301 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1302 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1303 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1304 } 1305 1306 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1307 { 1308 u_register_t mpam_idr = read_mpamidr_el1(); 1309 1310 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1311 1312 /* 1313 * The context registers that we intend to save would be part of the 1314 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1315 */ 1316 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1317 return; 1318 } 1319 1320 /* 1321 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1322 * MPAMIDR_HAS_HCR_BIT == 1. 1323 */ 1324 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1325 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1326 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1327 1328 /* 1329 * The number of MPAMVPM registers is implementation defined, their 1330 * number is stored in the MPAMIDR_EL1 register. 1331 */ 1332 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1333 case 7: 1334 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1335 __fallthrough; 1336 case 6: 1337 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1338 __fallthrough; 1339 case 5: 1340 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1341 __fallthrough; 1342 case 4: 1343 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1344 __fallthrough; 1345 case 3: 1346 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1347 __fallthrough; 1348 case 2: 1349 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1350 __fallthrough; 1351 case 1: 1352 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1353 break; 1354 } 1355 } 1356 1357 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1358 { 1359 u_register_t mpam_idr = read_mpamidr_el1(); 1360 1361 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1362 1363 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1364 return; 1365 } 1366 1367 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1368 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1369 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1370 1371 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1372 case 7: 1373 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1374 __fallthrough; 1375 case 6: 1376 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1377 __fallthrough; 1378 case 5: 1379 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1380 __fallthrough; 1381 case 4: 1382 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1383 __fallthrough; 1384 case 3: 1385 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1386 __fallthrough; 1387 case 2: 1388 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1389 __fallthrough; 1390 case 1: 1391 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1392 break; 1393 } 1394 } 1395 1396 /* --------------------------------------------------------------------------- 1397 * The following registers are not added: 1398 * ICH_AP0R<n>_EL2 1399 * ICH_AP1R<n>_EL2 1400 * ICH_LR<n>_EL2 1401 * 1402 * NOTE: For a system with S-EL2 present but not enabled, accessing 1403 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1404 * SCR_EL3.NS = 1 before accessing this register. 1405 * --------------------------------------------------------------------------- 1406 */ 1407 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1408 { 1409 u_register_t scr_el3 = read_scr_el3(); 1410 1411 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1412 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1413 #else 1414 write_scr_el3(scr_el3 | SCR_NS_BIT); 1415 isb(); 1416 1417 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1418 1419 write_scr_el3(scr_el3); 1420 isb(); 1421 #endif 1422 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1423 1424 if (errata_ich_vmcr_el2_applies()) { 1425 if (security_state == SECURE) { 1426 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1427 } else { 1428 write_scr_el3(scr_el3 | SCR_NS_BIT); 1429 } 1430 isb(); 1431 } 1432 1433 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1434 1435 if (errata_ich_vmcr_el2_applies()) { 1436 write_scr_el3(scr_el3); 1437 isb(); 1438 } 1439 } 1440 1441 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1442 { 1443 u_register_t scr_el3 = read_scr_el3(); 1444 1445 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1446 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1447 #else 1448 write_scr_el3(scr_el3 | SCR_NS_BIT); 1449 isb(); 1450 1451 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1452 1453 write_scr_el3(scr_el3); 1454 isb(); 1455 #endif 1456 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1457 1458 if (errata_ich_vmcr_el2_applies()) { 1459 if (security_state == SECURE) { 1460 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1461 } else { 1462 write_scr_el3(scr_el3 | SCR_NS_BIT); 1463 } 1464 isb(); 1465 } 1466 1467 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1468 1469 if (errata_ich_vmcr_el2_applies()) { 1470 write_scr_el3(scr_el3); 1471 isb(); 1472 } 1473 } 1474 1475 /* ----------------------------------------------------- 1476 * The following registers are not added: 1477 * AMEVCNTVOFF0<n>_EL2 1478 * AMEVCNTVOFF1<n>_EL2 1479 * ----------------------------------------------------- 1480 */ 1481 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1482 { 1483 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1484 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1485 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1486 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1487 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1488 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1489 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1490 if (CTX_INCLUDE_AARCH32_REGS) { 1491 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1492 } 1493 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1494 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1495 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1496 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1497 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1498 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1499 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1500 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1501 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1502 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1503 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1504 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1505 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1506 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1507 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1508 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1509 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1510 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1511 1512 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1513 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1514 } 1515 1516 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1517 { 1518 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1519 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1520 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1521 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1522 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1523 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1524 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1525 if (CTX_INCLUDE_AARCH32_REGS) { 1526 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1527 } 1528 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1529 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1530 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1531 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1532 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1533 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1534 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1535 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1536 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1537 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1538 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1539 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1540 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1541 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1542 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1543 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1544 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1545 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1546 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1547 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1548 } 1549 1550 /******************************************************************************* 1551 * Save EL2 sysreg context 1552 ******************************************************************************/ 1553 void cm_el2_sysregs_context_save(uint32_t security_state) 1554 { 1555 cpu_context_t *ctx; 1556 el2_sysregs_t *el2_sysregs_ctx; 1557 1558 ctx = cm_get_context(security_state); 1559 assert(ctx != NULL); 1560 1561 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1562 1563 el2_sysregs_context_save_common(el2_sysregs_ctx); 1564 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1565 1566 if (is_feat_mte2_supported()) { 1567 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1568 } 1569 1570 if (is_feat_mpam_supported()) { 1571 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1572 } 1573 1574 if (is_feat_fgt_supported()) { 1575 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1576 } 1577 1578 if (is_feat_fgt2_supported()) { 1579 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1580 } 1581 1582 if (is_feat_ecv_v2_supported()) { 1583 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1584 } 1585 1586 if (is_feat_vhe_supported()) { 1587 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1588 read_contextidr_el2()); 1589 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1590 } 1591 1592 if (is_feat_ras_supported()) { 1593 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1594 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1595 } 1596 1597 if (is_feat_nv2_supported()) { 1598 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1599 } 1600 1601 if (is_feat_trf_supported()) { 1602 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1603 } 1604 1605 if (is_feat_csv2_2_supported()) { 1606 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1607 read_scxtnum_el2()); 1608 } 1609 1610 if (is_feat_hcx_supported()) { 1611 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1612 } 1613 1614 if (is_feat_tcr2_supported()) { 1615 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1616 } 1617 1618 if (is_feat_s1pie_supported()) { 1619 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1620 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1621 } 1622 1623 if (is_feat_s1poe_supported()) { 1624 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1625 } 1626 1627 if (is_feat_brbe_supported()) { 1628 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1629 } 1630 1631 if (is_feat_s2pie_supported()) { 1632 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1633 } 1634 1635 if (is_feat_gcs_supported()) { 1636 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1637 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1638 } 1639 1640 if (is_feat_sctlr2_supported()) { 1641 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1642 } 1643 1644 if (is_feat_amu_supported()) { 1645 cm_sysregs_context_save_amu(security_state); 1646 } 1647 } 1648 1649 /******************************************************************************* 1650 * Restore EL2 sysreg context 1651 ******************************************************************************/ 1652 void cm_el2_sysregs_context_restore(uint32_t security_state) 1653 { 1654 cpu_context_t *ctx; 1655 el2_sysregs_t *el2_sysregs_ctx; 1656 1657 ctx = cm_get_context(security_state); 1658 assert(ctx != NULL); 1659 1660 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1661 1662 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1663 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1664 1665 if (is_feat_mte2_supported()) { 1666 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1667 } 1668 1669 if (is_feat_mpam_supported()) { 1670 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1671 } 1672 1673 if (is_feat_fgt_supported()) { 1674 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1675 } 1676 1677 if (is_feat_fgt2_supported()) { 1678 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1679 } 1680 1681 if (is_feat_ecv_v2_supported()) { 1682 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1683 } 1684 1685 if (is_feat_vhe_supported()) { 1686 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1687 contextidr_el2)); 1688 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1689 } 1690 1691 if (is_feat_ras_supported()) { 1692 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1693 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1694 } 1695 1696 if (is_feat_nv2_supported()) { 1697 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1698 } 1699 1700 if (is_feat_trf_supported()) { 1701 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1702 } 1703 1704 if (is_feat_csv2_2_supported()) { 1705 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1706 scxtnum_el2)); 1707 } 1708 1709 if (is_feat_hcx_supported()) { 1710 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1711 } 1712 1713 if (is_feat_tcr2_supported()) { 1714 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1715 } 1716 1717 if (is_feat_s1pie_supported()) { 1718 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1719 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1720 } 1721 1722 if (is_feat_s1poe_supported()) { 1723 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1724 } 1725 1726 if (is_feat_s2pie_supported()) { 1727 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1728 } 1729 1730 if (is_feat_gcs_supported()) { 1731 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1732 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1733 } 1734 1735 if (is_feat_sctlr2_supported()) { 1736 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1737 } 1738 1739 if (is_feat_brbe_supported()) { 1740 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1741 } 1742 1743 if (is_feat_amu_supported()) { 1744 cm_sysregs_context_restore_amu(security_state); 1745 } 1746 } 1747 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1748 1749 /******************************************************************************* 1750 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1751 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1752 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1753 * cm_prepare_el3_exit function. 1754 ******************************************************************************/ 1755 void cm_prepare_el3_exit_ns(void) 1756 { 1757 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1758 #if ENABLE_ASSERTIONS 1759 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1760 assert(ctx != NULL); 1761 1762 /* Assert that EL2 is used. */ 1763 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1764 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1765 (el_implemented(2U) != EL_IMPL_NONE)); 1766 #endif /* ENABLE_ASSERTIONS */ 1767 1768 /* Restore EL2 sysreg contexts */ 1769 cm_el2_sysregs_context_restore(NON_SECURE); 1770 cm_set_next_eret_context(NON_SECURE); 1771 #else 1772 cm_prepare_el3_exit(NON_SECURE); 1773 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1774 1775 if (is_feat_amu_supported()) { 1776 cm_sysregs_context_restore_amu(NON_SECURE); 1777 } 1778 } 1779 1780 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1781 /******************************************************************************* 1782 * The next set of six functions are used by runtime services to save and restore 1783 * EL1 context on the 'cpu_context' structure for the specified security state. 1784 ******************************************************************************/ 1785 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1786 { 1787 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1788 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1789 1790 #if (!ERRATA_SPECULATIVE_AT) 1791 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1792 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1793 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1794 1795 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1796 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1797 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1798 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1799 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1800 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1801 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1802 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1803 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1804 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1805 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1806 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1807 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1808 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1809 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1810 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1811 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1812 1813 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1814 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1815 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1816 1817 if (CTX_INCLUDE_AARCH32_REGS) { 1818 /* Save Aarch32 registers */ 1819 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1820 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1821 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1822 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1823 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1824 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1825 } 1826 1827 /* Save counter-timer kernel control register */ 1828 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1829 #if NS_TIMER_SWITCH 1830 /* Save NS Timer registers */ 1831 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1832 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1833 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1834 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1835 #endif 1836 1837 if (is_feat_mte2_supported()) { 1838 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1839 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1840 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1841 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1842 } 1843 1844 if (is_feat_ras_supported()) { 1845 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1846 } 1847 1848 if (is_feat_s1pie_supported()) { 1849 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1850 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1851 } 1852 1853 if (is_feat_s1poe_supported()) { 1854 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1855 } 1856 1857 if (is_feat_s2poe_supported()) { 1858 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1859 } 1860 1861 if (is_feat_tcr2_supported()) { 1862 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1863 } 1864 1865 if (is_feat_trf_supported()) { 1866 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1867 } 1868 1869 if (is_feat_csv2_2_supported()) { 1870 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1871 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1872 } 1873 1874 if (is_feat_gcs_supported()) { 1875 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1876 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1877 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1878 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1879 } 1880 1881 if (is_feat_the_supported()) { 1882 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1883 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1884 } 1885 1886 if (is_feat_sctlr2_supported()) { 1887 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1888 } 1889 1890 if (is_feat_ls64_accdata_supported()) { 1891 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1892 } 1893 } 1894 1895 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1896 { 1897 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1898 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1899 1900 #if (!ERRATA_SPECULATIVE_AT) 1901 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1902 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1903 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1904 1905 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1906 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1907 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1908 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1909 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1910 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1911 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1912 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1913 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1914 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1915 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1916 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1917 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1918 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1919 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1920 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1921 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1922 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1923 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1924 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1925 1926 if (CTX_INCLUDE_AARCH32_REGS) { 1927 /* Restore Aarch32 registers */ 1928 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1929 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1930 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1931 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1932 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1933 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1934 } 1935 1936 /* Restore counter-timer kernel control register */ 1937 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1938 #if NS_TIMER_SWITCH 1939 /* Restore NS Timer registers */ 1940 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1941 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1942 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1943 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1944 #endif 1945 1946 if (is_feat_mte2_supported()) { 1947 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1948 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1949 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1950 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1951 } 1952 1953 if (is_feat_ras_supported()) { 1954 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1955 } 1956 1957 if (is_feat_s1pie_supported()) { 1958 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1959 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1960 } 1961 1962 if (is_feat_s1poe_supported()) { 1963 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1964 } 1965 1966 if (is_feat_s2poe_supported()) { 1967 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1968 } 1969 1970 if (is_feat_tcr2_supported()) { 1971 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1972 } 1973 1974 if (is_feat_trf_supported()) { 1975 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1976 } 1977 1978 if (is_feat_csv2_2_supported()) { 1979 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1980 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1981 } 1982 1983 if (is_feat_gcs_supported()) { 1984 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1985 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1986 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1987 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1988 } 1989 1990 if (is_feat_the_supported()) { 1991 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1992 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1993 } 1994 1995 if (is_feat_sctlr2_supported()) { 1996 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1997 } 1998 1999 if (is_feat_ls64_accdata_supported()) { 2000 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 2001 } 2002 } 2003 2004 /******************************************************************************* 2005 * The next couple of functions are used by runtime services to save and restore 2006 * EL1 context on the 'cpu_context' structure for the specified security state. 2007 ******************************************************************************/ 2008 void cm_el1_sysregs_context_save(uint32_t security_state) 2009 { 2010 cpu_context_t *ctx; 2011 2012 ctx = cm_get_context(security_state); 2013 assert(ctx != NULL); 2014 2015 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 2016 2017 #if IMAGE_BL31 2018 if (is_feat_amu_supported()) { 2019 cm_sysregs_context_save_amu(security_state); 2020 } 2021 2022 if (security_state == SECURE) { 2023 PUBLISH_EVENT(cm_exited_secure_world); 2024 } else { 2025 PUBLISH_EVENT(cm_exited_normal_world); 2026 } 2027 #endif 2028 } 2029 2030 void cm_el1_sysregs_context_restore(uint32_t security_state) 2031 { 2032 cpu_context_t *ctx; 2033 2034 ctx = cm_get_context(security_state); 2035 assert(ctx != NULL); 2036 2037 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 2038 2039 #if IMAGE_BL31 2040 if (is_feat_amu_supported()) { 2041 cm_sysregs_context_restore_amu(security_state); 2042 } 2043 2044 if (security_state == SECURE) { 2045 PUBLISH_EVENT(cm_entering_secure_world); 2046 } else { 2047 PUBLISH_EVENT(cm_entering_normal_world); 2048 } 2049 #endif 2050 } 2051 2052 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 2053 2054 /******************************************************************************* 2055 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 2056 * given security state with the given entrypoint 2057 ******************************************************************************/ 2058 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2059 { 2060 cpu_context_t *ctx; 2061 el3_state_t *state; 2062 2063 ctx = cm_get_context(security_state); 2064 assert(ctx != NULL); 2065 2066 /* Populate EL3 state so that ERET jumps to the correct entry */ 2067 state = get_el3state_ctx(ctx); 2068 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2069 } 2070 2071 /******************************************************************************* 2072 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2073 * pertaining to the given security state 2074 ******************************************************************************/ 2075 void cm_set_elr_spsr_el3(uint32_t security_state, 2076 uintptr_t entrypoint, uint32_t spsr) 2077 { 2078 cpu_context_t *ctx; 2079 el3_state_t *state; 2080 2081 ctx = cm_get_context(security_state); 2082 assert(ctx != NULL); 2083 2084 /* Populate EL3 state so that ERET jumps to the correct entry */ 2085 state = get_el3state_ctx(ctx); 2086 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2087 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2088 } 2089 2090 /******************************************************************************* 2091 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2092 * pertaining to the given security state using the value and bit position 2093 * specified in the parameters. It preserves all other bits. 2094 ******************************************************************************/ 2095 void cm_write_scr_el3_bit(uint32_t security_state, 2096 uint32_t bit_pos, 2097 uint32_t value) 2098 { 2099 cpu_context_t *ctx; 2100 el3_state_t *state; 2101 u_register_t scr_el3; 2102 2103 ctx = cm_get_context(security_state); 2104 assert(ctx != NULL); 2105 2106 /* Ensure that the bit position is a valid one */ 2107 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2108 2109 /* Ensure that the 'value' is only a bit wide */ 2110 assert(value <= 1U); 2111 2112 /* 2113 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2114 * and set it to its new value. 2115 */ 2116 state = get_el3state_ctx(ctx); 2117 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2118 scr_el3 &= ~(1UL << bit_pos); 2119 scr_el3 |= (u_register_t)value << bit_pos; 2120 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2121 } 2122 2123 /******************************************************************************* 2124 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2125 * given security state. 2126 ******************************************************************************/ 2127 u_register_t cm_get_scr_el3(uint32_t security_state) 2128 { 2129 const cpu_context_t *ctx; 2130 const el3_state_t *state; 2131 2132 ctx = cm_get_context(security_state); 2133 assert(ctx != NULL); 2134 2135 /* Populate EL3 state so that ERET jumps to the correct entry */ 2136 state = get_el3state_ctx(ctx); 2137 return read_ctx_reg(state, CTX_SCR_EL3); 2138 } 2139 2140 /******************************************************************************* 2141 * This function is used to program the context that's used for exception 2142 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2143 * the required security state 2144 ******************************************************************************/ 2145 void cm_set_next_eret_context(uint32_t security_state) 2146 { 2147 cpu_context_t *ctx; 2148 2149 ctx = cm_get_context(security_state); 2150 assert(ctx != NULL); 2151 2152 cm_set_next_context(ctx); 2153 } 2154