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Searched refs:HVD_REG_RESET_IDB_MIU_256 (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h237 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3481 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3497 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3458 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3533 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3574 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3471 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3511 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h250 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c3784 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h238 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h242 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c4389 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h242 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c4374 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DregHVD_EX.h242 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) macro
H A DhalHVD_EX.c4511 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256); in HAL_HVD_EX_InitHW()