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Searched refs:HVD_Delay_ms (Results 1 – 25 of 55) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/drv/hvd/
H A DdrvHVD_sub.c1336 HVD_Delay_ms(u32delaytime); in MDrv_HVD_Sub_Init()
1514 HVD_Delay_ms(1); in MDrv_HVD_Sub_Exit()
1593 HVD_Delay_ms(1); in MDrv_HVD_Sub_Flush()
1646 HVD_Delay_ms(1); in MDrv_HVD_Sub_Flush()
1763 HVD_Delay_ms(1); in MDrv_HVD_Sub_StepDecode()
2049 HVD_Delay_ms(1); in MDrv_HVD_Sub_DecodeIFrame()
2193 HVD_Delay_ms(1); in MDrv_HVD_Sub_SetDispSpeed()
2231 HVD_Delay_ms(1); in MDrv_HVD_Sub_SetSyncActive()
H A DdrvHVD_def.h338 #define HVD_Delay_ms(x) MsOS_DelayTask(x) macro
341 #define HVD_Delay_ms(x) msleep(x) macro
345 #define HVD_Delay_ms(x) \ macro
H A DdrvHVD.c1429 HVD_Delay_ms(u32delaytime); in MDrv_HVD_Init()
1607 HVD_Delay_ms(1); in MDrv_HVD_Exit()
1690 HVD_Delay_ms(1); in MDrv_HVD_Flush()
1752 HVD_Delay_ms(1); in MDrv_HVD_Flush()
1872 HVD_Delay_ms(1); in MDrv_HVD_StepDecode()
2158 HVD_Delay_ms(1); in MDrv_HVD_DecodeIFrame()
2302 HVD_Delay_ms(1); in MDrv_HVD_SetDispSpeed()
2340 HVD_Delay_ms(1); in MDrv_HVD_SetSyncActive()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_Sub_RstMVDParser()
1082 HVD_Delay_ms(1); in _HAL_HVD_Sub_SetRegCPU()
1717 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1724 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
1731 HVD_Delay_ms(1); in HAL_HVD_Sub_InitRegCPU()
2150 HVD_Delay_ms(1); in HAL_HVD_Sub_DeInit()
H A DhalHVD.c660 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete in _HAL_HVD_RstMVDParser()
1128 HVD_Delay_ms(1); in _HAL_HVD_SetRegCPU()
1851 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1858 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
1865 HVD_Delay_ms(1); in HAL_HVD_InitRegCPU()
2359 HVD_Delay_ms(1); in HAL_HVD_DeInit()
/utopia/UTPA2-700.0.x/modules/vdec_v2/drv/hvd_ex/
H A DdrvHVD_def.h395 #define HVD_Delay_ms(x) MsOS_DelayTask(x) macro
398 #define HVD_Delay_ms(x) msleep(x) macro
402 #define HVD_Delay_ms(x) \ macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c1873 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2039 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3268 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3417 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
3742 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4577 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4584 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4591 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5565 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
5570 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c2140 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2309 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3602 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3737 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
4033 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4668 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4675 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4682 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5616 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
6629 HVD_Delay_ms(1); in HAL_EVD_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/drv/hvd_v3/
H A DdrvHVD_def.h397 #define HVD_Delay_ms(x) MsOS_DelayTaskUs(1000*x) macro
400 #define HVD_Delay_ms(x) msleep(x) macro
404 #define HVD_Delay_ms(x) \ macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/drv/hvd_lite/
H A DdrvHVD_def.h407 #define HVD_Delay_ms(x) MsOS_DelayTask(x) macro
410 #define HVD_Delay_ms(x) msleep(x) macro
414 #define HVD_Delay_ms(x) \ macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c2002 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2168 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3393 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3525 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
3819 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4477 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4484 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4491 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5439 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
6392 HVD_Delay_ms(1); in HAL_EVD_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c1899 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2065 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3314 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3470 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
3790 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4626 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4633 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4640 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5641 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
5646 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c1873 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2039 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3281 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3430 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
3763 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4598 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4605 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4612 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5622 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
5627 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c1898 HVD_Delay_ms(1); in HAL_HVD_EX_IQMem_Init()
2064 HVD_Delay_ms(1); in _HVD_EX_SetRegCPU()
3300 HVD_Delay_ms(1); // FIXME in _HAL_HVD_EX_PostProc_Task()
3456 HVD_Delay_ms(1); in HAL_HVD_EX_InitHW()
3768 HVD_Delay_ms(1); in HAL_HVD_EX_DeinitHW()
4604 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4611 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
4618 HVD_Delay_ms(1); in HAL_HVD_EX_InitRegCPU()
5583 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
5588 HVD_Delay_ms(1); in HAL_HVD_EX_SetCmd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DhalVPU_EX.c2667 HVD_Delay_ms(1); in HAL_VPU_EX_Init()
2669 HVD_Delay_ms(1); in HAL_VPU_EX_Init()
2671 HVD_Delay_ms(1); in HAL_VPU_EX_Init()
2676 HVD_Delay_ms(1); in HAL_VPU_EX_Init()
2725 HVD_Delay_ms(1); in HAL_VPU_EX_DeInit()
2727 HVD_Delay_ms(1); in HAL_VPU_EX_DeInit()
2729 HVD_Delay_ms(1); in HAL_VPU_EX_DeInit()
2734 HVD_Delay_ms(1); in HAL_VPU_EX_DeInit()

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