1*53ee8cc1Swenshuai.xi //<MStar Software> 2*53ee8cc1Swenshuai.xi //****************************************************************************** 3*53ee8cc1Swenshuai.xi // MStar Software 4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are 6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties. 8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all 9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written 10*53ee8cc1Swenshuai.xi // permission has been granted by MStar. 11*53ee8cc1Swenshuai.xi // 12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you 13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to 14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations: 15*53ee8cc1Swenshuai.xi // 16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar 17*53ee8cc1Swenshuai.xi // Software and any modification/derivatives thereof. 18*53ee8cc1Swenshuai.xi // No right, ownership, or interest to MStar Software and any 19*53ee8cc1Swenshuai.xi // modification/derivatives thereof is transferred to you under Terms. 20*53ee8cc1Swenshuai.xi // 21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be 22*53ee8cc1Swenshuai.xi // supplied together with third party`s software and the use of MStar 23*53ee8cc1Swenshuai.xi // Software may require additional licenses from third parties. 24*53ee8cc1Swenshuai.xi // Therefore, you hereby agree it is your sole responsibility to separately 25*53ee8cc1Swenshuai.xi // obtain any and all third party right and license necessary for your use of 26*53ee8cc1Swenshuai.xi // such third party`s software. 27*53ee8cc1Swenshuai.xi // 28*53ee8cc1Swenshuai.xi // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29*53ee8cc1Swenshuai.xi // MStar`s confidential information and you agree to keep MStar`s 30*53ee8cc1Swenshuai.xi // confidential information in strictest confidence and not disclose to any 31*53ee8cc1Swenshuai.xi // third party. 32*53ee8cc1Swenshuai.xi // 33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34*53ee8cc1Swenshuai.xi // kind. Any warranties are hereby expressly disclaimed by MStar, including 35*53ee8cc1Swenshuai.xi // without limitation, any warranties of merchantability, non-infringement of 36*53ee8cc1Swenshuai.xi // intellectual property rights, fitness for a particular purpose, error free 37*53ee8cc1Swenshuai.xi // and in conformity with any international standard. You agree to waive any 38*53ee8cc1Swenshuai.xi // claim against MStar for any loss, damage, cost or expense that you may 39*53ee8cc1Swenshuai.xi // incur related to your use of MStar Software. 40*53ee8cc1Swenshuai.xi // In no event shall MStar be liable for any direct, indirect, incidental or 41*53ee8cc1Swenshuai.xi // consequential damages, including without limitation, lost of profit or 42*53ee8cc1Swenshuai.xi // revenues, lost or damage of data, and unauthorized system use. 43*53ee8cc1Swenshuai.xi // You agree that this Section 4 shall still apply without being affected 44*53ee8cc1Swenshuai.xi // even if MStar Software has been modified by MStar in accordance with your 45*53ee8cc1Swenshuai.xi // request or instruction for your use, except otherwise agreed by both 46*53ee8cc1Swenshuai.xi // parties in writing. 47*53ee8cc1Swenshuai.xi // 48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or 49*53ee8cc1Swenshuai.xi // services in relation with MStar Software to you for your use of 50*53ee8cc1Swenshuai.xi // MStar Software in conjunction with your or your customer`s product 51*53ee8cc1Swenshuai.xi // ("Services"). 52*53ee8cc1Swenshuai.xi // You understand and agree that, except otherwise agreed by both parties in 53*53ee8cc1Swenshuai.xi // writing, Services are provided on an "AS IS" basis and the warranty 54*53ee8cc1Swenshuai.xi // disclaimer set forth in Section 4 above shall apply. 55*53ee8cc1Swenshuai.xi // 56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels 57*53ee8cc1Swenshuai.xi // or otherwise: 58*53ee8cc1Swenshuai.xi // (a) conferring any license or right to use MStar name, trademark, service 59*53ee8cc1Swenshuai.xi // mark, symbol or any other identification; 60*53ee8cc1Swenshuai.xi // (b) obligating MStar or any of its affiliates to furnish any person, 61*53ee8cc1Swenshuai.xi // including without limitation, you and your customers, any assistance 62*53ee8cc1Swenshuai.xi // of any kind whatsoever, or any information; or 63*53ee8cc1Swenshuai.xi // (c) conferring any license or right under any intellectual property right. 64*53ee8cc1Swenshuai.xi // 65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws 66*53ee8cc1Swenshuai.xi // of Taiwan, R.O.C., excluding its conflict of law rules. 67*53ee8cc1Swenshuai.xi // Any and all dispute arising out hereof or related hereto shall be finally 68*53ee8cc1Swenshuai.xi // settled by arbitration referred to the Chinese Arbitration Association, 69*53ee8cc1Swenshuai.xi // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70*53ee8cc1Swenshuai.xi // Rules of the Association by three (3) arbitrators appointed in accordance 71*53ee8cc1Swenshuai.xi // with the said Rules. 72*53ee8cc1Swenshuai.xi // The place of arbitration shall be in Taipei, Taiwan and the language shall 73*53ee8cc1Swenshuai.xi // be English. 74*53ee8cc1Swenshuai.xi // The arbitration award shall be final and binding to both parties. 75*53ee8cc1Swenshuai.xi // 76*53ee8cc1Swenshuai.xi //****************************************************************************** 77*53ee8cc1Swenshuai.xi //<MStar Software> 78*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 79*53ee8cc1Swenshuai.xi // 80*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81*53ee8cc1Swenshuai.xi // All rights reserved. 82*53ee8cc1Swenshuai.xi // 83*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained 84*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of 85*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence 86*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient. 87*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure, 88*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling, 89*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential 90*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi /// 97*53ee8cc1Swenshuai.xi /// @file drvHVD.h 98*53ee8cc1Swenshuai.xi /// @brief HVD Driver Interface 99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc. 100*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 101*53ee8cc1Swenshuai.xi 102*53ee8cc1Swenshuai.xi #ifndef _DRV_HVD_DEF_H_ 103*53ee8cc1Swenshuai.xi #define _DRV_HVD_DEF_H_ 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi #include "drvHVD_Common.h" 106*53ee8cc1Swenshuai.xi 107*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 108*53ee8cc1Swenshuai.xi // Driver Capability 109*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 110*53ee8cc1Swenshuai.xi 111*53ee8cc1Swenshuai.xi // HW capability 112*53ee8cc1Swenshuai.xi #define HVD_HW_SVD 1 113*53ee8cc1Swenshuai.xi #define HVD_HW_HVD 2 114*53ee8cc1Swenshuai.xi #if defined(CHIP_T2) 115*53ee8cc1Swenshuai.xi #define HVD_HW_VERSION HVD_HW_SVD 116*53ee8cc1Swenshuai.xi #else 117*53ee8cc1Swenshuai.xi #define HVD_HW_VERSION HVD_HW_HVD 118*53ee8cc1Swenshuai.xi #endif 119*53ee8cc1Swenshuai.xi 120*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 121*53ee8cc1Swenshuai.xi // Macro and Define 122*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 123*53ee8cc1Swenshuai.xi // Feature switch 124*53ee8cc1Swenshuai.xi #if defined(REDLION_LINUX_KERNEL_ENVI) 125*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MUTEX_PROTECT 0 126*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MIU_RST_PROTECT 1 127*53ee8cc1Swenshuai.xi #define HVD_ENABLE_AUTO_SET_REG_BASE 0 128*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 129*53ee8cc1Swenshuai.xi #define HVD_ENABLE_PATCH_ISFRAMERDY 0 130*53ee8cc1Swenshuai.xi #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 131*53ee8cc1Swenshuai.xi #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 132*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_MIU1_BASE 0 133*53ee8cc1Swenshuai.xi #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 134*53ee8cc1Swenshuai.xi #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 135*53ee8cc1Swenshuai.xi #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 136*53ee8cc1Swenshuai.xi #define HVD_ENABLE_WAIT_CMD_FINISHED 0 137*53ee8cc1Swenshuai.xi #define HVD_ENABLE_TIME_MEASURE 0 138*53ee8cc1Swenshuai.xi #define HVD_ENABLE_REINIT_FAILED 1 139*53ee8cc1Swenshuai.xi #define HVD_ENABLE_RV_FEATURE 0 140*53ee8cc1Swenshuai.xi #else 141*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MUTEX_PROTECT 1 142*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MIU_RST_PROTECT 1 143*53ee8cc1Swenshuai.xi #if 1//defined( MSOS_TYPE_LINUX) 144*53ee8cc1Swenshuai.xi #define HVD_ENABLE_AUTO_SET_REG_BASE 1 145*53ee8cc1Swenshuai.xi #else 146*53ee8cc1Swenshuai.xi #define HVD_ENABLE_AUTO_SET_REG_BASE 0 147*53ee8cc1Swenshuai.xi #endif 148*53ee8cc1Swenshuai.xi #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) 149*53ee8cc1Swenshuai.xi #define HVD_ENABLE_PATCH_ISFRAMERDY 0 150*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 151*53ee8cc1Swenshuai.xi #else 152*53ee8cc1Swenshuai.xi #define HVD_ENABLE_PATCH_ISFRAMERDY 1 153*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 154*53ee8cc1Swenshuai.xi #endif 155*53ee8cc1Swenshuai.xi #if defined(MSOS_TYPE_NOS) && (defined(CHIP_T3) || defined(CHIP_T8) || defined(CHIP_J2)) 156*53ee8cc1Swenshuai.xi #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 157*53ee8cc1Swenshuai.xi #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 158*53ee8cc1Swenshuai.xi #else 159*53ee8cc1Swenshuai.xi #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 160*53ee8cc1Swenshuai.xi #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 161*53ee8cc1Swenshuai.xi #endif 162*53ee8cc1Swenshuai.xi 163*53ee8cc1Swenshuai.xi #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 164*53ee8cc1Swenshuai.xi 165*53ee8cc1Swenshuai.xi #if defined(CHIP_JANUS) 166*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_MIU1_BASE 0 167*53ee8cc1Swenshuai.xi #else 168*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MSOS_MIU1_BASE 1 169*53ee8cc1Swenshuai.xi #endif 170*53ee8cc1Swenshuai.xi 171*53ee8cc1Swenshuai.xi #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 172*53ee8cc1Swenshuai.xi #define HVD_ENABLE_WAIT_CMD_FINISHED 0 173*53ee8cc1Swenshuai.xi #define HVD_ENABLE_TIME_MEASURE 0 174*53ee8cc1Swenshuai.xi #define HVD_ENABLE_REINIT_FAILED 0 175*53ee8cc1Swenshuai.xi 176*53ee8cc1Swenshuai.xi #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) 177*53ee8cc1Swenshuai.xi #define HVD_ENABLE_RV_FEATURE 0 178*53ee8cc1Swenshuai.xi #else 179*53ee8cc1Swenshuai.xi #define HVD_ENABLE_RV_FEATURE 0 180*53ee8cc1Swenshuai.xi #endif 181*53ee8cc1Swenshuai.xi 182*53ee8cc1Swenshuai.xi #if defined(CHIP_T12) || \ 183*53ee8cc1Swenshuai.xi defined(CHIP_J2) || \ 184*53ee8cc1Swenshuai.xi defined(CHIP_A1) || \ 185*53ee8cc1Swenshuai.xi defined(CHIP_A2) || \ 186*53ee8cc1Swenshuai.xi defined(CHIP_A5) || \ 187*53ee8cc1Swenshuai.xi defined(CHIP_A5P) || \ 188*53ee8cc1Swenshuai.xi defined(CHIP_A7) || \ 189*53ee8cc1Swenshuai.xi defined(CHIP_A3) || \ 190*53ee8cc1Swenshuai.xi defined(CHIP_AMETHYST)|| \ 191*53ee8cc1Swenshuai.xi defined(CHIP_AGATE) || \ 192*53ee8cc1Swenshuai.xi defined(CHIP_EDISON) || \ 193*53ee8cc1Swenshuai.xi defined(CHIP_EMERALD)|| \ 194*53ee8cc1Swenshuai.xi defined(CHIP_EAGLE) || \ 195*53ee8cc1Swenshuai.xi defined(CHIP_EIFFEL) || \ 196*53ee8cc1Swenshuai.xi defined(CHIP_NIKE) || \ 197*53ee8cc1Swenshuai.xi defined(CHIP_MADISON) || \ 198*53ee8cc1Swenshuai.xi defined(CHIP_CLIPPERS) || \ 199*53ee8cc1Swenshuai.xi defined(CHIP_MIAMI) || \ 200*53ee8cc1Swenshuai.xi defined(CHIP_NUGGET) || \ 201*53ee8cc1Swenshuai.xi defined(CHIP_KAISER) || \ 202*53ee8cc1Swenshuai.xi defined(CHIP_NIKON) || \ 203*53ee8cc1Swenshuai.xi defined(CHIP_EINSTEIN)|| \ 204*53ee8cc1Swenshuai.xi defined(CHIP_NAPOLI) || \ 205*53ee8cc1Swenshuai.xi defined(CHIP_KERES) || \ 206*53ee8cc1Swenshuai.xi defined(CHIP_MONACO) || \ 207*53ee8cc1Swenshuai.xi defined(CHIP_MUJI) || \ 208*53ee8cc1Swenshuai.xi defined(CHIP_MUNICH) || \ 209*53ee8cc1Swenshuai.xi defined(CHIP_MONET) || \ 210*53ee8cc1Swenshuai.xi defined(CHIP_MANHATTAN) || \ 211*53ee8cc1Swenshuai.xi defined(CHIP_MASERATI) || \ 212*53ee8cc1Swenshuai.xi defined(CHIP_MESSI) || \ 213*53ee8cc1Swenshuai.xi defined(CHIP_MAXIM) || \ 214*53ee8cc1Swenshuai.xi defined(CHIP_K6) || \ 215*53ee8cc1Swenshuai.xi defined(CHIP_K6LITE) 216*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MVC 1 217*53ee8cc1Swenshuai.xi #else 218*53ee8cc1Swenshuai.xi #define HVD_ENABLE_MVC 0 219*53ee8cc1Swenshuai.xi #endif 220*53ee8cc1Swenshuai.xi 221*53ee8cc1Swenshuai.xi #endif 222*53ee8cc1Swenshuai.xi 223*53ee8cc1Swenshuai.xi #define HVD_CMA_SUPPORT_MAX_MIU_NUM 2 224*53ee8cc1Swenshuai.xi #define HVD_CMA_SUPPORTMAX_BLOCK_NUM 2 225*53ee8cc1Swenshuai.xi 226*53ee8cc1Swenshuai.xi #if defined(REDLION_LINUX_KERNEL_ENVI) 227*53ee8cc1Swenshuai.xi #include "drvHVD_redlion.h" 228*53ee8cc1Swenshuai.xi #endif 229*53ee8cc1Swenshuai.xi 230*53ee8cc1Swenshuai.xi #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) 231*53ee8cc1Swenshuai.xi #include "osalHVD_EX.h" 232*53ee8cc1Swenshuai.xi #endif 233*53ee8cc1Swenshuai.xi 234*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MSOS_MIU1_BASE 235*53ee8cc1Swenshuai.xi #include "halCHIP.h" 236*53ee8cc1Swenshuai.xi #endif 237*53ee8cc1Swenshuai.xi 238*53ee8cc1Swenshuai.xi #if HVD_ENABLE_BDMA_2_BITSTREAMBUF 239*53ee8cc1Swenshuai.xi #include "drvBDMA.h" 240*53ee8cc1Swenshuai.xi #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) 241*53ee8cc1Swenshuai.xi #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) 242*53ee8cc1Swenshuai.xi #endif 243*53ee8cc1Swenshuai.xi 244*53ee8cc1Swenshuai.xi 245*53ee8cc1Swenshuai.xi #if defined(MSOS_TYPE_ECOS) 246*53ee8cc1Swenshuai.xi #define HVD_PRINT diag_printf 247*53ee8cc1Swenshuai.xi #define HVD_PRINTI diag_printf 248*53ee8cc1Swenshuai.xi #define HVD_PRINTD diag_printf 249*53ee8cc1Swenshuai.xi #define HVD_ERR diag_printf 250*53ee8cc1Swenshuai.xi #else 251*53ee8cc1Swenshuai.xi #include "ULog.h" 252*53ee8cc1Swenshuai.xi #define HVD_PRINT(format,args...) ULOGD("VDEC", format, ##args) 253*53ee8cc1Swenshuai.xi #define HVD_PRINTI(format,args...) ULOGI("VDEC", format, ##args) 254*53ee8cc1Swenshuai.xi #define HVD_PRINTD(format,args...) ULOGD("VDEC", format, ##args) 255*53ee8cc1Swenshuai.xi #define HVD_ERR(format,args...) ULOGE("VDEC", format, ##args) 256*53ee8cc1Swenshuai.xi #endif 257*53ee8cc1Swenshuai.xi 258*53ee8cc1Swenshuai.xi 259*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_MUST(format, args...) \ 260*53ee8cc1Swenshuai.xi do \ 261*53ee8cc1Swenshuai.xi { \ 262*53ee8cc1Swenshuai.xi if (u32UartCtrl & E_HVD_UART_CTRL_MUST) \ 263*53ee8cc1Swenshuai.xi { \ 264*53ee8cc1Swenshuai.xi HVD_ERR("[HVD][MUST]%s:", __FUNCTION__); \ 265*53ee8cc1Swenshuai.xi HVD_ERR(format, ##args); \ 266*53ee8cc1Swenshuai.xi } \ 267*53ee8cc1Swenshuai.xi } while (0) 268*53ee8cc1Swenshuai.xi 269*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_ERR(format, args...) \ 270*53ee8cc1Swenshuai.xi do \ 271*53ee8cc1Swenshuai.xi { \ 272*53ee8cc1Swenshuai.xi if (u32UartCtrl & E_HVD_UART_CTRL_ERR) \ 273*53ee8cc1Swenshuai.xi { \ 274*53ee8cc1Swenshuai.xi HVD_ERR("[HVD][ERR]%s:", __FUNCTION__); \ 275*53ee8cc1Swenshuai.xi HVD_ERR(format, ##args); \ 276*53ee8cc1Swenshuai.xi } \ 277*53ee8cc1Swenshuai.xi } while (0) 278*53ee8cc1Swenshuai.xi 279*53ee8cc1Swenshuai.xi #if ((defined(CHIP_A1) || defined(CHIP_A7) || defined(CHIP_AMETHYST) || defined(CHIP_EMERALD) || defined(CHIP_NUGGET) || defined(CHIP_NIKON)) && defined (__aeon__)) 280*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_INF(format, args...) 281*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_DBG(format, args...) 282*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_TRACE() 283*53ee8cc1Swenshuai.xi #else 284*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_INF(format, args...) \ 285*53ee8cc1Swenshuai.xi do \ 286*53ee8cc1Swenshuai.xi { \ 287*53ee8cc1Swenshuai.xi if (u32UartCtrl & E_HVD_UART_CTRL_INFO) \ 288*53ee8cc1Swenshuai.xi { \ 289*53ee8cc1Swenshuai.xi HVD_PRINTI("[HVD][INF]%s:", __FUNCTION__); \ 290*53ee8cc1Swenshuai.xi HVD_PRINTI(format, ##args); \ 291*53ee8cc1Swenshuai.xi } \ 292*53ee8cc1Swenshuai.xi } while (0) 293*53ee8cc1Swenshuai.xi 294*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_DBG(format, args...) \ 295*53ee8cc1Swenshuai.xi do \ 296*53ee8cc1Swenshuai.xi { \ 297*53ee8cc1Swenshuai.xi if (u32UartCtrl & E_HVD_UART_CTRL_DBG) \ 298*53ee8cc1Swenshuai.xi { \ 299*53ee8cc1Swenshuai.xi HVD_PRINTD("[HVD][DBG]%s:", __FUNCTION__); \ 300*53ee8cc1Swenshuai.xi HVD_PRINTD(format, ##args); \ 301*53ee8cc1Swenshuai.xi } \ 302*53ee8cc1Swenshuai.xi } while (0) 303*53ee8cc1Swenshuai.xi 304*53ee8cc1Swenshuai.xi #define HVD_EX_MSG_TRACE() \ 305*53ee8cc1Swenshuai.xi do \ 306*53ee8cc1Swenshuai.xi { \ 307*53ee8cc1Swenshuai.xi if (u32UartCtrl & E_HVD_UART_CTRL_TRACE) \ 308*53ee8cc1Swenshuai.xi { \ 309*53ee8cc1Swenshuai.xi HVD_PRINTD("[HVD][TRA]%s:", __FUNCTION__); \ 310*53ee8cc1Swenshuai.xi } \ 311*53ee8cc1Swenshuai.xi } while (0) 312*53ee8cc1Swenshuai.xi #endif 313*53ee8cc1Swenshuai.xi 314*53ee8cc1Swenshuai.xi // Configs 315*53ee8cc1Swenshuai.xi #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks 316*53ee8cc1Swenshuai.xi #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 317*53ee8cc1Swenshuai.xi 318*53ee8cc1Swenshuai.xi #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 319*53ee8cc1Swenshuai.xi #define HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT 1000 320*53ee8cc1Swenshuai.xi 321*53ee8cc1Swenshuai.xi // Util or Functions 322*53ee8cc1Swenshuai.xi #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) 323*53ee8cc1Swenshuai.xi #define HVD_LWORD(x) (MS_U16)((x)&0xffff) 324*53ee8cc1Swenshuai.xi #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) 325*53ee8cc1Swenshuai.xi #define HVD_U32_MAX 0xffffffffUL 326*53ee8cc1Swenshuai.xi #define HVD_RV_BROKENBYUS_MASK 0x00800000 327*53ee8cc1Swenshuai.xi 328*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX 329*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MSOS_SYSTEM_CALL 330*53ee8cc1Swenshuai.xi #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 331*53ee8cc1Swenshuai.xi #else 332*53ee8cc1Swenshuai.xi #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 333*53ee8cc1Swenshuai.xi #endif 334*53ee8cc1Swenshuai.xi #else 335*53ee8cc1Swenshuai.xi #define HVD_VA2PA(x) (x) 336*53ee8cc1Swenshuai.xi #endif 337*53ee8cc1Swenshuai.xi 338*53ee8cc1Swenshuai.xi #if defined(REDLION_LINUX_KERNEL_ENVI) 339*53ee8cc1Swenshuai.xi #define HVD_PA2VA(x ) (MS_VIRT)MDrv_SYS_PA2NonCacheSeg((void*)(x)) 340*53ee8cc1Swenshuai.xi #else 341*53ee8cc1Swenshuai.xi #define HVD_PA2VA(x ) (MS_VIRT)MS_PA2KSEG1((MS_PHY)(x)) 342*53ee8cc1Swenshuai.xi #endif 343*53ee8cc1Swenshuai.xi 344*53ee8cc1Swenshuai.xi #if 0//def memcpy 345*53ee8cc1Swenshuai.xi #define HVD_memcpy(x , y , z) memcpy(x, y, z) 346*53ee8cc1Swenshuai.xi #else 347*53ee8cc1Swenshuai.xi 348*53ee8cc1Swenshuai.xi #if 0 349*53ee8cc1Swenshuai.xi #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 350*53ee8cc1Swenshuai.xi do { \ 351*53ee8cc1Swenshuai.xi MS_U32 i = 0; \ 352*53ee8cc1Swenshuai.xi volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ 353*53ee8cc1Swenshuai.xi volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ 354*53ee8cc1Swenshuai.xi for (i = 0; i < (u32Size); i++) \ 355*53ee8cc1Swenshuai.xi { \ 356*53ee8cc1Swenshuai.xi Dest[i] = Src[i]; \ 357*53ee8cc1Swenshuai.xi } \ 358*53ee8cc1Swenshuai.xi }while(0) 359*53ee8cc1Swenshuai.xi #else 360*53ee8cc1Swenshuai.xi #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 361*53ee8cc1Swenshuai.xi do { \ 362*53ee8cc1Swenshuai.xi register unsigned long u32I=0; \ 363*53ee8cc1Swenshuai.xi register unsigned long u32Dst = (unsigned long)pDstAddr; \ 364*53ee8cc1Swenshuai.xi void * pSrc = (void *)pSrcAddr; \ 365*53ee8cc1Swenshuai.xi MS_U32 _u32memsize = u32Size; \ 366*53ee8cc1Swenshuai.xi if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ 367*53ee8cc1Swenshuai.xi { \ 368*53ee8cc1Swenshuai.xi for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ 369*53ee8cc1Swenshuai.xi { \ 370*53ee8cc1Swenshuai.xi ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 371*53ee8cc1Swenshuai.xi } \ 372*53ee8cc1Swenshuai.xi } \ 373*53ee8cc1Swenshuai.xi else \ 374*53ee8cc1Swenshuai.xi { \ 375*53ee8cc1Swenshuai.xi for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ 376*53ee8cc1Swenshuai.xi { \ 377*53ee8cc1Swenshuai.xi ((volatile unsigned int *)u32Dst)[u32I] = ((volatile unsigned int *)pSrc)[u32I]; \ 378*53ee8cc1Swenshuai.xi } \ 379*53ee8cc1Swenshuai.xi if((_u32memsize)%4) \ 380*53ee8cc1Swenshuai.xi { \ 381*53ee8cc1Swenshuai.xi u32Dst += u32I*4; \ 382*53ee8cc1Swenshuai.xi pSrc = (void *)((unsigned long)pSrc + u32I*4); \ 383*53ee8cc1Swenshuai.xi for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ 384*53ee8cc1Swenshuai.xi { \ 385*53ee8cc1Swenshuai.xi ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 386*53ee8cc1Swenshuai.xi } \ 387*53ee8cc1Swenshuai.xi } \ 388*53ee8cc1Swenshuai.xi } \ 389*53ee8cc1Swenshuai.xi }while(0) 390*53ee8cc1Swenshuai.xi #endif 391*53ee8cc1Swenshuai.xi 392*53ee8cc1Swenshuai.xi #endif 393*53ee8cc1Swenshuai.xi 394*53ee8cc1Swenshuai.xi 395*53ee8cc1Swenshuai.xi 396*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MSOS_SYSTEM_CALL 397*53ee8cc1Swenshuai.xi #define HVD_Delay_ms(x) MsOS_DelayTaskUs(1000*x) 398*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_DELAY_MS_TYPE 2 399*53ee8cc1Swenshuai.xi #elif defined(REDLION_LINUX_KERNEL_ENVI) 400*53ee8cc1Swenshuai.xi #define HVD_Delay_ms(x) msleep(x) 401*53ee8cc1Swenshuai.xi //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) 402*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_DELAY_MS_TYPE 3 403*53ee8cc1Swenshuai.xi #else 404*53ee8cc1Swenshuai.xi #define HVD_Delay_ms(x) \ 405*53ee8cc1Swenshuai.xi do { \ 406*53ee8cc1Swenshuai.xi volatile MS_U32 ticks=0; \ 407*53ee8cc1Swenshuai.xi while( ticks < ( ((MS_U32)(x)) <<13) ) \ 408*53ee8cc1Swenshuai.xi { \ 409*53ee8cc1Swenshuai.xi ticks++; \ 410*53ee8cc1Swenshuai.xi } \ 411*53ee8cc1Swenshuai.xi } while(0) 412*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_DELAY_MS_TYPE 0 413*53ee8cc1Swenshuai.xi #endif // HVD_ENABLE_MSOS_SYSTEM_CALL 414*53ee8cc1Swenshuai.xi 415*53ee8cc1Swenshuai.xi 416*53ee8cc1Swenshuai.xi #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ 417*53ee8cc1Swenshuai.xi do{ \ 418*53ee8cc1Swenshuai.xi MS_U32 i = 0; \ 419*53ee8cc1Swenshuai.xi MS_U32 j = 0; \ 420*53ee8cc1Swenshuai.xi MS_U8* temp = (MS_U8*)addr; \ 421*53ee8cc1Swenshuai.xi MS_U8 string[17] ; \ 422*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ 423*53ee8cc1Swenshuai.xi temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ 424*53ee8cc1Swenshuai.xi memset(string , 0 , sizeof(string)); \ 425*53ee8cc1Swenshuai.xi for (j = 0; j < (size >> 4); j++) \ 426*53ee8cc1Swenshuai.xi { \ 427*53ee8cc1Swenshuai.xi if (ascii) \ 428*53ee8cc1Swenshuai.xi { \ 429*53ee8cc1Swenshuai.xi for (i = 0; i < 16; i++) \ 430*53ee8cc1Swenshuai.xi { \ 431*53ee8cc1Swenshuai.xi if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 432*53ee8cc1Swenshuai.xi string[i] = *(temp + i); \ 433*53ee8cc1Swenshuai.xi else \ 434*53ee8cc1Swenshuai.xi string[i] = '.'; \ 435*53ee8cc1Swenshuai.xi } \ 436*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ 437*53ee8cc1Swenshuai.xi , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ 438*53ee8cc1Swenshuai.xi } \ 439*53ee8cc1Swenshuai.xi else \ 440*53ee8cc1Swenshuai.xi { \ 441*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ 442*53ee8cc1Swenshuai.xi , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ 443*53ee8cc1Swenshuai.xi } \ 444*53ee8cc1Swenshuai.xi temp += 16; \ 445*53ee8cc1Swenshuai.xi } \ 446*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("0x%08x " , j << 4); \ 447*53ee8cc1Swenshuai.xi memset(string , 0 , sizeof(string)); \ 448*53ee8cc1Swenshuai.xi for (i = 0; i < (size & 0x0f); i++) \ 449*53ee8cc1Swenshuai.xi { \ 450*53ee8cc1Swenshuai.xi if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 451*53ee8cc1Swenshuai.xi string[i] = *(temp + i); \ 452*53ee8cc1Swenshuai.xi else \ 453*53ee8cc1Swenshuai.xi string[i] = '.'; \ 454*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("%02x ", *(MS_U8*)(temp + i)); \ 455*53ee8cc1Swenshuai.xi } \ 456*53ee8cc1Swenshuai.xi if (ascii) \ 457*53ee8cc1Swenshuai.xi { \ 458*53ee8cc1Swenshuai.xi for (; i < 16 ; i++) \ 459*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG(" "); \ 460*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG(" %s\n" , string); \ 461*53ee8cc1Swenshuai.xi } \ 462*53ee8cc1Swenshuai.xi else \ 463*53ee8cc1Swenshuai.xi HVD_EX_MSG_DBG("\n"); \ 464*53ee8cc1Swenshuai.xi }while(0) 465*53ee8cc1Swenshuai.xi 466*53ee8cc1Swenshuai.xi 467*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MSOS_SYSTEM_CALL 468*53ee8cc1Swenshuai.xi #define HVD_GetSysTime_ms() MsOS_GetSystemTime() 469*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_CLOCK_TYPE 1 470*53ee8cc1Swenshuai.xi #elif defined(REDLION_LINUX_KERNEL_ENVI) 471*53ee8cc1Swenshuai.xi #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() 472*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_CLOCK_TYPE 2 473*53ee8cc1Swenshuai.xi #else 474*53ee8cc1Swenshuai.xi #define HVD_GetSysTime_ms() 1 475*53ee8cc1Swenshuai.xi #define HVD_SYSTEM_CLOCK_TYPE 0 476*53ee8cc1Swenshuai.xi #endif // MsOS_GetSystemTime 477*53ee8cc1Swenshuai.xi 478*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MSOS_SYSTEM_CALL 479*53ee8cc1Swenshuai.xi #include "asmCPU.h" 480*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() 481*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 3 482*53ee8cc1Swenshuai.xi #else 483*53ee8cc1Swenshuai.xi #if defined (__mips__) 484*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") 485*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 1 486*53ee8cc1Swenshuai.xi #elif defined (__aeon__) 487*53ee8cc1Swenshuai.xi #ifdef __AEONR2__ 488*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") 489*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 22 490*53ee8cc1Swenshuai.xi #else 491*53ee8cc1Swenshuai.xi #if defined( CHIP_T2 ) 492*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") 493*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 21 494*53ee8cc1Swenshuai.xi #else 495*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") 496*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 23 497*53ee8cc1Swenshuai.xi #endif 498*53ee8cc1Swenshuai.xi #endif 499*53ee8cc1Swenshuai.xi #else 500*53ee8cc1Swenshuai.xi #define HAL_MEMORY_BARRIER() 501*53ee8cc1Swenshuai.xi #define HVD_MEMORY_BARRIER_TYPE 0 502*53ee8cc1Swenshuai.xi #endif 503*53ee8cc1Swenshuai.xi #endif 504*53ee8cc1Swenshuai.xi 505*53ee8cc1Swenshuai.xi #define HVD_DRV_MODE_EXTERNAL_DS_BUFFER (1 << 0) 506*53ee8cc1Swenshuai.xi 507*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 508*53ee8cc1Swenshuai.xi // Type and Structure 509*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 510*53ee8cc1Swenshuai.xi typedef void (*HVD_ISRCallBack)(MS_U32 u32Sid); 511*53ee8cc1Swenshuai.xi 512*53ee8cc1Swenshuai.xi typedef enum 513*53ee8cc1Swenshuai.xi { 514*53ee8cc1Swenshuai.xi E_HVD_RETURN_FAIL=0, 515*53ee8cc1Swenshuai.xi E_HVD_RETURN_SUCCESS, 516*53ee8cc1Swenshuai.xi E_HVD_RETURN_INVALID_PARAMETER, 517*53ee8cc1Swenshuai.xi E_HVD_RETURN_ILLEGAL_ACCESS, 518*53ee8cc1Swenshuai.xi E_HVD_RETURN_HARDWARE_BREAKDOWN, 519*53ee8cc1Swenshuai.xi E_HVD_RETURN_OUTOF_MEMORY, 520*53ee8cc1Swenshuai.xi E_HVD_RETURN_UNSUPPORTED, 521*53ee8cc1Swenshuai.xi E_HVD_RETURN_TIMEOUT, 522*53ee8cc1Swenshuai.xi E_HVD_RETURN_NOTREADY, 523*53ee8cc1Swenshuai.xi E_HVD_RETURN_MEMORY_OVERWIRTE, 524*53ee8cc1Swenshuai.xi E_HVD_RETURN_ES_FULL, 525*53ee8cc1Swenshuai.xi E_HVD_RETURN_RE_INIT, 526*53ee8cc1Swenshuai.xi E_HVD_RETURN_NOT_RUNNING, 527*53ee8cc1Swenshuai.xi } HVD_Return; 528*53ee8cc1Swenshuai.xi 529*53ee8cc1Swenshuai.xi typedef enum 530*53ee8cc1Swenshuai.xi { 531*53ee8cc1Swenshuai.xi // share memory 532*53ee8cc1Swenshuai.xi E_HVD_GDATA_SHARE_MEM=0x1000, 533*53ee8cc1Swenshuai.xi // switch 534*53ee8cc1Swenshuai.xi //E_HVD_GDATA_SEMAPHORE, 535*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), 536*53ee8cc1Swenshuai.xi E_HVD_GDATA_MIU_SEL, 537*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRAMEBUF_ADDR, 538*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRAMEBUF_SIZE, 539*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRAMEBUF2_ADDR, 540*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRAMEBUF2_SIZE, 541*53ee8cc1Swenshuai.xi E_HVD_GDATA_CMA_USED, 542*53ee8cc1Swenshuai.xi E_HVD_GDATA_CMA_ALLOC_DONE, 543*53ee8cc1Swenshuai.xi E_HVD_GDATA_DYNMC_DISP_PATH_STATUS, 544*53ee8cc1Swenshuai.xi // report 545*53ee8cc1Swenshuai.xi E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), 546*53ee8cc1Swenshuai.xi E_HVD_GDATA_U64PTS, 547*53ee8cc1Swenshuai.xi E_HVD_GDATA_DECODE_CNT, 548*53ee8cc1Swenshuai.xi E_HVD_GDATA_DATA_ERROR_CNT, 549*53ee8cc1Swenshuai.xi E_HVD_GDATA_DEC_ERROR_CNT, 550*53ee8cc1Swenshuai.xi E_HVD_GDATA_ERROR_CODE, 551*53ee8cc1Swenshuai.xi E_HVD_GDATA_VPU_IDLE_CNT, 552*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_FRM_INFO, 553*53ee8cc1Swenshuai.xi E_HVD_GDATA_DEC_FRM_INFO, 554*53ee8cc1Swenshuai.xi E_HVD_GDATA_ES_LEVEL, 555*53ee8cc1Swenshuai.xi E_HVD_GDATA_PTS_STC_DIFF, 556*53ee8cc1Swenshuai.xi #if HVD_ENABLE_MVC 557*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_FRM_INFO_SUB, 558*53ee8cc1Swenshuai.xi E_HVD_GDATA_DEC_FRM_INFO_SUB, 559*53ee8cc1Swenshuai.xi #endif 560*53ee8cc1Swenshuai.xi E_HVD_GDATA_HVD_HW_MAX_PIXEL, 561*53ee8cc1Swenshuai.xi E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS, 562*53ee8cc1Swenshuai.xi E_HVD_GDATA_TS_SEAMLESS_TARGET_POC, 563*53ee8cc1Swenshuai.xi 564*53ee8cc1Swenshuai.xi // user data 565*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_WPTR, 566*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, 567*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, 568*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_PACKET_SIZE, 569*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, 570*53ee8cc1Swenshuai.xi E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, 571*53ee8cc1Swenshuai.xi // report - modes 572*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_SHOW_ERR_FRM, 573*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_REPEAT_LAST_FIELD, 574*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_ERR_CONCEAL, 575*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_SYNC_ON, 576*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_PLAYBACK_FINISH, 577*53ee8cc1Swenshuai.xi E_HVD_GDATA_SYNC_MODE, 578*53ee8cc1Swenshuai.xi E_HVD_GDATA_SKIP_MODE, 579*53ee8cc1Swenshuai.xi E_HVD_GDATA_DROP_MODE, 580*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISPLAY_DURATION, 581*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRC_MODE, 582*53ee8cc1Swenshuai.xi E_HVD_GDATA_NEXT_PTS, 583*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_Q_SIZE, 584*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_Q_PTR, 585*53ee8cc1Swenshuai.xi E_HVD_GDATA_NEXT_DISP_FRM_INFO, 586*53ee8cc1Swenshuai.xi E_HVD_GDATA_REAL_FRAMERATE, 587*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_ORI_INTERLACE_MODE, 588*53ee8cc1Swenshuai.xi E_HVD_GDATA_FRM_PACKING_SEI_DATA, 589*53ee8cc1Swenshuai.xi E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, 590*53ee8cc1Swenshuai.xi E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE, 591*53ee8cc1Swenshuai.xi E_HVD_GDATA_FIELD_PIC_FLAG, 592*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_STATUS_FLAG, 593*53ee8cc1Swenshuai.xi E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT, 594*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA, 595*53ee8cc1Swenshuai.xi E_HVD_GDATA_U64PTS_PRE_PARSE, 596*53ee8cc1Swenshuai.xi E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO, 597*53ee8cc1Swenshuai.xi E_HVD_GDATA_SEQ_CHANGE_INFO, 598*53ee8cc1Swenshuai.xi 599*53ee8cc1Swenshuai.xi // internal control 600*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), 601*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_I_FRM_FOUND, 602*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_SYNC_START, 603*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_SYNC_REACH, 604*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_VERSION_ID, 605*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_IF_VERSION_ID, 606*53ee8cc1Swenshuai.xi E_HVD_GDATA_BBU_Q_NUMB, 607*53ee8cc1Swenshuai.xi E_HVD_GDATA_DEC_Q_NUMB, 608*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_Q_NUMB, 609*53ee8cc1Swenshuai.xi E_HVD_GDATA_PTS_Q_NUMB, 610*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_INIT_DONE, 611*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_IS_IQMEM_SUPPORT, 612*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_IQMEM_CTRL, 613*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_FLUSH_STATUS, 614*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_CODEC_TYPE, 615*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_ES_BUF_STATUS, 616*53ee8cc1Swenshuai.xi E_HVD_GDATA_TS_SEAMLESS_STATUS, 617*53ee8cc1Swenshuai.xi E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG, 618*53ee8cc1Swenshuai.xi E_HVD_GDATA_GET_NOT_SUPPORT_INFO, 619*53ee8cc1Swenshuai.xi E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE, 620*53ee8cc1Swenshuai.xi 621*53ee8cc1Swenshuai.xi // debug 622*53ee8cc1Swenshuai.xi E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), 623*53ee8cc1Swenshuai.xi E_HVD_GDATA_GOP_CNT, 624*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_CNT, 625*53ee8cc1Swenshuai.xi E_HVD_GDATA_DROP_CNT, 626*53ee8cc1Swenshuai.xi E_HVD_GDATA_DISP_STC, 627*53ee8cc1Swenshuai.xi E_HVD_GDATA_VSYNC_CNT, 628*53ee8cc1Swenshuai.xi E_HVD_GDATA_MAIN_LOOP_CNT, 629*53ee8cc1Swenshuai.xi // AVC 630*53ee8cc1Swenshuai.xi E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), 631*53ee8cc1Swenshuai.xi E_HVD_GDATA_AVC_LOW_DELAY, 632*53ee8cc1Swenshuai.xi E_HVD_GDATA_AVC_VUI_DISP_INFO, 633*53ee8cc1Swenshuai.xi //E_HVD_GDATA_AVC_SPS_ADDR, 634*53ee8cc1Swenshuai.xi 635*53ee8cc1Swenshuai.xi // SRAM 636*53ee8cc1Swenshuai.xi E_HVD_GDATA_SRAM=0x2000, 637*53ee8cc1Swenshuai.xi //E_HVD_GDATA_AVC_NAL_CNT, 638*53ee8cc1Swenshuai.xi 639*53ee8cc1Swenshuai.xi // Mailbox or Reg 640*53ee8cc1Swenshuai.xi E_HVD_GDATA_MBOX=0x3000, 641*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) 642*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) 643*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) 644*53ee8cc1Swenshuai.xi E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) 645*53ee8cc1Swenshuai.xi E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) 646*53ee8cc1Swenshuai.xi E_HVD_GDATA_ES_READ_PTR, // 647*53ee8cc1Swenshuai.xi E_HVD_GDATA_ES_WRITE_PTR, // 648*53ee8cc1Swenshuai.xi E_HVD_GDATA_BBU_READ_PTR, // 649*53ee8cc1Swenshuai.xi E_HVD_GDATA_BBU_WRITE_PTR, // 650*53ee8cc1Swenshuai.xi E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // 651*53ee8cc1Swenshuai.xi E_HVD_GDATA_VPU_PC_CNT, // 652*53ee8cc1Swenshuai.xi E_HVD_GDATA_ES_QUANTITY, 653*53ee8cc1Swenshuai.xi 654*53ee8cc1Swenshuai.xi // FW def 655*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DEF=0x4000, 656*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? 657*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, 658*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, 659*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, 660*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, 661*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, 662*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DS_BUF_ADDR, 663*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DS_BUF_SIZE, 664*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DS_VECTOR_DEPTH, 665*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DS_INFO_ADDR, 666*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_DS_IS_ENABLED, 667*53ee8cc1Swenshuai.xi #ifdef VDEC3 668*53ee8cc1Swenshuai.xi E_HVD_GDATA_FW_VBBU_ADDR, 669*53ee8cc1Swenshuai.xi #endif 670*53ee8cc1Swenshuai.xi // BBU size 671*53ee8cc1Swenshuai.xi // default pitch number 672*53ee8cc1Swenshuai.xi // 673*53ee8cc1Swenshuai.xi } HVD_GetData; 674*53ee8cc1Swenshuai.xi 675*53ee8cc1Swenshuai.xi typedef enum 676*53ee8cc1Swenshuai.xi { 677*53ee8cc1Swenshuai.xi // share memory 678*53ee8cc1Swenshuai.xi E_HVD_SDATA_SHARE_MEM = 0x1000, 679*53ee8cc1Swenshuai.xi // switch 680*53ee8cc1Swenshuai.xi E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100 + E_HVD_SDATA_SHARE_MEM), 681*53ee8cc1Swenshuai.xi E_HVD_SDATA_FRAMEBUF_SIZE, 682*53ee8cc1Swenshuai.xi E_HVD_SDATA_ERROR_CODE, 683*53ee8cc1Swenshuai.xi E_HVD_SDATA_DISP_INFO_TH, 684*53ee8cc1Swenshuai.xi E_HVD_SDATA_FW_FLUSH_STATUS, 685*53ee8cc1Swenshuai.xi E_HVD_SDATA_DMX_FRAMERATE, 686*53ee8cc1Swenshuai.xi E_HVD_SDATA_DMX_FRAMERATEBASE, 687*53ee8cc1Swenshuai.xi E_HVD_SDATA_MIU_SEL, 688*53ee8cc1Swenshuai.xi E_HVD_SDATA_FRAMEBUF2_ADDR, 689*53ee8cc1Swenshuai.xi E_HVD_SDATA_FRAMEBUF2_SIZE, 690*53ee8cc1Swenshuai.xi E_HVD_SDATA_CMA_USED, 691*53ee8cc1Swenshuai.xi E_HVD_SDATA_CMA_ALLOC_DONE, 692*53ee8cc1Swenshuai.xi E_HVD_SDATA_CMA_TWO_MIU, 693*53ee8cc1Swenshuai.xi E_HVD_SDATA_MAX_CMA_SIZE, 694*53ee8cc1Swenshuai.xi E_HVD_SDATA_MAX_CMA_SIZE2, 695*53ee8cc1Swenshuai.xi E_HVD_SDATA_DV_XC_SHM_SIZE, 696*53ee8cc1Swenshuai.xi E_HVD_SDATA_DYNMC_DISP_PATH_STATUS, 697*53ee8cc1Swenshuai.xi // display info 698*53ee8cc1Swenshuai.xi //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), 699*53ee8cc1Swenshuai.xi // report 700*53ee8cc1Swenshuai.xi //E_HVD_SDATA_PTS=0x0200, 701*53ee8cc1Swenshuai.xi // internal control 702*53ee8cc1Swenshuai.xi //E_HVD_SDATA_IDLE_CNT=0x0300, 703*53ee8cc1Swenshuai.xi // debug 704*53ee8cc1Swenshuai.xi //E_HVD_SDATA_SKIP_CNT=0x0400, 705*53ee8cc1Swenshuai.xi // RM 706*53ee8cc1Swenshuai.xi E_HVD_SDATA_RM_PICTURE_SIZES = (0x0500 | E_HVD_SDATA_SHARE_MEM), 707*53ee8cc1Swenshuai.xi 708*53ee8cc1Swenshuai.xi // SRAM 709*53ee8cc1Swenshuai.xi // Mailbox or Reg 710*53ee8cc1Swenshuai.xi E_HVD_SDATA_MAILBOX = 0x3000, 711*53ee8cc1Swenshuai.xi E_HVD_SDATA_FW_CODE_TYPE = (0x0000 | E_HVD_SDATA_MAILBOX), 712*53ee8cc1Swenshuai.xi E_HVD_SDATA_TRIGGER_DISP, 713*53ee8cc1Swenshuai.xi E_HVD_SDATA_GET_DISP_INFO_DONE, 714*53ee8cc1Swenshuai.xi E_HVD_SDATA_GET_DISP_INFO_START, 715*53ee8cc1Swenshuai.xi 716*53ee8cc1Swenshuai.xi // FW def 717*53ee8cc1Swenshuai.xi E_HVD_SDATA_FW_DEF = 0x4000, 718*53ee8cc1Swenshuai.xi E_HVD_SDATA_VIRTUAL_BOX_WIDTH, 719*53ee8cc1Swenshuai.xi E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, 720*53ee8cc1Swenshuai.xi //modify the state of the frame in DispQueue 721*53ee8cc1Swenshuai.xi E_HVD_SDATA_DISPQ_STATUS_VIEW, 722*53ee8cc1Swenshuai.xi E_HVD_SDATA_DISPQ_STATUS_DISP, 723*53ee8cc1Swenshuai.xi E_HVD_SDATA_DISPQ_STATUS_FREE, 724*53ee8cc1Swenshuai.xi E_HVD_SDATA_FW_IQMEM_CTRL, 725*53ee8cc1Swenshuai.xi E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, 726*53ee8cc1Swenshuai.xi E_HVD_SDATA_DV_INFO, 727*53ee8cc1Swenshuai.xi E_HVD_SDATA_HDR_PERFRAME, 728*53ee8cc1Swenshuai.xi E_HVD_SDATA_VP9HDR10INFO, 729*53ee8cc1Swenshuai.xi } HVD_SetData; 730*53ee8cc1Swenshuai.xi 731*53ee8cc1Swenshuai.xi typedef enum 732*53ee8cc1Swenshuai.xi { 733*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_DISABLE = BIT(4), 734*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_ERR = BIT(0), 735*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_INFO = BIT(1), 736*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_DBG = BIT(2), 737*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_FW = BIT(3), 738*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_MUST = BIT(4), 739*53ee8cc1Swenshuai.xi E_HVD_UART_CTRL_TRACE = BIT(5), 740*53ee8cc1Swenshuai.xi } HVD_Uart_Ctrl; 741*53ee8cc1Swenshuai.xi 742*53ee8cc1Swenshuai.xi typedef enum 743*53ee8cc1Swenshuai.xi { 744*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_MASK = BMASK(3:0), ///< HW Type, should same as HVD_Codec_Type in fwHVD_if.h 745*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_AVC = BITS(3:0, 0), ///< HW deflaut: AVC 0X00 746*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_AVS = BITS(3:0, 1), ///< HW: AVS 0X01 747*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_RM = BITS(3:0, 2), ///< HW: RM 0X10 748*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_MVC = BITS(3:0, 3), ///< HW: MVC 0x11 749*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_VP8 = BITS(3:0, 4), ///< HW: VP8 0X100 750*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_MJPEG = BITS(3:0, 5), ///< HW: MJPEG 0x101 751*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_VP6 = BITS(3:0, 6), ///< HW: VP6 0x110 752*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_HEVC = BITS(3:0, 7), ///< HW: HEVC 0x111 753*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_VP9 = BITS(3:0, 8), ///< HW: VP9 0x1000 754*53ee8cc1Swenshuai.xi E_HVD_INIT_HW_HEVC_DV = BITS(3:0, 9), ///< HW: HEVC_DV 0x1001 755*53ee8cc1Swenshuai.xi E_HVD_INIT_MAIN_MASK = BMASK(5:4), ///< main type 756*53ee8cc1Swenshuai.xi E_HVD_INIT_MAIN_FILE_RAW = BITS(5:4, 0), ///< main type: default: 0X00 757*53ee8cc1Swenshuai.xi E_HVD_INIT_MAIN_FILE_TS = BITS(5:4, 1), ///< main type: 0X01 758*53ee8cc1Swenshuai.xi E_HVD_INIT_MAIN_LIVE_STREAM = BITS(5:4, 2), ///< main type: 0X10 759*53ee8cc1Swenshuai.xi E_HVD_INIT_INPUT_MASK = BMASK(6:6), ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode 760*53ee8cc1Swenshuai.xi E_HVD_INIT_INPUT_TSP = BITS(6:6, 0), ///< tsp input( default) 761*53ee8cc1Swenshuai.xi E_HVD_INIT_INPUT_DRV = BITS(6:6, 1), ///< driver input 762*53ee8cc1Swenshuai.xi E_HVD_INIT_START_CODE_MASK = BMASK(7:7), ///< AVC FILE MODE ONLY: mkv, mp4 container use. 763*53ee8cc1Swenshuai.xi E_HVD_INIT_START_CODE_REMAINED = BITS(7:7, 0), ///< start code remained.(Defualt) 764*53ee8cc1Swenshuai.xi E_HVD_INIT_START_CODE_REMOVED = BITS(7:7, 1), ///< start code removed. 765*53ee8cc1Swenshuai.xi E_HVD_INIT_UTOPIA_ENVI = BIT(8), ///< check MIU sel and set it 766*53ee8cc1Swenshuai.xi E_HVD_INIT_DBG_FW = BIT(9), ///< check FW is debug version or not 767*53ee8cc1Swenshuai.xi E_HVD_INIT_DUAL_ES_MASK = BMASK(10:10), ///< Dual ES buffer iput. 768*53ee8cc1Swenshuai.xi E_HVD_INIT_DUAL_ES_DISABLE = BITS(10:10, 0), ///< Disable Dual ES buffer input. 769*53ee8cc1Swenshuai.xi E_HVD_INIT_DUAL_ES_ENABLE = BITS(10:10, 1), ///< Enable Dual ES buffer input. 770*53ee8cc1Swenshuai.xi //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. 771*53ee8cc1Swenshuai.xi } HVD_Init_Mode_Flag; 772*53ee8cc1Swenshuai.xi 773*53ee8cc1Swenshuai.xi typedef enum 774*53ee8cc1Swenshuai.xi { 775*53ee8cc1Swenshuai.xi E_HVD_PLAY_NORMAL, 776*53ee8cc1Swenshuai.xi E_HVD_PLAY_PAUSE, 777*53ee8cc1Swenshuai.xi E_HVD_PLAY_STEP_DISPLAY, 778*53ee8cc1Swenshuai.xi } HVD_Play_Type; 779*53ee8cc1Swenshuai.xi 780*53ee8cc1Swenshuai.xi typedef enum 781*53ee8cc1Swenshuai.xi { 782*53ee8cc1Swenshuai.xi E_HVD_ESB_LEVEL_NORMAL = 0, 783*53ee8cc1Swenshuai.xi E_HVD_ESB_LEVEL_UNDER = BIT(0), 784*53ee8cc1Swenshuai.xi E_HVD_ESB_LEVEL_OVER = BIT(1), 785*53ee8cc1Swenshuai.xi } HVD_ESBuf_Level; 786*53ee8cc1Swenshuai.xi 787*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 788*53ee8cc1Swenshuai.xi /// @brief \b Enum \b Name: HVD_FWInputSourceType 789*53ee8cc1Swenshuai.xi /// @brief \b Enum \b Description: The type of fw binary input source 790*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 791*53ee8cc1Swenshuai.xi typedef enum 792*53ee8cc1Swenshuai.xi { 793*53ee8cc1Swenshuai.xi E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. 794*53ee8cc1Swenshuai.xi E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. 795*53ee8cc1Swenshuai.xi E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. 796*53ee8cc1Swenshuai.xi } HVD_FWInputSourceType; 797*53ee8cc1Swenshuai.xi 798*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 799*53ee8cc1Swenshuai.xi /// @brief \b Enum \b Name: HVD_FB_Reduction_Type 800*53ee8cc1Swenshuai.xi /// @brief \b Enum \b Description: The type of frame buffer reduction type 801*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 802*53ee8cc1Swenshuai.xi typedef enum 803*53ee8cc1Swenshuai.xi { 804*53ee8cc1Swenshuai.xi E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable 805*53ee8cc1Swenshuai.xi E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 806*53ee8cc1Swenshuai.xi E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 807*53ee8cc1Swenshuai.xi } HVD_FBReductionType; 808*53ee8cc1Swenshuai.xi 809*53ee8cc1Swenshuai.xi typedef enum 810*53ee8cc1Swenshuai.xi { 811*53ee8cc1Swenshuai.xi E_VDEC_EX_MAIN_VIEW = 0, ///< MVC main view 812*53ee8cc1Swenshuai.xi E_VDEC_EX_SUB_VIEW, ///< MVC sub view 813*53ee8cc1Swenshuai.xi } VDEC_EX_View; 814*53ee8cc1Swenshuai.xi 815*53ee8cc1Swenshuai.xi typedef enum 816*53ee8cc1Swenshuai.xi { 817*53ee8cc1Swenshuai.xi E_HVD_SECURE_MODE_NONE = 0, /// None secure 818*53ee8cc1Swenshuai.xi E_HVD_SECURE_MODE_TRUSTZONE /// Secure for TrustZone 819*53ee8cc1Swenshuai.xi } HVD_SECURE_MODE; 820*53ee8cc1Swenshuai.xi 821*53ee8cc1Swenshuai.xi typedef enum 822*53ee8cc1Swenshuai.xi { 823*53ee8cc1Swenshuai.xi E_HWDEC_ISR_NONE = 0, 824*53ee8cc1Swenshuai.xi E_HWDEC_ISR_HVD = 1, // For HW Decoder check 825*53ee8cc1Swenshuai.xi E_HWDEC_ISR_EVD = 2, 826*53ee8cc1Swenshuai.xi E_HWDEC_ISR_G2VP9 = 3 827*53ee8cc1Swenshuai.xi } HWDEC_ISR_TYPE; 828*53ee8cc1Swenshuai.xi 829*53ee8cc1Swenshuai.xi //HVD set MFcodec Mode 830*53ee8cc1Swenshuai.xi typedef enum 831*53ee8cc1Swenshuai.xi { 832*53ee8cc1Swenshuai.xi E_HVD_DEF_MFCODEC_DEFAULT = 0, 833*53ee8cc1Swenshuai.xi E_HVD_DEF_MFCODEC_FORCE_ENABLE, 834*53ee8cc1Swenshuai.xi E_HVD_DEF_MFCODEC_FORCE_DISABLE, 835*53ee8cc1Swenshuai.xi } HVD_MFCodec_mode; 836*53ee8cc1Swenshuai.xi 837*53ee8cc1Swenshuai.xi typedef enum 838*53ee8cc1Swenshuai.xi { 839*53ee8cc1Swenshuai.xi E_HVD_DEF_FEATURE_DEFAULT = 0, 840*53ee8cc1Swenshuai.xi E_HVD_DEF_FEATURE_FORCE_MAIN_PROFILE = 1, //BIT0=1: HEVC Only support Main profile decode 841*53ee8cc1Swenshuai.xi E_HVD_DEF_FEATURE_DISABLE_TEMPORAL_SCALABILITY = 1 << 1, // Bit 1 = 1: do not support temporal scalibity 842*53ee8cc1Swenshuai.xi } HVD_Feature; 843*53ee8cc1Swenshuai.xi 844*53ee8cc1Swenshuai.xi 845*53ee8cc1Swenshuai.xi typedef enum 846*53ee8cc1Swenshuai.xi { 847*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is Unsupported. 848*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_UNSUPPORTED = 0x0, 849*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvav.per". 850*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVAV_PER = 0x1, 851*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvav.pen". 852*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVAV_PEN = 0x2, 853*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvhe.der". 854*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVHE_DER = 0x4, 855*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvhe.den". 856*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVHE_DEN = 0x8, 857*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvhe.dtr". 858*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVHE_DTR = 0x10, 859*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvhe.stn". 860*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVHE_STN = 0x20, 861*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream profile is "dvhe.dth". 862*53ee8cc1Swenshuai.xi E_DV_STREAM_PROFILE_ID_DVHE_DTH = 0x40, 863*53ee8cc1Swenshuai.xi } DV_Stream_Profile; 864*53ee8cc1Swenshuai.xi 865*53ee8cc1Swenshuai.xi typedef enum 866*53ee8cc1Swenshuai.xi { 867*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is unsupported. 868*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_UNSUPPORTED = 0, 869*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "HD24". 870*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_HD24, 871*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "HD30". 872*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_HD30, 873*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "FHD24". 874*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_FHD24, 875*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "FHD30". 876*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_FHD30, 877*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "FHD60". 878*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_FHD60, 879*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "UHD24". 880*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_UHD24, 881*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "UHD30". 882*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_UHD30, 883*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "UHD48". 884*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_UHD48, 885*53ee8cc1Swenshuai.xi // Indicates Dolby Vision stream level is "UHD60". 886*53ee8cc1Swenshuai.xi E_DV_STREAM_LEVEL_ID_UHD60, 887*53ee8cc1Swenshuai.xi } DV_Stream_Level; 888*53ee8cc1Swenshuai.xi 889*53ee8cc1Swenshuai.xi typedef enum 890*53ee8cc1Swenshuai.xi { 891*53ee8cc1Swenshuai.xi E_HVD_ORIGINAL_MAIN_STREAM = 0, 892*53ee8cc1Swenshuai.xi E_HVD_ORIGINAL_SUB_STREAM, 893*53ee8cc1Swenshuai.xi E_HVD_ORIGINAL_N_STREAM, 894*53ee8cc1Swenshuai.xi } HVD_Original_Stream; 895*53ee8cc1Swenshuai.xi 896*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 897*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_EX_MemMap 898*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the HVD driver config 899*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 900*53ee8cc1Swenshuai.xi typedef struct 901*53ee8cc1Swenshuai.xi { 902*53ee8cc1Swenshuai.xi MS_PHY u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. 903*53ee8cc1Swenshuai.xi MS_PHY u32MIU2BaseAddr; //!< the physical memory start address of MIU 2 base address. 0: default value. 904*53ee8cc1Swenshuai.xi MS_VIRT u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM 905*53ee8cc1Swenshuai.xi MS_PHY u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. 906*53ee8cc1Swenshuai.xi MS_U32 u32FWBinarySize; //!< the FW code size 907*53ee8cc1Swenshuai.xi MS_VIRT u32VLCBinaryVAddr; //!< VLC table binary data buffer start address 908*53ee8cc1Swenshuai.xi MS_PHY u32VLCBinaryAddr; //!< VLC table binary data buffer start address 909*53ee8cc1Swenshuai.xi MS_U32 u32VLCBinarySize; //!<VLC table binary data buffer size 910*53ee8cc1Swenshuai.xi MS_VIRT u32CodeBufVAddr; //!< the virtual memory start address of code buffer 911*53ee8cc1Swenshuai.xi MS_PHY u32CodeBufAddr; //!< the physical memory start address of code buffer 912*53ee8cc1Swenshuai.xi MS_U32 u32CodeBufSize; //!< the code buffer size 913*53ee8cc1Swenshuai.xi MS_VIRT u32FrameBufVAddr; //!< the virtual memory start address of frame buffer 914*53ee8cc1Swenshuai.xi MS_PHY u32FrameBufAddr; //!< the physical memory start address of frame buffer 915*53ee8cc1Swenshuai.xi MS_U32 u32FrameBufSize; //!< the frame buffer size 916*53ee8cc1Swenshuai.xi MS_VIRT u32BitstreamBufVAddr; //!< the virtual memory start address of bit stream buffer 917*53ee8cc1Swenshuai.xi MS_PHY u32BitstreamBufAddr; //!< the physical memory start address of bit stream buffer 918*53ee8cc1Swenshuai.xi MS_U32 u32BitstreamBufSize; //!< the bit stream buffer size 919*53ee8cc1Swenshuai.xi MS_VIRT u32DrvProcessBufVAddr; //!< the virtual memory start address of driver process buffer 920*53ee8cc1Swenshuai.xi MS_PHY u32DrvProcessBufAddr; //!< the physical memory start address of driver process buffer 921*53ee8cc1Swenshuai.xi MS_U32 u32DrvProcessBufSize; //!< the driver process buffer size 922*53ee8cc1Swenshuai.xi MS_VIRT u32DynSacalingBufVAddr; //!< the virtual memory start address of dynamic scaling buffer 923*53ee8cc1Swenshuai.xi MS_PHY u32DynSacalingBufAddr; //!< the physical memory start address of dynamic scaling buffer 924*53ee8cc1Swenshuai.xi MS_U32 u32DynSacalingBufSize; //!< the dynamic scaling buffer size 925*53ee8cc1Swenshuai.xi HVD_FWInputSourceType eFWSourceType; //!< the input FW source type. 926*53ee8cc1Swenshuai.xi #ifdef VDEC3 927*53ee8cc1Swenshuai.xi MS_PHY u32TotalBitstreamBufAddr; 928*53ee8cc1Swenshuai.xi MS_U32 u32TotalBitstreamBufSize; 929*53ee8cc1Swenshuai.xi #endif 930*53ee8cc1Swenshuai.xi } HVD_EX_MemMap; 931*53ee8cc1Swenshuai.xi 932*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 933*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_Nal_Entry 934*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the information of one nal entry 935*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 936*53ee8cc1Swenshuai.xi typedef struct 937*53ee8cc1Swenshuai.xi { 938*53ee8cc1Swenshuai.xi MS_U32 u32NalID; ///< the ID nunber of this nal 939*53ee8cc1Swenshuai.xi MS_VIRT u32NalAddr; ///< the offset of this nal from bit stream buffer start address. unit: byte 940*53ee8cc1Swenshuai.xi MS_U32 u32NalSize; ///< the size of this nal. unit: byte 941*53ee8cc1Swenshuai.xi MS_U32 u32NalPTS; ///< the time stamp of this nal. unit: ms 942*53ee8cc1Swenshuai.xi MS_BOOL bRVBrokenPacket; ///< the RV only 943*53ee8cc1Swenshuai.xi } HVD_Nal_Entry; 944*53ee8cc1Swenshuai.xi 945*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 946*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: RV_FileInfo 947*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: RV file information 948*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 949*53ee8cc1Swenshuai.xi typedef struct 950*53ee8cc1Swenshuai.xi { 951*53ee8cc1Swenshuai.xi MS_U16 RV_Version; ///< Real Video Bitstream version 952*53ee8cc1Swenshuai.xi MS_U16 ulNumSizes; ///< Real Video Number sizes 953*53ee8cc1Swenshuai.xi MS_U16 ulPicSizes_w[8]; ///< Real Video file width 954*53ee8cc1Swenshuai.xi MS_U16 ulPicSizes_h[8]; ///< Real Video file height 955*53ee8cc1Swenshuai.xi } RV_FileInfo; 956*53ee8cc1Swenshuai.xi 957*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 958*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_FB_Reduction_Mode 959*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Set up frame buffer reduction mode 960*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 961*53ee8cc1Swenshuai.xi typedef struct 962*53ee8cc1Swenshuai.xi { 963*53ee8cc1Swenshuai.xi HVD_FBReductionType eLumaFBReductionMode; ///< Luma frame buffer reduction mode. 964*53ee8cc1Swenshuai.xi HVD_FBReductionType eChromaFBReductionMode; ///< Chroma frame buffer reduction mode. 965*53ee8cc1Swenshuai.xi MS_U8 u8EnableAutoMode; /// 0: Disable, 1: Enable 966*53ee8cc1Swenshuai.xi } HVD_FBReductionMode; 967*53ee8cc1Swenshuai.xi 968*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 969*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_Init_Params 970*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the initialization settings 971*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 972*53ee8cc1Swenshuai.xi typedef struct 973*53ee8cc1Swenshuai.xi { 974*53ee8cc1Swenshuai.xi MS_U32 u32ModeFlag; ///< init mode flag, use HVD_INIT_* to setup HVD. 975*53ee8cc1Swenshuai.xi MS_U32 u32FrameRate; ///< frame rate. 976*53ee8cc1Swenshuai.xi MS_U32 u32FrameRateBase; ///< frame rate base. The value of u32FrameRate /u32FrameRateBase must be frames per sec. 977*53ee8cc1Swenshuai.xi MS_U8 u8MinFrmGap; ///< set the min frame gap. 978*53ee8cc1Swenshuai.xi MS_U8 u8SyncType; ///< HVD_EX_SyncType. sync type of current playback. 979*53ee8cc1Swenshuai.xi MS_U16 u16Pitch; ///< not zero: specify the pitch. 0: use default value. 980*53ee8cc1Swenshuai.xi MS_U32 u32MaxDecTick; ///< not zero: specify the max decode tick. 0: use default value. 981*53ee8cc1Swenshuai.xi MS_BOOL bSyncEachFrm; ///< TRUE: sync STC at each frame. FALSE: not sync each frame. 982*53ee8cc1Swenshuai.xi MS_BOOL bAutoFreeES; ///< TRUE: auto free ES buffer when ES buffer is full. FALSE: not do the auto free. 983*53ee8cc1Swenshuai.xi MS_BOOL bAutoPowerSaving; ///< TRUE: auto power saving. FALSE: not do the auto power saving. 984*53ee8cc1Swenshuai.xi MS_BOOL bDynamicScaling; ///< TRUE: enable Dynamic Scaling. FALSE: disable Dynamic Scaling. 985*53ee8cc1Swenshuai.xi MS_BOOL bFastDisplay; ///< TRUE: enable Fast Display. FALSE: disable Fast Display. 986*53ee8cc1Swenshuai.xi MS_BOOL bUserData; ///< TRUE: enable processing User data. FALSE: disable processing User data. 987*53ee8cc1Swenshuai.xi MS_U8 u8TurboInit; ///< HVD_TurboInitLevel. set the turbo init mode. 988*53ee8cc1Swenshuai.xi MS_U8 u8TimeUnit; ///< HVD_Time_Unit_Type.set the type of input/output time unit. 989*53ee8cc1Swenshuai.xi MS_U16 u16DecoderClock; ///< HVD decoder clock speed. 0: default value. non-zero: any nearist clock. 990*53ee8cc1Swenshuai.xi MS_U16 u16ChipECONum; ///< Chip revision, ECO number. 991*53ee8cc1Swenshuai.xi RV_FileInfo* pRVFileInfo; ///< pointer to RV file info 992*53ee8cc1Swenshuai.xi HVD_FBReductionMode stFBReduction; ///< HVD Frame buffer reduction type 993*53ee8cc1Swenshuai.xi } HVD_Init_Params; 994*53ee8cc1Swenshuai.xi 995*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 996*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_BBU_Info 997*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the packet information 998*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 999*53ee8cc1Swenshuai.xi typedef struct 1000*53ee8cc1Swenshuai.xi { 1001*53ee8cc1Swenshuai.xi MS_VIRT u32Staddr; ///< Packet offset from bitstream buffer base address. unit: byte. 1002*53ee8cc1Swenshuai.xi MS_U32 u32Length; ///< Packet size. unit: byte. 1003*53ee8cc1Swenshuai.xi MS_VIRT u32Staddr2; ///< Packet offset from bitstream buffer base address. unit: byte. 1004*53ee8cc1Swenshuai.xi MS_U32 u32Length2; ///< Packet size. unit: byte. 1005*53ee8cc1Swenshuai.xi MS_U32 u32TimeStamp; ///< Packet time stamp. unit: ms. 1006*53ee8cc1Swenshuai.xi MS_U32 u32ID_L; ///< Packet ID low part. 1007*53ee8cc1Swenshuai.xi MS_U32 u32ID_H; ///< Packet ID high part. 1008*53ee8cc1Swenshuai.xi MS_U32 u32AllocLength; ///< Allocated Packet size. unit: byte. 1009*53ee8cc1Swenshuai.xi MS_U32 u32OriPktAddr; ///< Original packet offset from bitstream buffer base address. unit: byte. 1010*53ee8cc1Swenshuai.xi MS_BOOL bRVBrokenPacket; ///< the RV only 1011*53ee8cc1Swenshuai.xi } HVD_BBU_Info; 1012*53ee8cc1Swenshuai.xi 1013*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1014*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_Alive_Status 1015*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the decoder living information 1016*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1017*53ee8cc1Swenshuai.xi typedef struct 1018*53ee8cc1Swenshuai.xi { 1019*53ee8cc1Swenshuai.xi MS_U32 u32DecCnt; 1020*53ee8cc1Swenshuai.xi MS_U32 u32SkipCnt; 1021*53ee8cc1Swenshuai.xi MS_U32 u32IdleCnt; 1022*53ee8cc1Swenshuai.xi MS_U32 u32MainLoopCnt; 1023*53ee8cc1Swenshuai.xi MS_U32 u32LastAliveTime; 1024*53ee8cc1Swenshuai.xi } HVD_Alive_Status; 1025*53ee8cc1Swenshuai.xi 1026*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1027*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_DISP_INFO_THRESHOLD 1028*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the disp information threshold. 1029*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1030*53ee8cc1Swenshuai.xi typedef struct 1031*53ee8cc1Swenshuai.xi { 1032*53ee8cc1Swenshuai.xi MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 1033*53ee8cc1Swenshuai.xi MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 1034*53ee8cc1Swenshuai.xi MS_U32 u32MvopUpBound; //mvop filter upper bound 1035*53ee8cc1Swenshuai.xi MS_U32 u32MvopLowBound; //mvop filter lower bound 1036*53ee8cc1Swenshuai.xi } HVD_Disp_Info_TH; 1037*53ee8cc1Swenshuai.xi 1038*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1039*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_Settings 1040*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: Store the settings of user requirment 1041*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1042*53ee8cc1Swenshuai.xi typedef struct 1043*53ee8cc1Swenshuai.xi { 1044*53ee8cc1Swenshuai.xi // TODO: currently only DTV settings. Need to add more settings for MM. 1045*53ee8cc1Swenshuai.xi // Mode 1046*53ee8cc1Swenshuai.xi HVD_Disp_Info_TH DispInfoTH; 1047*53ee8cc1Swenshuai.xi MS_U32 u32IsrEvent; 1048*53ee8cc1Swenshuai.xi MS_BOOL bEnISR; 1049*53ee8cc1Swenshuai.xi 1050*53ee8cc1Swenshuai.xi MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 1051*53ee8cc1Swenshuai.xi MS_U8 bIsShowErrFrm; 1052*53ee8cc1Swenshuai.xi MS_U8 u8FrcMode; //HVD_EX_FrmRateConvMode 1053*53ee8cc1Swenshuai.xi 1054*53ee8cc1Swenshuai.xi MS_BOOL bIsErrConceal; 1055*53ee8cc1Swenshuai.xi MS_BOOL bAutoFreeES; 1056*53ee8cc1Swenshuai.xi MS_BOOL bDisDeblocking; 1057*53ee8cc1Swenshuai.xi MS_BOOL bDisQuarterPixel; 1058*53ee8cc1Swenshuai.xi 1059*53ee8cc1Swenshuai.xi MS_U8 bIsSyncOn; 1060*53ee8cc1Swenshuai.xi MS_U32 u32SyncTolerance; 1061*53ee8cc1Swenshuai.xi MS_U32 u32SyncRepeatTH; 1062*53ee8cc1Swenshuai.xi MS_U32 u32SyncVideoDelay; 1063*53ee8cc1Swenshuai.xi MS_U32 u32SyncFreeRunTH; 1064*53ee8cc1Swenshuai.xi MS_U32 u32MiuBurstLevel; 1065*53ee8cc1Swenshuai.xi } HVD_Settings; 1066*53ee8cc1Swenshuai.xi 1067*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1068*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_CC_Info 1069*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: HVD Close Caption Infomation. 1070*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1071*53ee8cc1Swenshuai.xi typedef struct 1072*53ee8cc1Swenshuai.xi { 1073*53ee8cc1Swenshuai.xi MS_U8 u8UserDataMode; 1074*53ee8cc1Swenshuai.xi MS_U8 u8ParsingStatus; 1075*53ee8cc1Swenshuai.xi MS_BOOL b708Enable; 1076*53ee8cc1Swenshuai.xi MS_BOOL b608InfoEnhance; 1077*53ee8cc1Swenshuai.xi //MS_BOOL bBufMiu1[2]; 1078*53ee8cc1Swenshuai.xi MS_U8 u8BufMiuSel[2]; 1079*53ee8cc1Swenshuai.xi MS_BOOL bOverFlow[2]; 1080*53ee8cc1Swenshuai.xi MS_PHY u32RingBufStartPAddr[2];//physical address 1081*53ee8cc1Swenshuai.xi MS_U32 u32RingBufLen[2]; 1082*53ee8cc1Swenshuai.xi MS_U32 volatile u32RingBufVacancy[2]; 1083*53ee8cc1Swenshuai.xi MS_PHY volatile u32RingBufRPAddr[2], u32RingBufWPAddr[2];//physical address 1084*53ee8cc1Swenshuai.xi MS_U32 volatile u32FWUsrDataRIdx, u32FWUsrDataWIdx; 1085*53ee8cc1Swenshuai.xi MS_U32 u32PktLen708; 1086*53ee8cc1Swenshuai.xi MS_VIRT u32PktHdrAddr708; 1087*53ee8cc1Swenshuai.xi MS_U8 u8CC608buf[512]; 1088*53ee8cc1Swenshuai.xi MS_U8 u8CC708buf[512]; 1089*53ee8cc1Swenshuai.xi } HVD_CC_Info; 1090*53ee8cc1Swenshuai.xi 1091*53ee8cc1Swenshuai.xi typedef struct 1092*53ee8cc1Swenshuai.xi { 1093*53ee8cc1Swenshuai.xi MS_U16 u16TmpRef; 1094*53ee8cc1Swenshuai.xi MS_U16 u16PicStruct; 1095*53ee8cc1Swenshuai.xi MS_U32 u32Pts; 1096*53ee8cc1Swenshuai.xi MS_U8 u8UsrDataCnt; 1097*53ee8cc1Swenshuai.xi } HVD_CC_608EnhanceInfo; 1098*53ee8cc1Swenshuai.xi 1099*53ee8cc1Swenshuai.xi 1100*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1101*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_ISR_Ctrl 1102*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: HVD driver ISR control. 1103*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1104*53ee8cc1Swenshuai.xi typedef struct 1105*53ee8cc1Swenshuai.xi { 1106*53ee8cc1Swenshuai.xi MS_BOOL bRegISR; 1107*53ee8cc1Swenshuai.xi MS_BOOL bInISR; 1108*53ee8cc1Swenshuai.xi MS_U32 u32ISRInfo; 1109*53ee8cc1Swenshuai.xi MS_U32 u32IntCount; 1110*53ee8cc1Swenshuai.xi HVD_ISRCallBack pfnISRCallBack; 1111*53ee8cc1Swenshuai.xi MS_BOOL bDisableISRFlag; 1112*53ee8cc1Swenshuai.xi MS_BOOL bIsHvdIsr; 1113*53ee8cc1Swenshuai.xi MS_BOOL bIsG2Vp9Isr; 1114*53ee8cc1Swenshuai.xi HWDEC_ISR_TYPE eHWDecIsr; //HVD, EVD, G2VP9 ISR 1115*53ee8cc1Swenshuai.xi } HVD_ISR_Ctrl; 1116*53ee8cc1Swenshuai.xi 1117*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1118*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Name: HVD_EX_Drv_Ctrl 1119*53ee8cc1Swenshuai.xi /// @brief \b Struct \b Description: HVD driver internal control. 1120*53ee8cc1Swenshuai.xi //----------------------------------------------------------------------------- 1121*53ee8cc1Swenshuai.xi typedef struct 1122*53ee8cc1Swenshuai.xi { 1123*53ee8cc1Swenshuai.xi // init stage 1124*53ee8cc1Swenshuai.xi MS_BOOL bUsed; 1125*53ee8cc1Swenshuai.xi HVD_EX_MemMap MemMap; ///< HVD memory config 1126*53ee8cc1Swenshuai.xi HVD_Init_Params InitParams; ///< HVD init settings 1127*53ee8cc1Swenshuai.xi MS_BOOL bNoDrvProccBuf; 1128*53ee8cc1Swenshuai.xi MS_BOOL bAutoRmLastZeroByte; 1129*53ee8cc1Swenshuai.xi MS_BOOL bCannotAccessMIU256; 1130*53ee8cc1Swenshuai.xi MS_U32 u32CmdTimeout; ///< HVD FW command timeout 1131*53ee8cc1Swenshuai.xi void *pLastFrmInfo; 1132*53ee8cc1Swenshuai.xi void *pLastFrmInfo_ext; 1133*53ee8cc1Swenshuai.xi 1134*53ee8cc1Swenshuai.xi // reset stage 1135*53ee8cc1Swenshuai.xi MS_U32 u32CtrlMode; ///< HVD run-time control flag 1136*53ee8cc1Swenshuai.xi MS_U32 u32DummyWriteBuf; ///< For dummy write MIU action. 1137*53ee8cc1Swenshuai.xi //MS_U32 u32CPUNonCacheMask; ///< CPU non-cache mask 1138*53ee8cc1Swenshuai.xi MS_U32 u32NULLPacketSize; ///< to store the size of AVI null packet pattern 1139*53ee8cc1Swenshuai.xi MS_VIRT u32NULLPacketAddr; ///< to store the start address of AVI null packet pattern from bitstream buffer base. 1140*53ee8cc1Swenshuai.xi MS_U32 u32RV_FlushPacketSize; ///< to store the size of rm flush packet pattern 1141*53ee8cc1Swenshuai.xi MS_U32 u32RV_FlushPacketAddr; ///< to store the start address of rm flush packet pattern from bitstream buffer base. 1142*53ee8cc1Swenshuai.xi MS_U32 u32StepDecodeCnt; 1143*53ee8cc1Swenshuai.xi //MS_U32 u32LastBBUPTS; 1144*53ee8cc1Swenshuai.xi //MS_U32 u32DummyDataSize; ///< buffer size of dummy data. 1145*53ee8cc1Swenshuai.xi //MS_U32 u32RestSizeofPushDummy; 1146*53ee8cc1Swenshuai.xi //MS_U32 u32AddrPushDummy; 1147*53ee8cc1Swenshuai.xi MS_U32 u32LastESRptr; 1148*53ee8cc1Swenshuai.xi MS_U32 u32BBUTblInBitstreamBufAddr; 1149*53ee8cc1Swenshuai.xi MS_U32 u32BBUPacketCnt; 1150*53ee8cc1Swenshuai.xi MS_U32 u32BBUWptr_Fired; 1151*53ee8cc1Swenshuai.xi MS_U32 u32LastErrCode; 1152*53ee8cc1Swenshuai.xi //MS_BOOL bPushingDummy; 1153*53ee8cc1Swenshuai.xi MS_BOOL bIsDispInfoChg; 1154*53ee8cc1Swenshuai.xi MS_BOOL bFrmRateSupported; 1155*53ee8cc1Swenshuai.xi HVD_Nal_Entry LastNal; 1156*53ee8cc1Swenshuai.xi HVD_Alive_Status LivingStatus; 1157*53ee8cc1Swenshuai.xi 1158*53ee8cc1Swenshuai.xi // recovery stage 1159*53ee8cc1Swenshuai.xi MS_BOOL bStepDecoding; 1160*53ee8cc1Swenshuai.xi HVD_Settings Settings; 1161*53ee8cc1Swenshuai.xi 1162*53ee8cc1Swenshuai.xi MS_U8 bTurboFWMode; //TRUE:not reload FW more than once if pre-decoder is the same. 1163*53ee8cc1Swenshuai.xi 1164*53ee8cc1Swenshuai.xi // ISR control 1165*53ee8cc1Swenshuai.xi HVD_ISR_Ctrl HVDISRCtrl; 1166*53ee8cc1Swenshuai.xi MS_U32 u32Sid; // stream ID 1167*53ee8cc1Swenshuai.xi 1168*53ee8cc1Swenshuai.xi // user data 1169*53ee8cc1Swenshuai.xi MS_U32 u32UsrDataRd; 1170*53ee8cc1Swenshuai.xi MS_U32 u32UsrDataWr; 1171*53ee8cc1Swenshuai.xi HVD_CC_Info CloseCaptionInfo; 1172*53ee8cc1Swenshuai.xi 1173*53ee8cc1Swenshuai.xi MS_U32 u32FlushRstPtr; ///< flush rst ptr: 0: init, 1:after flush and before push packet 1174*53ee8cc1Swenshuai.xi 1175*53ee8cc1Swenshuai.xi // Secure Mode 1176*53ee8cc1Swenshuai.xi MS_U8 u8SecureMode; // Enum HVD_SECURE_MODE 1177*53ee8cc1Swenshuai.xi MS_U8 u8SettingMode; // Record Setting mode 1178*53ee8cc1Swenshuai.xi MS_U8 u8Resv[2]; 1179*53ee8cc1Swenshuai.xi MS_U32 u32ExternalDSbuf; // External DS buffer 1180*53ee8cc1Swenshuai.xi MS_U8 u8CodeMiuSel; 1181*53ee8cc1Swenshuai.xi MS_U8 u8ESMiuSel; 1182*53ee8cc1Swenshuai.xi MS_U8 u8FrmMiuSel; 1183*53ee8cc1Swenshuai.xi MS_U8 u8Frm2MiuSel; 1184*53ee8cc1Swenshuai.xi MS_U8 u8DrvProccMiuSel; 1185*53ee8cc1Swenshuai.xi #ifdef VDEC3 1186*53ee8cc1Swenshuai.xi MS_BOOL bShareBBU; 1187*53ee8cc1Swenshuai.xi MS_U32 u32BBUId; 1188*53ee8cc1Swenshuai.xi HVD_Original_Stream eStream; 1189*53ee8cc1Swenshuai.xi #endif 1190*53ee8cc1Swenshuai.xi } HVD_EX_Drv_Ctrl; 1191*53ee8cc1Swenshuai.xi 1192*53ee8cc1Swenshuai.xi typedef void(*P_SC_ISR_Proc)(MS_U8 u8SCID); 1193*53ee8cc1Swenshuai.xi 1194*53ee8cc1Swenshuai.xi typedef struct 1195*53ee8cc1Swenshuai.xi { 1196*53ee8cc1Swenshuai.xi MS_BOOL bEnable; 1197*53ee8cc1Swenshuai.xi MS_U32 u32IapGnBufAddr; 1198*53ee8cc1Swenshuai.xi MS_U32 u32IapGnBufSize; 1199*53ee8cc1Swenshuai.xi } HVD_EX_IapGnBufShareBWMode; 1200*53ee8cc1Swenshuai.xi 1201*53ee8cc1Swenshuai.xi typedef struct 1202*53ee8cc1Swenshuai.xi { 1203*53ee8cc1Swenshuai.xi MS_BOOL bConnect; 1204*53ee8cc1Swenshuai.xi MS_U8 eMvopPath; 1205*53ee8cc1Swenshuai.xi } HVD_EX_DynmcDispPath; 1206*53ee8cc1Swenshuai.xi 1207*53ee8cc1Swenshuai.xi typedef struct 1208*53ee8cc1Swenshuai.xi { 1209*53ee8cc1Swenshuai.xi MS_BOOL bEnable; 1210*53ee8cc1Swenshuai.xi HVD_EX_DynmcDispPath stDynmcDispPath; 1211*53ee8cc1Swenshuai.xi } HVD_EX_PreCtrlDispPath; 1212*53ee8cc1Swenshuai.xi 1213*53ee8cc1Swenshuai.xi typedef struct 1214*53ee8cc1Swenshuai.xi { 1215*53ee8cc1Swenshuai.xi MS_BOOL bEnable; 1216*53ee8cc1Swenshuai.xi MS_U8 u8InputTsp; 1217*53ee8cc1Swenshuai.xi } HVD_EX_PreCtrlInputTsp; 1218*53ee8cc1Swenshuai.xi 1219*53ee8cc1Swenshuai.xi typedef struct 1220*53ee8cc1Swenshuai.xi { 1221*53ee8cc1Swenshuai.xi MS_BOOL bOnePendingBuffer; 1222*53ee8cc1Swenshuai.xi MS_BOOL bFrameRateHandling; 1223*53ee8cc1Swenshuai.xi MS_U32 u32PreSetFrameRate; 1224*53ee8cc1Swenshuai.xi HVD_EX_IapGnBufShareBWMode stIapGnShBWMode; 1225*53ee8cc1Swenshuai.xi MS_BOOL bDisableTspInBbuMode; 1226*53ee8cc1Swenshuai.xi HVD_MFCodec_mode eMFCodecMode; 1227*53ee8cc1Swenshuai.xi MS_BOOL bForce8BitMode; 1228*53ee8cc1Swenshuai.xi MS_U32 eVdecFeature; 1229*53ee8cc1Swenshuai.xi MS_BOOL bDVSingleLayerMode; 1230*53ee8cc1Swenshuai.xi MS_BOOL bEnableDynamicCMA; 1231*53ee8cc1Swenshuai.xi MS_BOOL bCalFrameRate; 1232*53ee8cc1Swenshuai.xi HVD_EX_PreCtrlDispPath stPreConnectDispPath; 1233*53ee8cc1Swenshuai.xi HVD_EX_PreCtrlInputTsp stPreConnectInputTsp; 1234*53ee8cc1Swenshuai.xi } HVD_Pre_Ctrl; 1235*53ee8cc1Swenshuai.xi 1236*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1237*53ee8cc1Swenshuai.xi // Function and Variable 1238*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 1239*53ee8cc1Swenshuai.xi extern MS_U32 u32UartCtrl; 1240*53ee8cc1Swenshuai.xi //extern MS_U32 u32InitSysTimeBase; 1241*53ee8cc1Swenshuai.xi 1242*53ee8cc1Swenshuai.xi #endif // _DRV_HVD_DEF_H_ 1243*53ee8cc1Swenshuai.xi 1244