1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114 #include "drvSYS.h"
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #if defined(VDEC3)
123 #include "../../../drv/hvd_lite/drvHVD_def.h"
124 #include "../hvd_lite/fwHVD_if.h"
125 #include "../mvd_lite/mvd4_interface.h"
126 #include "halHVD_EX.h"
127 #else
128 #include "../../../drv/hvd_lite/drvHVD_def.h"
129 #include "../hvd_lite/fwHVD_if.h"
130 #include "../mvd_lite/mvd4_interface.h"
131 #endif
132 #include "controller.h"
133
134 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
135 #include "ms_decompress.h"
136 #include "ms_decompress_priv.h"
137 #endif
138 #include "../../drv/mbx/apiMBX_St.h"
139 #include "../../drv/mbx/apiMBX.h"
140
141 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
142 #include "drvSERFLASH.h"
143 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
144 #endif
145
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #elif defined(MSOS_TYPE_ECOS)
150 #define VPRINTF diag_printf
151 #else
152 #ifndef ANDROID
153 #define VPRINTF printf
154 #else
155 #include <sys/mman.h>
156 #include <cutils/ashmem.h>
157 #include <cutils/log.h>
158 #define VPRINTF ALOGD
159 #endif
160 #endif
161
162 #ifdef CONFIG_MSTAR_CLKM
163 #include "drvCLKM.h"
164 #endif
165
166 //-------------------------------------------------------------------------------------------------
167 // Driver Compiler Options
168 //-------------------------------------------------------------------------------------------------
169
170
171 //-------------------------------------------------------------------------------------------------
172 // Local Defines
173 //-------------------------------------------------------------------------------------------------
174 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
175
176 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
177
178 #ifdef VDEC3
179 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
180 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
181 #define MAX_MVD_SLQ_COUNT 2
182 #define MAX_SUPPORT_DECODER_NUM 16
183 #else
184 #define MAX_SUPPORT_DECODER_NUM 2
185 #endif
186
187 typedef enum
188 {
189 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
190 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
191 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
192 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
193
194
195 typedef enum
196 {
197 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
198 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
199 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
200 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
201 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
202 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
203
204 typedef enum
205 {
206 E_VPU_UART_CTRL_DISABLE = BIT(4),
207 E_VPU_UART_CTRL_ERR = BIT(0),
208 E_VPU_UART_CTRL_INFO = BIT(1),
209 E_VPU_UART_CTRL_DBG = BIT(2),
210 E_VPU_UART_CTRL_FW = BIT(3),
211 E_VPU_UART_CTRL_MUST = BIT(4),
212 E_VPU_UART_CTRL_TRACE = BIT(5),
213 } VPU_EX_UartCtrl;
214
215 typedef struct
216 {
217 HAL_VPU_StreamId eStreamId;
218 VPU_EX_DecoderType eDecodertype;
219 } VPU_EX_Stream;
220
221 typedef struct
222 {
223 MS_BOOL bSTCSetMode;
224 MS_U32 u32STCindex;
225 }VPU_EX_STC;
226
227 #define VPU_MSG_ERR(format, args...) \
228 do \
229 { \
230 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
231 { \
232 VPRINTF("[VPU][ERR]%s:", __FUNCTION__); \
233 VPRINTF(format, ##args); \
234 } \
235 } while (0)
236
237 #define VPU_MSG_DBG(format, args...) \
238 do \
239 { \
240 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
241 { \
242 VPRINTF("[VPU][DBG]%s:", __FUNCTION__); \
243 VPRINTF(format, ##args); \
244 } \
245 } while (0)
246
247 #define VPU_MSG_INFO(format, args...) \
248 do \
249 { \
250 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
251 { \
252 VPRINTF("[VPU][INF]%s:", __FUNCTION__); \
253 VPRINTF(format, ##args); \
254 } \
255 } while (0)
256
257 //------------------------------ MIU SETTINGS ----------------------------------
258 #define _MaskMiuReq_VPU_D_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0));})
259 #define _MaskMiuReq_VPU_Q_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0));})
260 #define _MaskMiuReq_VPU_I_R(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(3));}):({_VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(7));})
261
262 #define _MaskMiu1Req_VPU_D_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0));})
263 #define _MaskMiu1Req_VPU_Q_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0));})
264 #define _MaskMiu1Req_VPU_I_R(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(3));}):({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(7));})
265
266 #define _MaskMiu2Req_VPU_D_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0));})
267 #define _MaskMiu2Req_VPU_Q_RW(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0));})
268 #define _MaskMiu2Req_VPU_I_R(vpu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(3));}):({_VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(7));})
269
270
271
272 #define VPU_D_RW_ON_MIU0(vpu) ((vpu==VPU_EVDR2)? \
273 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0)): \
274 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)))
275
276 #define VPU_Q_RW_ON_MIU0(vpu) ((vpu==VPU_EVDR2)? \
277 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0)): \
278 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)))
279
280 #define VPU_I_R_ON_MIU0(vpu) ((vpu==VPU_EVDR2)? \
281 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(3)) == 0)): \
282 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(7)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(7)) == 0)))
283
284 #define VPU_D_RW_ON_MIU1(vpu) ((vpu==VPU_EVDR2)? \
285 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0)): \
286 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)))
287
288 #define VPU_Q_RW_ON_MIU1(vpu) ((vpu==VPU_EVDR2)? \
289 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == BIT(5)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == 0)): \
290 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)))
291
292 #define VPU_I_R_ON_MIU1(vpu) ((vpu==VPU_EVDR2)? \
293 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == BIT(3)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(3)) == 0)): \
294 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(7)) == 0)))
295
296 #define VPU_D_RW_ON_MIU2(vpu) ((vpu==VPU_EVDR2)? \
297 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == BIT(5))): \
298 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))))
299
300 #define VPU_Q_RW_ON_MIU2(vpu) ((vpu==VPU_EVDR2)? \
301 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(5)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(5)) == BIT(5))): \
302 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))))
303
304 #define VPU_I_R_ON_MIU2(vpu) ((vpu==VPU_EVDR2)? \
305 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(3)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(3)) == BIT(3))): \
306 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(7)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(7)) == BIT(7))))
307
308
309
310 #define _VPU_MIU_SetReqMask(vpu, miu_clients, mask) \
311 do \
312 { \
313 if (miu_clients##_ON_MIU0(vpu) == 1) \
314 { \
315 _MaskMiuReq_##miu_clients(vpu,mask); \
316 } \
317 else \
318 { \
319 if (miu_clients##_ON_MIU1(vpu) == 1) \
320 { \
321 _MaskMiu1Req_##miu_clients(vpu,mask); \
322 } \
323 else if (miu_clients##_ON_MIU2(vpu) == 1) \
324 { \
325 _MaskMiu2Req_##miu_clients(vpu,mask); \
326 } \
327 } \
328 } while(0)
329
330
331
332
333 #if ENABLE_VPU_MUTEX_PROTECTION
334 MS_S32 s32VPUMutexID = -1;
335 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
336
337 #define _HAL_VPU_MutexCreate() \
338 if (s32VPUMutexID < 0) \
339 { \
340 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
341 }
342
343 #define _HAL_VPU_MutexDelete() \
344 if (s32VPUMutexID >= 0) \
345 { \
346 MsOS_DeleteMutex(s32VPUMutexID); \
347 s32VPUMutexID = -1; \
348 }
349
350 #define _HAL_VPU_Entry() \
351 if (s32VPUMutexID >= 0) \
352 { \
353 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
354 { \
355 VPRINTF("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
356 } \
357 }
358
359 #define _HAL_VPU_Return(_ret) \
360 { \
361 if (s32VPUMutexID >= 0) \
362 { \
363 MsOS_ReleaseMutex(s32VPUMutexID); \
364 } \
365 return _ret; \
366 }
367
368 #define _HAL_VPU_Release() \
369 { \
370 if (s32VPUMutexID >= 0) \
371 { \
372 MsOS_ReleaseMutex(s32VPUMutexID); \
373 } \
374 }
375 #else
376 #define _HAL_VPU_MutexCreate()
377 #define _HAL_VPU_MutexDelete()
378 #define _HAL_VPU_Entry()
379 #define _HAL_VPU_Return(_ret) {return _ret;}
380 #define _HAL_VPU_Release()
381 #endif
382
383 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
384 #define VPU_CMD_TIMEOUT 1000 // 1 sec
385
386 //-------------------------------------------------------------------------------------------------
387 // Local Structures
388 //-------------------------------------------------------------------------------------------------
389 typedef struct _VPU_HWInitFunc
390 {
391 MS_BOOL (*pfMVDHW_Init)(void);
392 MS_BOOL (*pfMVDHW_Deinit)(void);
393 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
394 MS_BOOL (*pfHVDHW_Deinit)(void);
395 } VPU_HWInitFunc;
396
397 typedef struct
398 {
399 MS_U32 u32ApiHW_Version; //<Version of current structure>
400 MS_U16 u16ApiHW_Length; //<Length of this structure>
401
402 MS_U8 u8Cap_Support_Decoder_Num;
403
404 MS_BOOL bCap_Support_MPEG2;
405 MS_BOOL bCap_Support_H263;
406 MS_BOOL bCap_Support_MPEG4;
407 MS_BOOL bCap_Support_DIVX311;
408 MS_BOOL bCap_Support_DIVX412;
409 MS_BOOL bCap_Support_FLV;
410 MS_BOOL bCap_Support_VC1ADV;
411 MS_BOOL bCap_Support_VC1MAIN;
412
413 MS_BOOL bCap_Support_RV8;
414 MS_BOOL bCap_Support_RV9;
415 MS_BOOL bCap_Support_H264;
416 MS_BOOL bCap_Support_AVS;
417 MS_BOOL bCap_Support_AVS_PLUS;
418 MS_BOOL bCap_Support_MJPEG;
419 MS_BOOL bCap_Support_MVC;
420 MS_BOOL bCap_Support_VP8;
421 MS_BOOL bCap_Support_VP9;
422 MS_BOOL bCap_Support_HEVC;
423
424 /*New HW Cap and Feature add in struct at the end*/
425 }VDEC_HwCap;
426
427 //-------------------------------------------------------------------------------------------------
428 // Local Functions Prototype
429 //-------------------------------------------------------------------------------------------------
430 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
431 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
432 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
433
434 //-------------------------------------------------------------------------------------------------
435 // Global Variables
436 //-------------------------------------------------------------------------------------------------
437 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
438 extern MS_BOOL HAL_MVD_InitHW(MS_U32 u32Id,VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
439 extern MS_BOOL HAL_MVD_DeinitHW(MS_U32 u32Id, VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
440 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
441 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
442 extern void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
443 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
444 #if SUPPORT_G2VP9 && defined(VDEC3)
445 extern MS_BOOL HAL_VP9_EX_DeinitHW(MS_U32 u32Id);
446 #endif
447 #if defined (__aeon__)
448 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
449 #else
450 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
451 #endif
452
453 //-------------------------------------------------------------------------------------------------
454 // Local Variables
455 //-------------------------------------------------------------------------------------------------
456 #if 0
457
458 static MS_BOOL _bVPUPowered = FALSE;
459 static MS_BOOL _bVPURsted = FALSE;
460 static MS_BOOL _bVPUSingleMode = FALSE;
461 static VPU_EX_DecModCfg _stVPUDecMode;
462
463 static MS_U8 u8TaskCnt = 0;
464
465 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
466
467 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
468 static VPU_EX_Stream _stVPUStream[] =
469 {
470 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
471 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
472 };
473 static VPU_HWInitFunc stHWInitFunc =
474 {
475 &HAL_MVD_InitHW,
476 &HAL_MVD_DeinitHW,
477 &HAL_HVD_EX_InitHW,
478 &HAL_HVD_EX_DeinitHW,
479 };
480
481 #endif
482
483 #if VPU_ENABLE_EMBEDDED_FW_BINARY
484 static const MS_U8 u8HVD_FW_Binary[] = {
485 #include "fwVPU.dat"
486 };
487
488 #if HVD_ENABLE_RV_FEATURE
489 static const MS_U8 u8HVD_VLC_Binary[] = {
490 #include "fwVPU_VLC.dat"
491 };
492 #endif
493 #endif
494
495
496 #ifdef VDEC3
497 typedef struct
498 {
499 MS_BOOL bTSP;
500 MS_U32 u32Used;
501 } BBU_STATE;
502
503 typedef struct
504 {
505 MS_BOOL bTSP;
506 MS_BOOL bUsedbyMVD;
507 MS_U32 u32Used;
508 } SLQ_STATE;
509 #endif
510
511 typedef struct
512 {
513 MS_BOOL _bVPUPowered;
514 MS_BOOL _bVPURsted;
515 VPU_EX_DecModCfg _stVPUDecMode;
516 MS_U8 u8TaskCnt;
517
518 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
519 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
520
521 VPU_HWInitFunc stHWInitFunc;
522
523 MS_BOOL bVpuExReloadFW;
524 MS_BOOL bVpuExLoadFWRlt;
525
526 #ifndef ONE_SETTING_FOR_DUAL_VPU
527 MS_BOOL _bVPUSingleMode;
528 MS_VIRT u32VPUSHMAddr; //PA
529 MS_BOOL bEnableVPUSecureMode;
530 #endif
531
532 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
533 MS_BOOL bEnableDymanicFBMode;
534 MS_PHY u32DynamicFBAddress;
535 MS_U32 u32DynamicFBSize;
536
537 #ifdef VDEC3
538 MS_VIRT u32FWCodeAddr;
539 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
540
541 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
542 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
543 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
544
545 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
546 #endif
547 VPU_EX_STC _stVPUSTCMode[2];
548 } VPU_Unit_Ctx;
549
550 //check initial value and de-initial value
551 typedef struct
552 {
553 VPU_Unit_Ctx _stCtx[MAX_VPU_NUM];
554 MS_U8 u8Cidx[MAX_SUPPORT_DECODER_NUM];
555
556 #ifdef ONE_SETTING_FOR_DUAL_VPU
557 MS_BOOL _bVPUSingleMode;
558 MS_VIRT u32VPUSHMAddr; //PA
559 MS_BOOL bEnableVPUSecureMode;
560 #endif
561 } VPU_Hal_CTX;
562
563 //global variables
564 VPU_Hal_CTX* pVPUHalContext = NULL;
565 VPU_Hal_CTX gVPUHalContext;
566
567 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
568 MS_BOOL bVPUMbxInitFlag = 0;
569 MS_U8 u8VPUMbxMsgClass = 0;
570 MBX_Msg VPUReeToTeeMbxMsg;
571 MBX_Msg VPUTeeToReeMbxMsg;
572
573 //-------------------------------------------------------------------------------------------------
574 // Debug Functions
575 //-------------------------------------------------------------------------------------------------
576
577
578 //-------------------------------------------------------------------------------------------------
579 // Local Functions
580 //-------------------------------------------------------------------------------------------------
581
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)582 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
583 {
584 #if HVD_ENABLE_RV_FEATURE
585 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
586 {
587 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
588 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
589 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
590
591 if (pVlcCfg->u32BinSize)
592 {
593 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
594
595 MS_U32 u32Start;
596 MS_U32 u32StartOffset;
597 MS_U8 u8MiuSel;
598
599 // Get MIU selection and offset from physical address = 0x30000000
600 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
601
602
603 if(u8MiuSel == E_CHIP_MIU_0)
604 cpyflag = E_SPIDMA_DEV_MIU0;
605 else if(u8MiuSel == E_CHIP_MIU_1)
606 cpyflag = E_SPIDMA_DEV_MIU1;
607 else if(u8MiuSel == E_CHIP_MIU_2)
608 cpyflag = E_SPIDMA_DEV_MIU2;
609
610 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
611 {
612 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
613 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
614
615 return FALSE;
616 }
617 }
618 else
619 {
620 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
621 return FALSE;
622 }
623 #else
624 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
625 return FALSE;
626 #endif
627 }
628 else
629 {
630 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
631 {
632 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
633 {
634 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
635 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
636
637 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
638 BDMA_Result bdmaRlt;
639 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
640
641 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
642 u32SrcAdd = pVlcCfg->u32BinAddr;
643 u32tabsize = pVlcCfg->u32BinSize;
644 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
645 MsOS_FlushMemory();
646 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
647
648 if (E_BDMA_OK != bdmaRlt)
649 {
650 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
651 }
652 #else
653 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
654 #endif
655 }
656 else
657 {
658 VPU_MSG_ERR
659 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
660 return FALSE;
661 }
662 }
663 else
664 {
665 #if VPU_ENABLE_EMBEDDED_FW_BINARY
666 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
667 MS_U8 *pu8HVD_VLC_Binary;
668
669 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
670
671 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
672 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
673 (MS_U32) sizeof(u8HVD_VLC_Binary));
674
675 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
676 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
677 #else
678 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
679 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
680 (MS_U32) sizeof(u8HVD_VLC_Binary));
681
682 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
683 #endif
684 #else
685 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
686 return FALSE;
687 #endif
688 }
689 }
690 #endif
691
692 return TRUE;
693 }
694
695 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)696 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
697 {
698 MS_U8 u8OffsetIdx = 0;
699 MS_U8 u8VSidBaseMask = 0xF0;
700 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
701
702 switch (eVSidBase)
703 {
704 case E_HAL_VPU_MAIN_STREAM_BASE:
705 {
706 u8OffsetIdx = 0;
707 break;
708 }
709 case E_HAL_VPU_SUB_STREAM_BASE:
710 {
711 u8OffsetIdx = 1;
712 break;
713 }
714 case E_HAL_VPU_MVC_STREAM_BASE:
715 {
716 u8OffsetIdx = 0;
717 break;
718 }
719 #ifdef VDEC3
720 case E_HAL_VPU_N_STREAM_BASE:
721 {
722 u8OffsetIdx = u32Id & 0x0F;
723 break;
724 }
725 #endif
726 default:
727 {
728 u8OffsetIdx = 0;
729 break;
730 }
731 }
732
733 /*
734 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
735 u32Id, eVSidBase, u8OffsetIdx);
736 */
737 return u8OffsetIdx;
738 }
739
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)740 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
741 {
742 return _VPU_EX_GetOffsetIdx(u32Id);
743 }
HAL_VPU_EX_Mutex_Lock(void)744 void HAL_VPU_EX_Mutex_Lock(void)
745 {
746 _HAL_VPU_Entry();
747 }
748
HAL_VPU_EX_Mutex_UnLock(void)749 void HAL_VPU_EX_Mutex_UnLock(void)
750 {
751 _HAL_VPU_Release();
752 }
753
754
_VPU_EX_Context_Init(void)755 static void _VPU_EX_Context_Init(void)
756 {
757 MS_U8 i,j;
758 VPU_Unit_Ctx *pVPUCtx = NULL;
759
760 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
761 {
762 pVPUHalContext->u8Cidx[i] = 0xFF;
763 }
764
765 for (j = 0; j < MAX_VPU_NUM; j++)
766 {
767 pVPUCtx = &pVPUHalContext->_stCtx[j];
768
769 #ifdef VDEC3
770 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
771 {
772 pVPUCtx->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
773 pVPUCtx->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
774 }
775
776 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
777 {
778 pVPUCtx->stHVD_BBU_STATE[i].bTSP = FALSE;
779 pVPUCtx->stHVD_BBU_STATE[i].u32Used = 0;
780 }
781
782 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
783 {
784 pVPUCtx->stEVD_BBU_STATE[i].bTSP = FALSE;
785 pVPUCtx->stEVD_BBU_STATE[i].u32Used = 0;
786 }
787
788 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
789 {
790 pVPUCtx->stMVD_SLQ_STATE[i].bTSP = FALSE;
791 pVPUCtx->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
792 pVPUCtx->stMVD_SLQ_STATE[i].u32Used = 0;
793 }
794 #else
795 pVPUCtx->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
796 pVPUCtx->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
797 #endif
798
799 pVPUCtx->bVpuExReloadFW = TRUE;
800 }
801 }
802
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)803 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
804 {
805 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
806 MS_U8 u8OffsetIdx = 0;
807
808 if (NULL == pTaskInfo)
809 {
810 return eCmd;
811 }
812
813 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
814
815 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
816 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
817
818 #ifdef VDEC3
819 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
820 {
821 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
822 {
823 eCmd = E_NST_CMD_TASK_MVD_TSP;
824 }
825 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
826 {
827 eCmd = E_NST_CMD_TASK_MVD_SLQ;
828 }
829 }
830 #else
831 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
832 {
833 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
834 {
835 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
836 }
837 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
838 {
839 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
840 }
841 }
842 #endif
843 #ifdef VDEC3
844 #if SUPPORT_G2VP9
845 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
846 #else
847 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
848 #endif
849 {
850 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
851 {
852 eCmd = E_NST_CMD_TASK_HVD_TSP;
853 }
854 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
855 {
856 eCmd = E_NST_CMD_TASK_HVD_BBU;
857 }
858 }
859 #else
860 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
861 {
862 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
863 {
864 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
865 }
866 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
867 {
868 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
869 }
870 }
871 #endif
872
873 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
874 return eCmd;
875 }
876
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)877 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
878 {
879 if (!pTaskInfo)
880 {
881 VPU_MSG_ERR("null input\n");
882 return FALSE;
883 }
884
885 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
886 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
887
888 //Check if we need to init MVD HW
889 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
890 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
891 {
892 //Init HW
893 if (FALSE == HAL_VPU_EX_MVDInUsed(pTaskInfo->u32Id))
894 {
895 if (TRUE != HAL_MVD_InitHW(pTaskInfo->u32Id,pTaskInfo->eSrcType,pTaskInfo->eDecType))
896 {
897 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
898 return FALSE;
899 }
900 }
901 else
902 {
903 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
904 }
905 }
906
907 //MVD use sub mvop
908 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
909 #ifdef VDEC3
910 (pTaskInfo->u8HalId == 1) )
911 #else
912 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
913 #endif
914 {
915 VPU_MSG_ERR("Force turn on HVD\n");
916 if(!HAL_VPU_EX_HVDInUsed(pTaskInfo->u32Id))
917 {
918 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUCtx->_stVPUDecMode.u8DecMod)
919 {
920 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
921 {
922 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
923 return FALSE;
924 }
925 }
926 else
927 {
928 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
929 #ifdef CONFIG_MSTAR_CLKM
930 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
931 #else
932 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id,TRUE);
933 #endif
934 }
935 }
936 else
937 {
938 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
939 }
940 }
941
942 //Check if we need to init HVD HW
943 #ifdef VDEC3
944 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
945 #else
946 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
947 #endif
948 {
949 if (!HAL_VPU_EX_MVDInUsed(pTaskInfo->u32Id))
950 {
951 if (!HAL_MVD_InitHW(pTaskInfo->u32Id,pTaskInfo->eSrcType,pTaskInfo->eDecType))
952 {
953 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
954 return FALSE;
955 }
956 }
957
958 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
959 {
960 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
961 return FALSE;
962 }
963 }
964
965 #if SUPPORT_G2VP9 && defined(VDEC3)
966 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
967 {
968 if (!HAL_VPU_EX_MVDInUsed(pTaskInfo->u32Id))
969 {
970 if (!HAL_MVD_InitHW(pTaskInfo->u32Id,pTaskInfo->eSrcType,pTaskInfo->eDecType))
971 {
972 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
973 return FALSE;
974 }
975 }
976 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
977 {
978 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
979 return FALSE;
980 }
981 }
982 #endif
983
984 return TRUE;
985 }
986
_VPU_EX_InClock(MS_U32 u32type)987 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
988 {
989 switch (u32type)
990 {
991 case VPU_CLOCK_480MHZ:
992 return 480000000UL;
993 case VPU_CLOCK_432MHZ:
994 return 432000000UL;
995 case VPU_CLOCK_384MHZ:
996 return 384000000UL;
997 default:
998 return 480000000UL;
999 }
1000 }
1001
1002
1003 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL)
1004 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)1005 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
1006 {
1007 //#ifndef MSOS_TYPE_LINUX_KERNEL
1008 #if 1
1009 MS_U8 ClassNum = 0;
1010 MBX_Result result;
1011
1012 if (bVPUMbxInitFlag == TRUE)
1013 {
1014 return TRUE;
1015 }
1016
1017 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
1018 {
1019 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
1020 return FALSE;
1021 }
1022 else
1023 {
1024 MApi_MBX_Enable(TRUE);
1025 }
1026
1027 if (E_MBX_SUCCESS != MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum))
1028 {
1029 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail\n");
1030 return FALSE;
1031 }
1032
1033 result = MApi_MBX_RegisterMSG(ClassNum, 10);
1034
1035 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
1036 {
1037 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
1038 return FALSE;
1039 }
1040 else
1041 {
1042 bVPUMbxInitFlag = TRUE;
1043 u8VPUMbxMsgClass = ClassNum;
1044 return TRUE;
1045 }
1046 #else
1047 return FALSE;
1048 #endif
1049 }
1050
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type,MS_BOOL bIsHVD)1051 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type,MS_BOOL bIsHVD)
1052 {
1053 MBX_Result result;
1054 MS_U8 u8Index;
1055
1056 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1057 {
1058 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1059 }
1060
1061 if (bVPUMbxInitFlag == FALSE)
1062 {
1063 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1064 }
1065
1066 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1067 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1068 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1069 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1070 VPUReeToTeeMbxMsg.u8Index = msg_type;
1071 VPUReeToTeeMbxMsg.u8ParameterCount = 1;
1072 VPUReeToTeeMbxMsg.u8Parameters[0] = bIsHVD;
1073
1074 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1075 if (E_MBX_SUCCESS != result)
1076 {
1077 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1078 }
1079
1080 // Receive Reply ACK from TEE side.
1081 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1082
1083 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1084
1085 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1086 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1087 {
1088 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1089 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1090 }
1091 else
1092 #else
1093 do
1094 {
1095 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1096 } while(E_MBX_SUCCESS != result);
1097 #endif
1098 {
1099 u8Index = VPUTeeToReeMbxMsg.u8Index;
1100 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1101
1102 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1103 {
1104 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1105 }
1106 }
1107
1108 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1109 }
1110
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1111 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1112 {
1113 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1114 {
1115 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,0) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1116 {
1117 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1118 return FALSE;
1119 }
1120 else
1121 {
1122 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1123 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1124 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1125 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1126 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1127 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1128 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1129 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1130
1131 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1132
1133
1134 MS_U32 u32Start;
1135
1136 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1137 {
1138 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1139 pVPUHalContext->u32VPUSHMAddr = u32Start;
1140 }
1141 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1142 {
1143 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1144 pVPUHalContext->u32VPUSHMAddr = u32Start;
1145
1146 }
1147 else // == 0
1148 {
1149 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1150 }
1151 }
1152 }
1153 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1154 {
1155 MS_U32 u32Offset;
1156 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1157 {
1158 u32Offset = u32SHMAddr-u32MIU1Addr;
1159 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1160 }
1161 else
1162 {
1163 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1164 }
1165 }
1166 return true;
1167 }
1168
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1169 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1170 {
1171 bVPUMbxInitFlag = TRUE;
1172 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1173 return TRUE;
1174 }
1175 #endif
1176
HAL_VPU_EX_GetFWReload(MS_U32 u32Id)1177 MS_BOOL HAL_VPU_EX_GetFWReload(MS_U32 u32Id)
1178 {
1179 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1180 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
1181
1182 return pVPUCtx->bVpuExReloadFW;
1183 }
1184
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1185 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1186 {
1187 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1188 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1189 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1190 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1191 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1192 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1193 )
1194 {
1195 return FALSE;
1196 }
1197 else
1198 {
1199 return TRUE;
1200 }
1201 }
1202
_VPU_EX_InitAll(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1203 static MS_BOOL _VPU_EX_InitAll(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1204 {
1205 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1206 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
1207 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[u8VPU];
1208
1209 MS_PHY u32fwPA = NULL; //physical address
1210 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ; ///Note : Max EVD_R2 clock in Kano is only 480MHz
1211
1212 if (TRUE == HAL_VPU_EX_IsPowered(u32Id))
1213 {
1214 VPU_MSG_DBG("IsPowered\n");
1215 return TRUE;
1216 }
1217 else
1218 {
1219 //VPU hold
1220 HAL_VPU_EX_SwRst(u32Id, FALSE);
1221
1222 //VPU clock on
1223 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1224
1225 if (VPU_I_R_ON_MIU0(u8VPU))
1226 VPUInitParams.u8MiuSel = 0;
1227 else if (VPU_I_R_ON_MIU1(u8VPU))
1228 VPUInitParams.u8MiuSel = 1;
1229 else if (VPU_I_R_ON_MIU2(u8VPU))
1230 VPUInitParams.u8MiuSel = 2;
1231
1232 HAL_VPU_EX_Init(u32Id, &VPUInitParams);
1233 }
1234
1235 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1236 VPU_EX_TaskInfo *pTaskInfo = NULL;
1237 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1238
1239 if (pInitPara)
1240 {
1241 pFWCodeCfg = pInitPara->pFWCodeCfg;
1242 pTaskInfo = pInitPara->pTaskInfo;
1243 pVlcCfg = pInitPara->pVLCCfg;
1244 }
1245 else
1246 {
1247 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1248 return FALSE;
1249 }
1250
1251 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1252 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1253 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1254 {
1255 SYS_TEEINFO teemode;
1256 MDrv_SYS_ReadKernelCmdLine();
1257 MDrv_SYS_GetTEEInfo(&teemode);
1258 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1259 {
1260 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1261
1262 if (FALSE == HAL_VPU_EX_GetFWReload(u32Id))
1263 {
1264 if (FALSE == pVPUCtx->bVpuExLoadFWRlt)
1265 {
1266 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1267 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,(pTaskInfo->eDecType == E_VPU_EX_DECODER_HVD)) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1268 {
1269 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1270 return FALSE;
1271 }
1272 pVPUCtx->bVpuExLoadFWRlt = TRUE;
1273 }
1274 else
1275 {
1276 //Check f/w prefix "VDEC30"
1277 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1278 {
1279 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1280 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,(pTaskInfo->eDecType == E_VPU_EX_DECODER_HVD)) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1281 {
1282 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1283 pVPUCtx->bVpuExLoadFWRlt = FALSE;
1284 return FALSE;
1285 }
1286 }
1287 else
1288 {
1289 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1290 }
1291 }
1292 }
1293 else
1294 {
1295 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,(pTaskInfo->eDecType == E_VPU_EX_DECODER_HVD)) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1296 {
1297 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1298 pVPUCtx->bVpuExLoadFWRlt = FALSE;
1299 return FALSE;
1300 }
1301 pVPUCtx->bVpuExLoadFWRlt = TRUE;
1302 }
1303 }
1304 }
1305 else
1306 #endif
1307 {
1308 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1309
1310 if (!HAL_VPU_EX_LoadCode(u32Id, pFWCodeCfg))
1311 {
1312 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1313 return FALSE;
1314 }
1315 }
1316
1317 if (pVlcCfg)
1318 {
1319 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1320 {
1321 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1322 return FALSE;
1323 }
1324 }
1325
1326 if (!HAL_VPU_EX_CPUSetting(u32Id, u32fwPA))
1327 {
1328 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1329 return FALSE;
1330 }
1331
1332 //Init HW
1333 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1334 {
1335 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1336 //_MVD_INIT_FAIL_RET();
1337 return FALSE;
1338 }
1339 else
1340 {
1341 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1342 }
1343
1344 //set vpu clock to FW
1345 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1346 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1347
1348 ctl_ptr->statue = CTL_STU_NONE;
1349 //notify controller the interface version of VPU driver.
1350 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1351 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1352 ctl_ptr->u8HicodecType = u8VPU;
1353 MsOS_FlushMemory();
1354 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1355
1356 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1357 if (TRUE == HAL_VPU_EX_IsRsted(u32Id))
1358 {
1359 VPU_MSG_DBG("VPU_IsRsted\n");
1360 return TRUE;
1361 }
1362 else
1363 {
1364 HAL_VPU_EX_SwRstRelse(u32Id);
1365 }
1366
1367 return TRUE;
1368 }
1369
_VPU_EX_DeinitHW(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo)1370 static MS_BOOL _VPU_EX_DeinitHW(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo)
1371 {
1372 MS_BOOL bRet = FALSE;
1373
1374 if (FALSE == HAL_VPU_EX_MVDInUsed(u32Id))
1375 {
1376 bRet = HAL_MVD_DeinitHW(u32Id, pTaskInfo->eSrcType, pTaskInfo->eDecType);
1377 }
1378
1379 if (FALSE == HAL_VPU_EX_HVDInUsed(u32Id))
1380 {
1381 bRet = HAL_HVD_EX_DeinitHW(u32Id);
1382 }
1383 #if SUPPORT_G2VP9 && defined(VDEC3)
1384 if (FALSE == HAL_VPU_EX_G2VP9InUsed(u32Id))
1385 {
1386 bRet = HAL_VP9_EX_DeinitHW(u32Id);
1387 }
1388 #endif
1389 return bRet;
1390 }
1391
_VPU_EX_DeinitAll(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1392 static MS_BOOL _VPU_EX_DeinitAll(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1393 {
1394 HAL_VPU_EX_SwRst(u32Id, TRUE);
1395 _VPU_EX_DeinitHW(u32Id, pInitPara->pTaskInfo);
1396 HAL_VPU_EX_DeInit(u32Id);
1397
1398 return TRUE;
1399 }
1400
_VPU_EX_GetActiveCodecCnt(MS_U32 u32Id)1401 static MS_U8 _VPU_EX_GetActiveCodecCnt(MS_U32 u32Id)
1402 {
1403 MS_U32 i;
1404 MS_U8 u8ActiveCnt = 0;
1405 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1406 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
1407
1408 for (i = 0; i < sizeof(pVPUCtx->_stVPUStream) / sizeof(pVPUCtx->_stVPUStream[0]); i++)
1409 {
1410 if (E_VPU_EX_DECODER_NONE != pVPUCtx->_stVPUStream[i].eDecodertype &&
1411 E_VPU_EX_DECODER_GET != pVPUCtx->_stVPUStream[i].eDecodertype &&
1412 E_VPU_EX_DECODER_GET_MVC != pVPUCtx->_stVPUStream[i].eDecodertype)
1413 {
1414 u8ActiveCnt++;
1415 }
1416 }
1417 if (pVPUCtx->u8TaskCnt != u8ActiveCnt)
1418 {
1419 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUCtx->u8TaskCnt, u8ActiveCnt);
1420 }
1421 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1422
1423 return u8ActiveCnt;
1424 }
1425
_VPU_EX_ClockInv(MS_BOOL bEnable)1426 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1427 {
1428 if (TRUE)
1429 {
1430 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1431 }
1432 else
1433 {
1434 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1435 }
1436 }
1437
_VPU_EX_ClockSpeed(MS_U32 u32type)1438 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1439 {
1440 switch (u32type)
1441 {
1442 case VPU_CLOCK_480MHZ:
1443 case VPU_CLOCK_432MHZ:
1444 case VPU_CLOCK_384MHZ:
1445 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1446 break;
1447 default:
1448 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_480MHZ, TOP_CKG_VPU_CLK_MASK);
1449 break;
1450 }
1451 }
1452
1453 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(MS_U32 u32Id)1454 static MS_BOOL _VPU_EX_MAU_IDLE(MS_U32 u32Id)
1455 {
1456 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1457 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
1458
1459 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0(u8VPU)) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1460 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0(u8VPU)) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1461 {
1462 return TRUE;
1463 }
1464 return FALSE;
1465 }
1466 #endif
1467
1468 #ifdef VDEC3
_VPU_EX_DecideCidx(MS_U8 u8OffsetIdx,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)1469 static MS_U8 _VPU_EX_DecideCidx(MS_U8 u8OffsetIdx, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
1470 #else
1471 static MS_U8 _VPU_EX_DecideCidx(MS_U8 u8OffsetIdx, MS_BOOL bIsEVD)
1472 #endif
1473 {
1474 MS_U8 u8DecideCidx = 0;
1475
1476 #if (VPU_DISPATCH_POLICY == USE_FIRST_VPU_ONLY)
1477 {
1478 u8DecideCidx = 0;
1479 }
1480 #elif (VPU_DISPATCH_POLICY == USE_SECOND_VPU_ONLY)
1481 {
1482 u8DecideCidx = 1;
1483 }
1484 #elif (VPU_DISPATCH_POLICY == USE_KANO_RULE)
1485 {
1486 if (bIsEVD)
1487 {
1488 MS_U8 i = 0;
1489 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[0];
1490 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
1491 {
1492 if (E_VPU_EX_DECODER_EVD == pVPUCtx->_stVPUStream[i].eDecodertype)
1493 {
1494 break;
1495 }
1496 }
1497
1498 if (i < MAX_SUPPORT_DECODER_NUM)
1499 {
1500 u8DecideCidx = 1;
1501 }
1502 else
1503 {
1504 u8DecideCidx = 0;
1505 }
1506 }
1507 else
1508 {
1509 u8DecideCidx = 0;
1510 }
1511 }
1512 #elif (VPU_DISPATCH_POLICY == USE_KANO_INV_RULE)
1513 {
1514 if (bIsEVD)
1515 {
1516 MS_U8 i = 0;
1517 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[1];
1518 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
1519 {
1520 if (E_VPU_EX_DECODER_EVD == pVPUCtx->_stVPUStream[i].eDecodertype)
1521 {
1522 break;
1523 }
1524 }
1525
1526 if (i < MAX_SUPPORT_DECODER_NUM)
1527 {
1528 u8DecideCidx = 0;
1529 }
1530 else
1531 {
1532 u8DecideCidx = 1;
1533 }
1534 }
1535 else
1536 {
1537 u8DecideCidx = 0;
1538 }
1539 }
1540 #elif (VPU_DISPATCH_POLICY == USE_MAIN_EVD_IN_LITE)
1541 {
1542 if (bIsEVD && (u8OffsetIdx==0))
1543 {
1544 u8DecideCidx = 1;
1545 }
1546 else
1547 {
1548 u8DecideCidx = 0;
1549 }
1550 }
1551 #elif (VPU_DISPATCH_POLICY == USE_MAIN_EVD_IN_LITE_NDEC_IN_HICODEC)
1552 {
1553 if(bIsNStreamMode)
1554 {
1555 u8DecideCidx = 0;
1556 }
1557 else
1558 {
1559 if (bIsEVD && (u8OffsetIdx==0))
1560 {
1561 u8DecideCidx = 1;
1562 }
1563 else
1564 {
1565 u8DecideCidx = 0;
1566 }
1567 }
1568 }
1569 #endif
1570
1571 if(pVPUHalContext->bEnableVPUSecureMode == TRUE) //because tee world can't get this information,tmp solution,fix me
1572 {
1573 u8DecideCidx = 0;
1574 VPRINTF("[VDEC][%s]Secure mode always use u8DecideCidx=%d\n",__FUNCTION__,u8DecideCidx);
1575 }
1576
1577 VPRINTF("[%s] policy=%d, u8Id=%d, bIsEVD=%d, u8DecideCidx=%d \n", __FUNCTION__, VPU_DISPATCH_POLICY, u8OffsetIdx, bIsEVD, u8DecideCidx);
1578 return u8DecideCidx;
1579 }
1580
1581 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1582 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1583 {
1584 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1585 {
1586 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1587 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1588 ms_VDECDecompressDeInit();
1589 return TRUE;
1590 }
1591 else
1592 {
1593 return FALSE;
1594 }
1595 }
1596 #endif
1597
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1598 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1599 {
1600 MS_BOOL bRet = TRUE;
1601 pVPUHalContext->_bVPUSingleMode = bEnable;
1602 return bRet;
1603 }
1604
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCindex)1605 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCindex)
1606 {
1607 MS_BOOL bRet = TRUE;
1608 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1609 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
1610
1611 pVPUCtx->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = 1;
1612 pVPUCtx->_stVPUSTCMode[u8OffsetIdx].u32STCindex = u32STCindex;
1613
1614 return bRet;
1615 }
1616
HAL_VPU_EX_SetDecodeMode(MS_U32 u32Id,VPU_EX_DecModCfg * pstCfg)1617 MS_BOOL HAL_VPU_EX_SetDecodeMode(MS_U32 u32Id, VPU_EX_DecModCfg *pstCfg)
1618 {
1619 MS_U8 i = 0;
1620 MS_BOOL bRet = TRUE;
1621 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1622 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
1623
1624 if (pstCfg != NULL)
1625 {
1626 pVPUCtx->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1627 pVPUCtx->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1628 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1629 {
1630 pVPUCtx->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1631 }
1632 pVPUCtx->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1633 pVPUCtx->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1634 }
1635 else
1636 {
1637 bRet = FALSE;
1638 }
1639 return bRet;
1640 }
1641
1642 //static MS_BOOL bVpuExReloadFW = TRUE;
1643 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_U32 u32Id,MS_BOOL bReload)1644 MS_BOOL HAL_VPU_EX_SetFWReload(MS_U32 u32Id, MS_BOOL bReload)
1645 {
1646 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1647 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
1648
1649 pVPUCtx->bVpuExReloadFW = bReload;
1650 //VPRINTF("%s bVpuExReloadFW = %x\n", __FUNCTION__, pVPUCtx->bVpuExReloadFW);
1651 return TRUE;
1652 }
1653
1654
1655 //-------------------------------------------------------------------------------------------------
1656 // Global Functions
1657 //-------------------------------------------------------------------------------------------------
1658 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1659 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1660 {
1661 #if HVD_ENABLE_RV_FEATURE
1662 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1663 {
1664 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1665 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1666 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1667
1668 if (pVlcCfg->u32BinSize)
1669 {
1670 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1671
1672 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1673 {
1674 cpyflag = E_SPIDMA_DEV_MIU1;
1675 }
1676 else
1677 {
1678 cpyflag = E_SPIDMA_DEV_MIU0;
1679 }
1680
1681 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1682 {
1683 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1684 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1685
1686 return FALSE;
1687 }
1688 }
1689 else
1690 {
1691 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1692 return FALSE;
1693 }
1694 #else
1695 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1696 return FALSE;
1697 #endif
1698 }
1699 else
1700 {
1701 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1702 {
1703 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1704 {
1705 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1706 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1707
1708 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1709 BDMA_Result bdmaRlt;
1710
1711 MsOS_FlushMemory();
1712 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1713
1714 if (E_BDMA_OK != bdmaRlt)
1715 {
1716 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1717 }
1718 #else
1719 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1720 #endif
1721 }
1722 else
1723 {
1724 VPU_MSG_ERR
1725 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1726 return FALSE;
1727 }
1728 }
1729 else
1730 {
1731 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1732 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1733 MS_U8 *pu8HVD_VLC_Binary;
1734
1735 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1736
1737 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1738 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1739 (MS_U32) sizeof(u8HVD_VLC_Binary));
1740
1741 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1742 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1743 #else
1744 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1745 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1746 (MS_U32) sizeof(u8HVD_VLC_Binary));
1747
1748 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1749 #endif
1750 #else
1751 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1752 return FALSE;
1753 #endif
1754 }
1755 }
1756 #endif
1757
1758 return TRUE;
1759 }
1760 #endif
1761
1762 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1763 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1764 #else
1765 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1766 #endif
1767 {
1768 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1769 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1770 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8Offset]];
1771 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1772 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1773 MS_U32 u32Arg = 0xFFFFFFFF;
1774 MS_U32 u32Timeout = 0;
1775 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1776 MS_U32 u32CmdArg = 0;
1777 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1778 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1779
1780 _HAL_VPU_Entry();
1781 //Check FW buffer size
1782 if (1 == u8Offset)
1783 {
1784 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1785 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1786
1787 if (u32CurFWBuffSize < u32MinFWBuffSize)
1788 {
1789 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1790 _HAL_VPU_Release();
1791 return FALSE;
1792 }
1793 }
1794
1795 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1796 &&(E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[0].eDecodertype)
1797 &&(E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[1].eDecodertype))
1798 {
1799 pVPUCtx->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1800 }
1801
1802 #ifdef VDEC3
1803 pVPUCtx->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1804 #endif
1805
1806 if (0 == pVPUCtx->u8TaskCnt)
1807 {
1808 //No task is created, need to load f/w, etc.
1809 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUCtx->u8TaskCnt);
1810
1811 if (!_VPU_EX_InitAll(u32Id, pInitPara))
1812 {
1813 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1814 _HAL_VPU_Release();
1815 return FALSE;
1816 }
1817
1818 //Check if controller finish initialization: clear mailbox, etc.
1819 //Need to check it before sending any controller commands!
1820 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1821 while (CTL_STU_NONE == ctl_ptr->statue)
1822 {
1823 if (HVD_GetSysTime_ms() > u32Timeout)
1824 {
1825 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1826 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1827 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1828 MS_U32 t=0;
1829 for (t=0; t<30; t++)
1830 {
1831 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt(u32Id));
1832 }
1833 _HAL_VPU_Release();
1834 return FALSE;
1835 }
1836
1837 MsOS_ReadMemory();
1838 }
1839
1840 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1841 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1842
1843 }
1844 else
1845 {
1846 if (pVPUHalContext->_bVPUSingleMode)
1847 {
1848 //Show error message
1849 VPRINTF("This task will use dram instead of sram!!!\n");
1850 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1851 }
1852
1853 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1854 {
1855 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1856 _HAL_VPU_Release();
1857 return FALSE;
1858 }
1859 if (pInitPara->pVLCCfg)
1860 {
1861 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1862 {
1863 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1864 _HAL_VPU_Release();
1865 return FALSE;
1866 }
1867 }
1868 }
1869
1870
1871 #ifdef VDEC3
1872 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1873 {
1874 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1875
1876 memset(pTemp4,0,sizeof(VDEC_VBBU));
1877
1878 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1879
1880 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1881
1882 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1883
1884 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*0x100000);
1885
1886 memset(pTemp2,0,sizeof(CMD_QUEUE));
1887
1888 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1889
1890 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1891
1892 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1893
1894 memset(pTemp3,0,0x2000);
1895
1896 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1897
1898 memset((void*)pVersion,0,0x8);
1899
1900 *pVersion = 1; //0:diu, 1:wb
1901 }
1902
1903 #endif
1904
1905 #if 1 // For TEE
1906 #ifdef VDEC3
1907 #if SUPPORT_G2VP9
1908 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1909 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1910 #else
1911 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1912 #endif
1913 #else
1914 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1915 #endif
1916 {
1917 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1918
1919 if (pVPUCtx->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1920 {
1921 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1922 }
1923 else
1924 {
1925 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUCtx->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1926 }
1927
1928 MsOS_FlushMemory();
1929 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1930
1931 ///VPRINTF("DRV side, share info offset = 0x%lx\n", pVPUCtx->u32FWShareInfoAddr[u8Offset]);
1932 ///VPRINTF("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1933 }
1934 #endif
1935
1936 if ((pVPUCtx->bEnableDymanicFBMode == TRUE) && (pVPUCtx->u8TaskCnt == 0))
1937 {
1938 ctl_ptr->FB_ADDRESS = pVPUCtx->u32DynamicFBAddress;
1939 ctl_ptr->FB_Total_SIZE = pVPUCtx->u32DynamicFBSize;
1940
1941 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1942
1943 MsOS_FlushMemory();
1944 }
1945
1946 if(pVPUCtx->_stVPUSTCMode[u8Offset].bSTCSetMode == 1)
1947 {
1948 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, u32CmdArg);
1949 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1950 {
1951 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1952 }
1953 }
1954
1955 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUCtx->_stVPUDecMode.u8DecMod))
1956 {
1957 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1958 //arg=1 to get better performance for single task
1959 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1960 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1961 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1962 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1963 {
1964 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1965 }
1966 }
1967 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUCtx->_stVPUDecMode.u8DecMod)
1968 {
1969 if (pVPUCtx->_stVPUDecMode.u8CodecType[0] != pVPUCtx->_stVPUDecMode.u8CodecType[1])
1970 {
1971 switch (pVPUCtx->_stVPUDecMode.u32Arg)
1972 {
1973 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1974 u32CmdArg = CTL_MODE_3DTV;
1975 break;
1976 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1977 u32CmdArg = CTL_MODE_3DTV_PROG;
1978 break;
1979 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1980 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1981 break;
1982 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1983 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1984 break;
1985 default:
1986 u32CmdArg = CTL_MODE_3DTV;
1987 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUCtx->_stVPUDecMode.u32Arg);
1988 break;
1989 }
1990 }
1991 else
1992 {
1993 u32CmdArg = CTL_MODE_3DWMV;
1994 }
1995 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1996 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1997 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1998 {
1999 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
2000 }
2001 }
2002 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUCtx->_stVPUDecMode.u8DecMod)
2003 {
2004 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUCtx->_stVPUDecMode.u32Arg)
2005 {
2006 u32CmdArg = CTL_MODE_ONE_STC;
2007 }
2008 else
2009 {
2010 u32CmdArg = (pVPUCtx->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
2011 }
2012 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
2013 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
2014 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
2015 {
2016 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
2017 }
2018 }
2019
2020 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
2021 #if defined(SUPPORT_NEW_MEM_LAYOUT)
2022 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2023 #ifdef VDEC3
2024 {
2025 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2026 }
2027 #else
2028 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
2029 #endif
2030
2031 #ifdef VDEC3
2032 #if SUPPORT_G2VP9
2033 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2034 #else
2035 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2036 #endif
2037 {
2038 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2039 }
2040 #else
2041 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2042 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
2043 #endif
2044 else
2045 {
2046 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2047 _HAL_VPU_Release();
2048 return FALSE;
2049 }
2050 #else
2051 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
2052 #endif
2053 VPRINTF("[%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
2054
2055 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
2056
2057 MsOS_ReadMemory();
2058 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2059 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2060
2061 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2062 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
2063 {
2064 if (HVD_GetSysTime_ms() > u32Timeout)
2065 {
2066 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
2067 MS_U32 t=0;
2068 for (t=0; t<30; t++)
2069 {
2070 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt(u32Id));
2071 }
2072 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2073 pVPUCtx->bVpuExLoadFWRlt = FALSE; ///error handling
2074 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
2075 _HAL_VPU_Release();
2076 return FALSE;
2077 //#endif
2078 }
2079
2080 MsOS_ReadMemory();
2081 }
2082
2083 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2084 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2085
2086 #ifdef VDEC3
2087 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2088 #else
2089 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2090 #endif
2091 {
2092 HAL_HVD_EX_SetBufferAddr(u32Id);
2093 }
2094
2095 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
2096 {
2097 eDecType = E_VPU_EX_DECODER_MVD;
2098 }
2099 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
2100 {
2101 eDecType = E_VPU_EX_DECODER_HVD;
2102 }
2103 #ifdef VDEC3
2104 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
2105 {
2106 eDecType = E_VPU_EX_DECODER_EVD;
2107 }
2108 #if SUPPORT_G2VP9
2109 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
2110 {
2111 eDecType = E_VPU_EX_DECODER_G2VP9;
2112 }
2113 #endif
2114 #endif
2115 else
2116 {
2117 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
2118 _HAL_VPU_Release();
2119 return FALSE;
2120 }
2121
2122 #ifdef VDEC3
2123 if ((bFWdecideFB == TRUE) && (pVPUCtx->u8TaskCnt == 0))
2124 {
2125 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
2126 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
2127 }
2128 #endif
2129
2130 if (pTaskInfo->eDecType != eDecType)
2131 {
2132 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
2133 pTaskInfo->eDecType, eDecType);
2134 }
2135 goto _SAVE_DEC_TYPE;
2136
2137 _SAVE_DEC_TYPE:
2138 if (pVPUCtx->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
2139 {
2140 pVPUCtx->_stVPUStream[u8Offset].eDecodertype = eDecType;
2141 }
2142 else
2143 {
2144 VPU_MSG_ERR("Cannot save eDecType!!\n");
2145 }
2146
2147 (pVPUCtx->u8TaskCnt)++;
2148 _HAL_VPU_Release();
2149 return TRUE;
2150 }
2151
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)2152 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
2153 {
2154 HVD_Return eRet;
2155 #ifdef VDEC3
2156 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2157 #else
2158 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2159 #endif
2160 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2161 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
2162
2163 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2164
2165 _HAL_VPU_Entry();
2166 VPU_MSG_DBG("DecType=%d\n", pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype);
2167
2168 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2169 if(eRet != E_HVD_RETURN_SUCCESS)
2170 {
2171 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2172 }
2173
2174 {
2175 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2176 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2177 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2178
2179 MsOS_ReadMemory();
2180
2181 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2182 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2183
2184 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2185 {
2186 if (HVD_GetSysTime_ms() > u32Timeout)
2187 {
2188 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2189 pVPUCtx->bVpuExLoadFWRlt = FALSE; ///error handling
2190 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2191
2192 if (pVPUCtx->u8TaskCnt == 1)
2193 {
2194 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2195 break;
2196 }
2197 else if (pVPUCtx->u8TaskCnt == 2)
2198 {
2199 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2200 _HAL_VPU_Release();
2201 return FALSE;
2202 }
2203 else
2204 {
2205 VPU_MSG_ERR("Task number is not correct\n");
2206 _HAL_VPU_Release();
2207 return FALSE;
2208 }
2209 }
2210
2211 MsOS_ReadMemory();
2212 }
2213
2214 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2215 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2216 }
2217
2218 #if SUPPORT_EVD
2219 if (pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2220 {
2221 HAL_EVD_EX_ClearTSPInput(u32Id);
2222 }
2223 #endif
2224
2225 pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2226 if ((u8OffsetIdx == 0) && (pVPUCtx->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2227 {
2228 pVPUCtx->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2229 pVPUCtx->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2230 pVPUCtx->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2231 }
2232
2233 if (pVPUCtx->u8TaskCnt)
2234 {
2235 (pVPUCtx->u8TaskCnt)--;
2236 }
2237 else
2238 {
2239 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2240 }
2241
2242 if (0 == pVPUCtx->u8TaskCnt)
2243 {
2244 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUCtx->u8TaskCnt);
2245 _VPU_EX_DeinitAll(u32Id, pInitPara);
2246
2247 MS_U8 i = 0;
2248
2249 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2250 {
2251 pVPUCtx->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2252 }
2253
2254 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2255 {
2256 if (i == u8OffsetIdx) continue;
2257 else if (pVPUHalContext->u8Cidx[i] != 0xFF) break;
2258 }
2259
2260 if (i == MAX_SUPPORT_DECODER_NUM) //bOneVPURunning
2261 {
2262 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2263 pVPUHalContext->u32VPUSHMAddr = 0;
2264 }
2265 }
2266 else
2267 {
2268 pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2269 _VPU_EX_DeinitHW(u32Id, pInitPara->pTaskInfo);
2270 }
2271
2272 pVPUHalContext->u8Cidx[u8OffsetIdx] = 0xFF;
2273 _HAL_VPU_Release();
2274 return TRUE;
2275 }
2276
HAL_VPU_EX_LoadCode(MS_U32 u32Id,VPU_EX_FWCodeCfg * pFWCodeCfg)2277 MS_BOOL HAL_VPU_EX_LoadCode(MS_U32 u32Id, VPU_EX_FWCodeCfg *pFWCodeCfg)
2278 {
2279 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2280 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2281 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2282 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2283 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2284 #endif
2285 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2286 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
2287
2288 if (FALSE == HAL_VPU_EX_GetFWReload(u32Id))
2289 {
2290 //VPRINTF("%s bFWReload FALSE!!!\n", __FUNCTION__);
2291 if (FALSE == pVPUCtx->bVpuExLoadFWRlt)
2292 {
2293 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2294 }
2295 else
2296 {
2297 //Check f/w prefix "VDEC30"
2298 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2299 {
2300 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2301 }
2302 else
2303 {
2304 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2305 return TRUE;
2306 }
2307 }
2308 }
2309
2310 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2311 {
2312 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2313 if (u32Size != 0)
2314 {
2315 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2316
2317
2318 MS_U32 u32Start;
2319 MS_U32 u32StartOffset;
2320 MS_U8 u8MiuSel;
2321
2322 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2323
2324
2325 if(u8MiuSel == E_CHIP_MIU_0)
2326 cpyflag = E_SPIDMA_DEV_MIU0;
2327 else if(u8MiuSel == E_CHIP_MIU_1)
2328 cpyflag = E_SPIDMA_DEV_MIU1;
2329 else if(u8MiuSel == E_CHIP_MIU_2)
2330 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2331
2332 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2333 {
2334 goto _load_code_fail;
2335 }
2336 }
2337 else
2338 {
2339 goto _load_code_fail;
2340 }
2341 #else
2342 goto _load_code_fail;
2343 #endif
2344 }
2345 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2346 {
2347 if (u32BinAddr != 0 && u32Size != 0)
2348 {
2349 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2350 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2351 {
2352 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2353 {
2354 VPU_MSG_INFO("Decompress ok!!!\n");
2355 }
2356 else
2357 {
2358 VPU_MSG_INFO("Decompress fail!!!\n");
2359 }
2360 }
2361 else
2362 #endif
2363 {
2364 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2365 }
2366 }
2367 else
2368 {
2369 goto _load_code_fail;
2370 }
2371 }
2372 else
2373 {
2374 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2375 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2376 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2377 (MS_U32) sizeof(u8HVD_FW_Binary));
2378
2379 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2380 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2381 {
2382 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2383 {
2384 VPU_MSG_INFO("Decompress ok!!!\n");
2385 }
2386 else
2387 {
2388 VPU_MSG_INFO("Decompress fail!!!\n");
2389 }
2390 }
2391 else
2392 #endif
2393 {
2394 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2395 }
2396 #else
2397 goto _load_code_fail;
2398 #endif
2399 }
2400
2401 MAsm_CPU_Sync();
2402 MsOS_FlushMemory();
2403
2404 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2405 {
2406 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2407 goto _load_code_fail;
2408 }
2409
2410 pVPUCtx->bVpuExLoadFWRlt = TRUE;
2411 return TRUE;
2412
2413 _load_code_fail:
2414 pVPUCtx->bVpuExLoadFWRlt = FALSE;
2415 return FALSE;
2416 }
2417
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2418 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2419 {
2420 u32VPURegOSBase = u32RegBase;
2421 }
2422
HAL_VPU_EX_Init_Share_Mem(void)2423 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2424 {
2425 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2426
2427 MS_U32 u32ShmId;
2428 MS_VIRT u32Addr;
2429 MS_U32 u32BufSize;
2430
2431
2432 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2433 sizeof(VPU_Hal_CTX),
2434 &u32ShmId,
2435 &u32Addr,
2436 &u32BufSize,
2437 MSOS_SHM_QUERY))
2438 {
2439 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2440 sizeof(VPU_Hal_CTX),
2441 &u32ShmId,
2442 &u32Addr,
2443 &u32BufSize,
2444 MSOS_SHM_CREATE))
2445 {
2446 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2447 if(pVPUHalContext == NULL)
2448 {
2449 pVPUHalContext = &gVPUHalContext;
2450 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2451 _VPU_EX_Context_Init();
2452 VPRINTF("[%s]Global structure init Success!!!\n",__FUNCTION__);
2453 }
2454 else
2455 {
2456 VPRINTF("[%s]Global structure exists!!!\n",__FUNCTION__);
2457 }
2458 //return FALSE;
2459 }
2460 else
2461 {
2462 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2463 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2464 _VPU_EX_Context_Init();
2465 }
2466 }
2467 else
2468 {
2469 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2470 }
2471 #else
2472 if(pVPUHalContext == NULL)
2473 {
2474 pVPUHalContext = &gVPUHalContext;
2475 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2476 _VPU_EX_Context_Init();
2477 }
2478 #endif
2479
2480 return TRUE;
2481
2482 }
2483
2484 #ifdef VDEC3
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)2485 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
2486 #else
2487 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType, MS_BOOL bIsEVD)
2488 #endif
2489 {
2490 MS_U32 i = 0;
2491 MS_U8 idx = 0;
2492 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2493 {
2494 idx = 0;
2495 }
2496 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2497 {
2498 idx = 0;
2499 }
2500 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2501 {
2502 idx = 1;
2503 }
2504 #ifdef VDEC3
2505 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2506 {
2507 idx = eStreamType - E_HAL_VPU_N_STREAM;
2508 }
2509 #endif
2510
2511 #ifdef VDEC3
2512 MS_U8 u8DecideCidx = _VPU_EX_DecideCidx(idx, bIsEVD, bIsNStreamMode);
2513 #else
2514 MS_U8 u8DecideCidx = _VPU_EX_DecideCidx(idx, bIsEVD);
2515 #endif
2516 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[u8DecideCidx];
2517
2518 _HAL_VPU_MutexCreate();
2519
2520 _HAL_VPU_Entry();
2521
2522 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2523 {
2524 if((E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[1].eDecodertype))
2525 {
2526 pVPUCtx->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2527 pVPUCtx->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2528 pVPUCtx->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2529 _HAL_VPU_Release();
2530 return pVPUCtx->_stVPUStream[0].eStreamId; /// Need to check
2531 }
2532 }
2533 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2534 {
2535 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2536 {
2537 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUCtx->_stVPUStream[i].eStreamId)
2538 && (E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[i].eDecodertype))
2539 {
2540 pVPUCtx->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2541 _HAL_VPU_Release();
2542 return pVPUCtx->_stVPUStream[i].eStreamId;
2543 }
2544 }
2545 }
2546 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2547 {
2548 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2549 {
2550 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUCtx->_stVPUStream[i].eStreamId)
2551 && (E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[i].eDecodertype))
2552 {
2553 pVPUCtx->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2554 _HAL_VPU_Release();
2555 return pVPUCtx->_stVPUStream[i].eStreamId;
2556 }
2557 }
2558 }
2559 #ifdef VDEC3
2560 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2561 {
2562 #if 1 // bound FW task to main/sub stream
2563 i = eStreamType - E_HAL_VPU_N_STREAM;
2564
2565 if (pVPUCtx->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2566 {
2567 pVPUCtx->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2568 _HAL_VPU_Release();
2569 return pVPUCtx->_stVPUStream[i].eStreamId;
2570 }
2571 #else // dynamic select FW task id
2572 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2573 {
2574 if ((E_HAL_VPU_N_STREAM_BASE & pVPUCtx->_stVPUStream[i].eStreamId)
2575 && (E_VPU_EX_DECODER_NONE == pVPUCtx->_stVPUStream[i].eDecodertype))
2576 {
2577 return pVPUCtx->_stVPUStream[i].eStreamId;
2578 }
2579 }
2580 #endif
2581 }
2582 #endif
2583
2584 _HAL_VPU_Release();
2585
2586 return E_HAL_VPU_STREAM_NONE;
2587 }
2588
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2589 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2590 {
2591 if(u8Idx > 2)
2592 {
2593 return FALSE;
2594 }
2595
2596 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8Idx]];
2597
2598 _HAL_VPU_Entry();
2599
2600 if (pVPUCtx->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2601 {
2602 pVPUCtx->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2603 pVPUCtx->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2604 }
2605 else if (pVPUCtx->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2606 {
2607 pVPUCtx->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2608 }
2609
2610 _HAL_VPU_Release();
2611
2612 return TRUE;
2613 }
2614
HAL_VPU_EX_CheckFreeStream(void)2615 MS_U8 HAL_VPU_EX_CheckFreeStream(void)
2616 {
2617 MS_U8 u8Idx = 0;
2618 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8Idx]];
2619
2620 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2621 {
2622 if (pVPUCtx->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2623 break;
2624 }
2625
2626 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2627 {
2628 VPU_MSG_ERR("all vpu free streams are occupied \n");
2629 return -1;
2630 }
2631
2632 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2633 return u8Idx;
2634 }
2635
HAL_VPU_EX_Init(MS_U32 u32Id,VPU_EX_InitParam * InitParams)2636 MS_BOOL HAL_VPU_EX_Init(MS_U32 u32Id, VPU_EX_InitParam *InitParams)
2637 {
2638 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2639 VPU_MSG_DBG("u8OffsetIdx=%d, Inv=%d, clk=%d\n", u8OffsetIdx,InitParams->bClockInv, InitParams->eClockSpeed);
2640
2641 _VPU_EX_ClockInv(InitParams->bClockInv);
2642 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2643 HAL_VPU_EX_PowerCtrl(u32Id, TRUE);
2644 // enable module
2645 #ifdef CONFIG_MSTAR_CLKM
2646 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
2647 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2648 VPU_Unit_Ctx *pAnotherVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[1-u8OffsetIdx]];
2649 if (pAnotherVPUCtx->_bVPUPowered == FALSE)
2650 {
2651 if(u8VPU == VPU_EVDR2)
2652 {
2653 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2654 }
2655 else
2656 {
2657 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5_LITE, TRUE);
2658 }
2659 pVPUCtx->_bVPUPowered = TRUE;
2660 }
2661 #endif
2662
2663 #ifdef CONFIG_MSTAR_SRAMPD
2664 if(pVPUHalContext->u8Cidx[u8OffsetIdx] == VPU_EVDR2)
2665 {
2666 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2667 HVD_Delay_ms(1);
2668 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2669 HVD_Delay_ms(1);
2670 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2671 HVD_Delay_ms(1);
2672 }
2673 else
2674 {
2675 _VPU_WriteWordMask(REG_HICODEC_LITE_SRAM_SD_EN, HICODEC_LITE_SRAM_HICODEC1, HICODEC_LITE_SRAM_HICODEC1);
2676 HVD_Delay_ms(1);
2677 }
2678 #endif
2679
2680
2681 #if 1 //Create VPU's own mutex
2682 //_HAL_VPU_MutexCreate();
2683 #else
2684 pVPUCtx->s32VPUMutexID = InitParams->s32VPUMutexID;
2685 pVPUCtx->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2686 #endif
2687
2688 return TRUE;
2689 }
2690
HAL_VPU_EX_DeInit(MS_U32 u32Id)2691 MS_BOOL HAL_VPU_EX_DeInit(MS_U32 u32Id)
2692 {
2693 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2694 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
2695
2696 if (0 != _VPU_EX_GetActiveCodecCnt(u32Id))
2697 {
2698 VPU_MSG_DBG("do nothing since codec is active.\n");
2699 return TRUE;
2700 }
2701 memset(&(pVPUCtx->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2702 #ifdef CONFIG_MSTAR_CLKM
2703 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2704 VPU_Unit_Ctx *pAnotherVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[1-u8OffsetIdx]];
2705 if (pAnotherVPUCtx->_bVPUPowered == FALSE)
2706 {
2707 if(u8VPU == VPU_EVDR2)
2708 {
2709 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2710 }
2711 else
2712 {
2713 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5_LITE, FALSE);
2714 }
2715 pVPUCtx->_bVPUPowered = FALSE;
2716 }
2717 #else
2718 HAL_VPU_EX_PowerCtrl(u32Id, FALSE);
2719 #endif
2720
2721 #ifdef CONFIG_MSTAR_SRAMPD
2722 if(pVPUHalContext->u8Cidx[u8OffsetIdx] == VPU_EVDR2)
2723 {
2724 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2725 HVD_Delay_ms(1);
2726 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2727 HVD_Delay_ms(1);
2728 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2729 HVD_Delay_ms(1);
2730 }
2731 else
2732 {
2733 _VPU_WriteWordMask(REG_HICODEC_LITE_SRAM_SD_EN, ~HICODEC_LITE_SRAM_HICODEC1, HICODEC_LITE_SRAM_HICODEC1);
2734 HVD_Delay_ms(1);
2735 }
2736 #endif
2737
2738 HAL_VPU_EX_SwRelseMAU(u32Id);
2739 //_HAL_VPU_MutexDelete();
2740
2741 return TRUE;
2742 }
2743
_VPU_EX_GetVPUPoweredCnt(void)2744 static MS_U8 _VPU_EX_GetVPUPoweredCnt(void)
2745 {
2746 MS_U8 j;
2747 MS_U8 u8VPUPoweredCnt = 0;
2748 VPU_Unit_Ctx *pVPUCtx = NULL;
2749
2750 for (j = 0; j < MAX_VPU_NUM; j++)
2751 {
2752 pVPUCtx = &pVPUHalContext->_stCtx[j];
2753
2754 if (pVPUCtx->_bVPUPowered == TRUE)
2755 {
2756 u8VPUPoweredCnt++;
2757 }
2758 }
2759
2760 return u8VPUPoweredCnt;
2761 }
2762
HAL_VPU_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)2763 void HAL_VPU_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
2764 {
2765 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2766 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2767 //MS_U16 u16Value = (u8VPU==VPU_EVDR2_LITE)?(VPU_LITE_ICG_EN):(VPU_ICG_EN);
2768 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[u8VPU];
2769 MS_U8 u8VPUPoweredCnt = _VPU_EX_GetVPUPoweredCnt();
2770
2771 if (bEnable)
2772 {
2773 if (u8VPUPoweredCnt == 0)
2774 {
2775 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2776 }
2777
2778 //_VPU_WriteWordMask(REG_TOP_VPU, u16Value, u16Value);
2779 pVPUCtx->_bVPUPowered = TRUE;
2780 }
2781 else
2782 {
2783 if (u8VPUPoweredCnt == 1)
2784 {
2785 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2786 }
2787
2788 //_VPU_WriteWordMask(REG_TOP_VPU, ~(u16Value), u16Value);
2789 pVPUCtx->_bVPUPowered = FALSE;
2790 }
2791 }
2792
HAL_VPU_EX_MIU_RW_Protect(MS_U32 u32Id,MS_BOOL bEnable)2793 void HAL_VPU_EX_MIU_RW_Protect(MS_U32 u32Id, MS_BOOL bEnable)
2794 {
2795 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2796 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2797
2798 _VPU_MIU_SetReqMask(u8VPU, VPU_D_RW, bEnable);
2799 _VPU_MIU_SetReqMask(u8VPU, VPU_Q_RW, bEnable);
2800 _VPU_MIU_SetReqMask(u8VPU, VPU_I_R, bEnable);
2801 VPU_EX_TimerDelayMS(1);
2802 }
2803
2804 ///-----------------------------------------------------------------------------
2805 /// config AVCH264 CPU
2806 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2807 /// @param u8dlend_en \b IN: endian
2808 /// - 1, little endian
2809 /// - 0, big endian
2810 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_U32 u32Id,MS_PHY u32StAddr)2811 MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32Id, MS_PHY u32StAddr)
2812 {
2813 MS_BOOL bRet = TRUE;
2814 MS_U32 u32Offset = 0;
2815 MS_U16 tempreg = 0;
2816 MS_U8 u8MiuSel;
2817 //MS_U32 u32TmpStartOffset;
2818
2819 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2820 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2821
2822 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2823
2824 _VPU_Write2Byte(VPU_REG_SPI_BASE(u8VPU), 0xC000);
2825 _VPU_WriteWordMask(VPU_REG_CPU_SETTING(u8VPU), 0, VPU_REG_CPU_SPI_BOOT );
2826 _VPU_WriteWordMask(VPU_REG_CPU_SETTING(u8VPU), 0, VPU_REG_CPU_SDRAM_BOOT );
2827 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L(u8VPU), 0xc000);
2828 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H(u8VPU), 0xffff);
2829 _VPU_Write2Byte(VPU_REG_IO1_BASE(u8VPU), 0xf900); // UART BASE
2830 _VPU_Write2Byte(VPU_REG_IO2_BASE(u8VPU), 0xf000);
2831 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L(u8VPU), 0x0000);
2832 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H(u8VPU), 0xf200);
2833
2834 #if (HVD_ENABLE_IQMEM)
2835 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L(u8VPU), (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2836 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H(u8VPU), (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2837 #endif
2838
2839 #if (VPU_FORCE_MIU_MODE)
2840 // Data sram base Unit: byte address
2841 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L(u8VPU), (MS_U16)(u32Offset & 0x0000ffff)) ;
2842 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H(u8VPU), (MS_U16)((u32Offset >>16) & 0xffff));
2843 // Instruction sram base Unit: byte address
2844 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L(u8VPU), (MS_U16)(u32Offset & 0x0000ffff)) ;
2845 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H(u8VPU), (MS_U16)((u32Offset >>16) & 0xffff));
2846
2847 #ifndef HAL_FEATURE_MAU
2848 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE(u8VPU)) & 0xfff);
2849 #endif
2850 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2851
2852 //use force miu mode
2853 if(u8MiuSel == E_CHIP_MIU_0)
2854 {
2855 #ifdef HAL_FEATURE_MAU
2856 _VPU_Write2Byte(MAU1_MIU_SEL(u8VPU), 0x8900);
2857 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL(u8VPU), 0x8900);
2858 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL(u8VPU), 0x8900);
2859 #else
2860 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE(u8VPU), r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2861 #endif
2862 }
2863 else //if(u8MiuSel == E_CHIP_MIU_1)
2864 {
2865 #ifdef HAL_FEATURE_MAU
2866 _VPU_Write2Byte(MAU1_MIU_SEL(u8VPU), 0x8900);
2867 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL(u8VPU), 0x8b00);
2868 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL(u8VPU), 0x8900);
2869 #else
2870 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE(u8VPU), r2_miu_sel|0x5000);
2871 #endif
2872 }
2873 #if 0
2874 else //miu 2
2875 {
2876 #ifdef HAL_FEATURE_MAU
2877 _VPU_Write2Byte(MAU1_MIU_SEL(u8VPU), 0x8b00);
2878 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL(u8VPU), 0x8900);
2879 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL(u8VPU), 0x8900);
2880 #else
2881 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE(u8VPU), r2_miu_sel|0xa000);
2882 #endif
2883 }
2884 #endif
2885 #else
2886 ///TODO:
2887 #endif
2888
2889 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET(u8VPU));
2890 tempreg |= VPU_REG_IO2_EN;
2891 tempreg |= VPU_REG_QMEM_SPACE_EN;
2892 _VPU_Write2Byte(VPU_REG_CONTROL_SET(u8VPU), tempreg);
2893
2894 return bRet;
2895 }
2896
2897 ///-----------------------------------------------------------------------------
2898 /// Set IQMem data access mode or instruction fetch mode
2899 /// @param u8dlend_en \b IN: endian
2900 /// - 1, switch to data access mode
2901 /// - 0, switch to instruction fetch mode
2902 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_U32 u32Id,MS_BOOL bEnable)2903 void HAL_VPU_EX_IQMemSetDAMode(MS_U32 u32Id, MS_BOOL bEnable)
2904 {
2905 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2906 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2907
2908 if (bEnable)
2909 {
2910 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING(u8VPU), _VPU_Read2Byte(VPU_REG_IQMEM_SETTING(u8VPU))|0x10);
2911 _VPU_Write2Byte(VPU_REG_QMEM_OWNER(u8VPU), _VPU_Read2Byte(VPU_REG_QMEM_OWNER(u8VPU))&0xFFDE);
2912 }
2913 else
2914 {
2915 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING(u8VPU), _VPU_Read2Byte(VPU_REG_IQMEM_SETTING(u8VPU))& 0xFFEF);
2916 }
2917 }
2918
2919 ///-----------------------------------------------------------------------------
2920 /// H.264 SW reset
2921 /// @return TRUE or FALSE
2922 /// - TRUE, Success
2923 /// - FALSE, Failed
2924 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_U32 u32Id,MS_BOOL bCheckMauIdle)2925 MS_BOOL HAL_VPU_EX_SwRst(MS_U32 u32Id, MS_BOOL bCheckMauIdle)
2926 {
2927 MS_U16 tempreg = 0, tempreg1 = 0;
2928 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2929 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
2930 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[u8VPU];
2931
2932 #ifndef HAL_FEATURE_MAU
2933 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG(u8VPU));
2934 tempreg |= VPU_REG_CPU_STALL_EN;
2935 _VPU_Write2Byte(VPU_REG_CPU_CONFIG(u8VPU), tempreg);
2936
2937 MS_U32 idle_cnt = 100;// ms
2938 while (idle_cnt)
2939 {
2940 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS(u8VPU)) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2941 {
2942 break;
2943 }
2944 idle_cnt--;
2945 MsOS_DelayTask(1);
2946 }
2947
2948 if (idle_cnt == 0)
2949 {
2950 VPRINTF("ISB ICU idle time out~~~~~\n");
2951 }
2952
2953 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL(u8VPU));
2954 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2955 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2956 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL(u8VPU), tempreg1);
2957
2958 MS_U32 idle_cnt_1 = 100;// ms
2959 while (idle_cnt_1)
2960 {
2961 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS(u8VPU)) & (VPU_REG_BIU_EMPTY))
2962 {
2963 break;
2964 }
2965 idle_cnt_1--;
2966 MsOS_DelayTask(1);
2967 }
2968
2969 if (idle_cnt_1 == 0)
2970 {
2971 VPRINTF("BIU DCU idle time out~~~~~\n");
2972 }
2973
2974 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING(u8VPU));
2975 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2976 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
2977 VPU_EX_TimerDelayMS(1);
2978 tempreg &= ~VPU_REG_CPU_R2_EN;
2979 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2980 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
2981
2982 #else
2983 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2984
2985 if (bCheckMauIdle)
2986 {
2987 MS_U32 mau_idle_cnt = 100;// ms
2988 while (mau_idle_cnt)
2989 {
2990 if (TRUE == _VPU_EX_MAU_IDLE(u32Id))
2991 {
2992 break;
2993 }
2994 mau_idle_cnt--;
2995 MsOS_DelayTask(1);
2996 }
2997
2998 if (mau_idle_cnt == 0)
2999 {
3000 VPRINTF("MAU idle time out~~~~~\n");
3001 }
3002 }
3003
3004
3005 HAL_VPU_EX_MIU_RW_Protect(u32Id, TRUE);
3006
3007 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST(u8VPU));
3008 tempreg1 |= MAU1_REG_SW_RESET;
3009 _VPU_Write2Byte(MAU1_CPU_RST(u8VPU), tempreg1);
3010
3011 #if defined(UDMA_FPGA_ENVI)
3012 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
3013 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
3014 #endif
3015
3016 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING(u8VPU));
3017 tempreg &= ~VPU_REG_CPU_R2_EN;
3018 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
3019 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
3020 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
3021 #endif
3022
3023 VPU_EX_TimerDelayMS(1);
3024 HAL_VPU_EX_MIU_RW_Protect(u32Id, FALSE);
3025
3026 pVPUCtx->_bVPURsted = FALSE;
3027 return TRUE;
3028 }
3029
3030 ///-----------------------------------------------------------------------------
3031 /// CPU reset release
3032 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(MS_U32 u32Id)3033 void HAL_VPU_EX_SwRstRelse(MS_U32 u32Id)
3034 {
3035 MS_U16 tempreg = 0;
3036 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3037 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3038 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[u8VPU];
3039
3040 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG(u8VPU));
3041 tempreg &= ~VPU_REG_CPU_STALL_EN;
3042 _VPU_Write2Byte(VPU_REG_CPU_CONFIG(u8VPU), tempreg);
3043
3044 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING(u8VPU));
3045 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
3046 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
3047 VPU_EX_TimerDelayMS(1);
3048 tempreg |= VPU_REG_CPU_SW_RSTZ;
3049 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
3050 VPU_EX_TimerDelayMS(1);
3051 tempreg |= VPU_REG_CPU_R2_EN;
3052 _VPU_Write2Byte(VPU_REG_CPU_SETTING(u8VPU), tempreg);
3053
3054 #ifdef HAL_FEATURE_MAU
3055 MS_U16 tempreg1 = 0;
3056 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST(u8VPU));
3057 tempreg1 &= ~MAU1_REG_SW_RESET;
3058 _VPU_Write2Byte(MAU1_CPU_RST(u8VPU), tempreg1);
3059 #endif
3060
3061 pVPUCtx->_bVPURsted = TRUE;
3062 }
3063
HAL_VPU_EX_SwRelseMAU(MS_U32 u32Id)3064 void HAL_VPU_EX_SwRelseMAU(MS_U32 u32Id)
3065 {
3066 #ifdef HAL_FEATURE_MAU
3067 MS_U16 tempreg = 0;
3068 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3069 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3070
3071 tempreg = _VPU_Read2Byte(MAU1_CPU_RST(u8VPU));
3072 tempreg &= ~MAU1_REG_SW_RESET;
3073 _VPU_Write2Byte(MAU1_CPU_RST(u8VPU), tempreg);
3074 #endif
3075 }
3076
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)3077 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
3078 {
3079 MS_U32 u32value = 0;
3080
3081 return u32value;
3082 }
3083
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)3084 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
3085 {
3086 MS_BOOL bRet = TRUE;
3087
3088 return bRet;
3089 }
3090
3091 ///-----------------------------------------------------------------------------
3092 /// Check AVCH264 Ready or not
3093 /// @return TRUE or FALSE
3094 /// - TRUE, MailBox is free
3095 /// - FALSE, MailBox is busy
3096 /// @param u8MBox \b IN: MailBox to check
3097 /// - AVCH264_HI_MBOX0,
3098 /// - AVCH264_HI_MBOX1,
3099 /// - AVCH264_RISC_MBOX0,
3100 /// - AVCH264_RISC_MBOX1,
3101 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32Id,MS_U32 u32type)3102 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32Id, MS_U32 u32type)
3103 {
3104 MS_BOOL bResult = FALSE;
3105 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3106 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3107
3108 switch (u32type)
3109 {
3110 case VPU_HI_MBOX0:
3111 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY(u8VPU)) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
3112 break;
3113 case VPU_HI_MBOX1:
3114 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY(u8VPU)) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
3115 break;
3116 case VPU_RISC_MBOX0:
3117 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY(u8VPU)) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
3118 break;
3119 case VPU_RISC_MBOX1:
3120 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY(u8VPU)) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
3121 break;
3122 default:
3123 break;
3124 }
3125 return bResult;
3126 }
3127
3128
3129 ///-----------------------------------------------------------------------------
3130 /// Read message from AVCH264
3131 /// @return TRUE or FALSE
3132 /// - TRUE, success
3133 /// - FALSE, failed
3134 /// @param u8MBox \b IN: MailBox to read
3135 /// - AVCH264_RISC_MBOX0
3136 /// - AVCH264_RISC_MBOX1
3137 /// @param u32Msg \b OUT: message read
3138 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32Id,MS_U32 u32type,MS_U32 * u32Msg)3139 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32Id, MS_U32 u32type, MS_U32 * u32Msg)
3140 {
3141 MS_BOOL bResult = TRUE;
3142 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3143 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3144
3145 switch (u32type)
3146 {
3147 case VPU_HI_MBOX0:
3148 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H(u8VPU))) << 16) |
3149 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L(u8VPU))));
3150 break;
3151 case VPU_HI_MBOX1:
3152 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H(u8VPU))) << 16) |
3153 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L(u8VPU))));
3154 break;
3155 case VPU_RISC_MBOX0:
3156 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H(u8VPU))) << 16) |
3157 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L(u8VPU))));
3158 break;
3159 case VPU_RISC_MBOX1:
3160 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H(u8VPU))) << 16) |
3161 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L(u8VPU))));
3162 break;
3163 default:
3164 *u32Msg = 0;
3165 bResult = FALSE;
3166 break;
3167 }
3168 return bResult;
3169 }
3170
3171 ///-----------------------------------------------------------------------------
3172 /// Mailbox from AVCH264 clear bit resest
3173 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32Id,MS_U32 u32type)3174 void HAL_VPU_EX_MBoxClear(MS_U32 u32Id, MS_U32 u32type)
3175 {
3176 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3177 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3178
3179 switch (u32type)
3180 {
3181 case VPU_RISC_MBOX0:
3182 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR(u8VPU), VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3183 break;
3184 case VPU_RISC_MBOX1:
3185 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR(u8VPU), VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3186 break;
3187 default:
3188 break;
3189 }
3190 }
3191
3192 ///-----------------------------------------------------------------------------
3193 /// Send message to AVCH264
3194 /// @return TRUE or FALSE
3195 /// - TRUE, Success
3196 /// - FALSE, Failed
3197 /// @param u8MBox \b IN: MailBox
3198 /// - AVCH264_HI_MBOX0,
3199 /// - AVCH264_HI_MBOX1,
3200 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32Id,MS_U32 u32type,MS_U32 u32Msg)3201 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32Id, MS_U32 u32type, MS_U32 u32Msg)
3202 {
3203 MS_BOOL bResult = TRUE;
3204 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3205 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3206
3207 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3208
3209 switch (u32type)
3210 {
3211 case VPU_HI_MBOX0:
3212 {
3213 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L(u8VPU), u32Msg);
3214 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET(u8VPU), VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3215 break;
3216 }
3217 case VPU_HI_MBOX1:
3218 {
3219 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L(u8VPU), u32Msg);
3220 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET(u8VPU), VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3221 break;
3222 }
3223 default:
3224 {
3225 bResult = FALSE;
3226 break;
3227 }
3228 }
3229
3230 return bResult;
3231 }
3232
HAL_VPU_EX_GetProgCnt(MS_U32 u32Id)3233 MS_U32 HAL_VPU_EX_GetProgCnt(MS_U32 u32Id)
3234 {
3235 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3236 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3237 MS_U16 expc_l=0;
3238 MS_U16 expc_h=0;
3239 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L(u8VPU)) & 0xFFFF;
3240 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H(u8VPU)) & 0xFFFF;
3241 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3242 }
3243
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3244 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3245 {
3246 return _VPU_EX_GetOffsetIdx(u32Id);
3247 }
3248
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3249 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3250 {
3251 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3252 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3253
3254 if (u32ShmAddr == 0)
3255 {
3256 pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
3257 }
3258 else
3259 {
3260 if (u8OffsetIdx == 0)
3261 {
3262 pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx] = u32ShmAddr;
3263 }
3264 else if (u8OffsetIdx == 1)
3265 {
3266 pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3267 }
3268 }
3269
3270 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8OffsetIdx, (unsigned long)pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx]);
3271 return;
3272 }
3273
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3274 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3275 {
3276 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3277 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3278
3279 return pVPUCtx->u32FWShareInfoAddr[u8OffsetIdx];
3280 }
3281
HAL_VPU_EX_IsPowered(MS_U32 u32Id)3282 MS_BOOL HAL_VPU_EX_IsPowered(MS_U32 u32Id)
3283 {
3284 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3285 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3286
3287 return pVPUCtx->_bVPUPowered;
3288 }
3289
HAL_VPU_EX_IsRsted(MS_U32 u32Id)3290 MS_BOOL HAL_VPU_EX_IsRsted(MS_U32 u32Id)
3291 {
3292 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3293 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3294
3295 return pVPUCtx->_bVPURsted;
3296 }
3297
HAL_VPU_EX_IsEVDR2(MS_U32 u32Id)3298 MS_BOOL HAL_VPU_EX_IsEVDR2(MS_U32 u32Id)
3299 {
3300 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3301 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3302
3303 if (u8VPU == VPU_EVDR2)
3304 return TRUE;
3305 else
3306 return FALSE;
3307 }
3308
HAL_VPU_EX_MVDInUsed(MS_U32 u32Id)3309 MS_BOOL HAL_VPU_EX_MVDInUsed(MS_U32 u32Id)
3310 {
3311 //MVD is in used for MVD or HVD_TSP mode.
3312 MS_U8 i,j;
3313 MS_U8 u8UseCnt = 0;
3314 VPU_Unit_Ctx *pVPUCtx = NULL;
3315
3316 for (j = 0; j < MAX_VPU_NUM; j++)
3317 {
3318 pVPUCtx = &pVPUHalContext->_stCtx[j];
3319
3320 for (i = 0; i < sizeof(pVPUCtx->_stVPUStream) / sizeof(pVPUCtx->_stVPUStream[0]); i++)
3321 {
3322 if ((pVPUCtx->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3323 #ifdef VDEC3
3324 (pVPUCtx->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3325 #endif
3326 (pVPUCtx->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3327 {
3328 u8UseCnt++;
3329 }
3330 }
3331 }
3332
3333 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3334
3335 if (u8UseCnt != 0)
3336 {
3337 return TRUE;
3338 }
3339 else
3340 {
3341 return FALSE;
3342 }
3343 }
3344
HAL_VPU_EX_HVDInUsed(MS_U32 u32Id)3345 MS_BOOL HAL_VPU_EX_HVDInUsed(MS_U32 u32Id)
3346 {
3347 //HVD is in used for HVD or MVD in sub stream.
3348 MS_U8 i,j;
3349 MS_U8 u8UseCnt = 0;
3350 MS_BOOL bMVDTriggerHVD = FALSE;
3351 VPU_Unit_Ctx *pVPUCtx = NULL;
3352
3353 for (j = 0; j < MAX_VPU_NUM; j++)
3354 {
3355 pVPUCtx = &pVPUHalContext->_stCtx[j];
3356
3357 for (i = 0; i < sizeof(pVPUCtx->_stVPUStream) / sizeof(pVPUCtx->_stVPUStream[0]); i++)
3358 {
3359 #ifdef VDEC3
3360 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUCtx->_stVPUStream[i].eDecodertype) &&
3361 (pVPUCtx->u8HALId[i] == 1) &&
3362 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUCtx->_stVPUDecMode.u8DecMod);
3363 #else
3364 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUCtx->_stVPUStream[i].eDecodertype) &&
3365 (E_HAL_VPU_SUB_STREAM0 == pVPUCtx->_stVPUStream[i].eStreamId) &&
3366 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUCtx->_stVPUDecMode.u8DecMod);
3367 #endif
3368
3369 if(bMVDTriggerHVD)
3370 {
3371 VPU_MSG_DBG("%s i:%d eDecodertype:%d u8DecMod:%d\n", __FUNCTION__, i, pVPUCtx->_stVPUStream[i].eDecodertype, pVPUCtx->_stVPUDecMode.u8DecMod);
3372 }
3373
3374 if ((E_VPU_EX_DECODER_HVD == pVPUCtx->_stVPUStream[i].eDecodertype)
3375 #ifdef VDEC3
3376 ||(E_VPU_EX_DECODER_EVD == pVPUCtx->_stVPUStream[i].eDecodertype)
3377 #endif
3378 ||(TRUE == bMVDTriggerHVD)
3379 )
3380 {
3381 u8UseCnt++;
3382 }
3383 }
3384 }
3385
3386 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3387
3388 if (u8UseCnt != 0)
3389 {
3390 return TRUE;
3391 }
3392 else
3393 {
3394 return FALSE;
3395 }
3396 }
3397
3398 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(MS_U32 u32Id)3399 MS_BOOL HAL_VPU_EX_EVDInUsed(MS_U32 u32Id)
3400 {
3401 MS_U8 i;
3402 MS_U8 u8UseCnt = 0;
3403 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3404 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3405
3406 for (i = 0; i < sizeof(pVPUCtx->_stVPUStream) / sizeof(pVPUCtx->_stVPUStream[0]); i++)
3407 {
3408 if (E_VPU_EX_DECODER_EVD == pVPUCtx->_stVPUStream[i].eDecodertype)
3409 {
3410 u8UseCnt++;
3411 }
3412 }
3413
3414 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3415
3416 if (u8UseCnt != 0)
3417 {
3418 return TRUE;
3419 }
3420 else
3421 {
3422 return FALSE;
3423 }
3424 }
3425
3426 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(MS_U32 u32Id)3427 MS_BOOL HAL_VPU_EX_G2VP9InUsed(MS_U32 u32Id)
3428 {
3429 MS_U8 i;
3430 MS_U8 u8UseCnt = 0;
3431 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3432 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3433
3434 for (i = 0; i < sizeof(pVPUCtx->_stVPUStream) / sizeof(pVPUCtx->_stVPUStream[0]); i++)
3435 {
3436 if (E_VPU_EX_DECODER_G2VP9 == pVPUCtx->_stVPUStream[i].eDecodertype)
3437 {
3438 u8UseCnt++;
3439 }
3440 }
3441
3442 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3443
3444 if (u8UseCnt != 0)
3445 {
3446 return TRUE;
3447 }
3448 else
3449 {
3450 return FALSE;
3451 }
3452 }
3453 #endif
3454 #endif
3455
3456 //-----------------------------------------------------------------------------
3457 /// @brief \b Function \b Name: HAL_VPU_EX_SetDbgLevel()
3458 /// @brief \b Function \b Description: Set debug level
3459 /// @param -elevel \b IN : debug level
3460 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3461 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3462 {
3463 VPRINTF("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3464
3465 switch (eLevel)
3466 {
3467 case E_VPU_EX_UART_LEVEL_ERR:
3468 {
3469 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3470 break;
3471 }
3472 case E_VPU_EX_UART_LEVEL_INFO:
3473 {
3474 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3475 break;
3476 }
3477 case E_VPU_EX_UART_LEVEL_DBG:
3478 {
3479 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3480 break;
3481 }
3482 case E_VPU_EX_UART_LEVEL_TRACE:
3483 {
3484 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3485 break;
3486 }
3487 case E_VPU_EX_UART_LEVEL_FW:
3488 {
3489 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3490 break;
3491 }
3492 default:
3493 {
3494 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3495 break;
3496 }
3497 }
3498 }
3499
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3500 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3501 {
3502 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3503 MS_U32 u32CmdArg = (MS_U32)eVerType;
3504 MS_U32 u32Version = 0xFFFFFFFF;
3505 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3506 MS_U8 u8VPU = pVPUHalContext->u8Cidx[u8OffsetIdx];
3507
3508 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3509 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3510 {
3511 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3512 return u32Version;
3513 }
3514
3515 MS_BOOL bRet = false;
3516 MS_U32 u32TimeOut = 0xFFFFFFFF;
3517
3518 while(--u32TimeOut)
3519 {
3520 if (HAL_VPU_EX_MBoxRdy(u32Id, VPU_RISC_MBOX0))
3521 {
3522 bRet = HAL_VPU_EX_MBoxRead(u32Id, VPU_RISC_MBOX0, &u32Version);
3523 if (false == bRet)
3524 {
3525 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3526 return u32Version;
3527 }
3528
3529 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR(u8VPU), VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3530 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3531 return u32Version;
3532 }
3533 }
3534
3535 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3536
3537 return u32Version;
3538 }
3539
HAL_VPU_EX_NotSupportDS(void)3540 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3541 {
3542 return FALSE;
3543 }
3544
3545 //-----------------------------------------------------------------------------
3546 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3547 /// @brief \b Function \b Description: Get VPU MIU base address
3548 /// @return - vpu MIU1 base
3549 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3550 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3551 {
3552 return VPU_MIU1BASE_ADDR;
3553 }
3554
3555
HAL_VPU_EX_GetSHMAddr(void)3556 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3557 {
3558 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3559 {
3560 return 0;
3561 }
3562 return pVPUHalContext->u32VPUSHMAddr;
3563 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3564 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3565 {
3566 pVPUHalContext->bEnableVPUSecureMode = enable;
3567 return TRUE;
3568 }
3569
HAL_VPU_EX_GetSecurityMode(void)3570 MS_BOOL HAL_VPU_EX_GetSecurityMode(void)
3571 {
3572 return pVPUHalContext->bEnableVPUSecureMode;
3573 }
3574
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3575 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3576 {
3577 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3578
3579 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3580 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3581 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3582 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3583 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3584 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3585 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3586 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3587
3588 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3589 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3590 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3591 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3592 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3593 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3594 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3595 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3596 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3597 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3598
3599 return TRUE;
3600 }
3601
3602 //-----------------------------------------------------------------------------
3603 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3604 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3605 /// @return - success/fail
3606 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3607 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3608 {
3609 #define MAX_CAPABILITY_INFO_NUM 8
3610 #define MAX_CODEC_TYPE_NUM 20
3611
3612 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3613 {
3614 //width, height, frmrate, profile, level, version, reserved1, reserved2,
3615 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3616 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3617 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 0, 0},//E_HVD_EX_CODEC_TYPE_H263
3618 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3619 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 0, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3620 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 0, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3621 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 0, 0},//E_HVD_EX_CODEC_TYPE_FLV
3622 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3623 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3624 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_RV8
3625 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_RV9
3626 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_H264
3627 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_AVS
3628 { 1280, 720, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3629 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_MVC
3630 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_VP8
3631 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3632 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_VP9_0, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_VP9
3633 { 4096, 2176, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_VDEC_EX_CODEC_TYPE_HEVC_DV
3634 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_VDEC_EX_CODEC_TYPE_H264_DV
3635 };
3636
3637 if(eCodecType < MAX_CODEC_TYPE_NUM)
3638 {
3639 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3640 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3641 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3642 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3643 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3644 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3645 return TRUE;
3646 }
3647 else
3648 {
3649 return FALSE;
3650 }
3651 }
3652
HAL_VPU_EX_ExchangeCidx(MS_U32 u32Id)3653 void HAL_VPU_EX_ExchangeCidx(MS_U32 u32Id)
3654 {
3655 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3656 VPU_Unit_Ctx stCtx;
3657
3658 HVD_memcpy((volatile void *) (&stCtx), (void *) (&pVPUHalContext->_stCtx[0]), sizeof(VPU_Unit_Ctx));
3659 HVD_memcpy((volatile void *) (&pVPUHalContext->_stCtx[0]), (void *) (&pVPUHalContext->_stCtx[1]), sizeof(VPU_Unit_Ctx));
3660 HVD_memcpy((volatile void *) (&pVPUHalContext->_stCtx[1]), (void *) (&stCtx), sizeof(VPU_Unit_Ctx));
3661
3662 pVPUHalContext->u8Cidx[u8OffsetIdx] = 1 - pVPUHalContext->u8Cidx[u8OffsetIdx];
3663
3664 VPRINTF("[%s] u8Id=%d, cidx=%d \n", __FUNCTION__, u8OffsetIdx, pVPUHalContext->u8Cidx[u8OffsetIdx]);
3665
3666 return;
3667 }
3668
3669 #ifdef VDEC3
HAL_VPU_EX_SetCidx(MS_U32 u32Id,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)3670 void HAL_VPU_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
3671 {
3672 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3673 pVPUHalContext->u8Cidx[u8OffsetIdx] = _VPU_EX_DecideCidx(u8OffsetIdx, bIsEVD, bIsNStreamMode);
3674 return;
3675 }
3676 #else
HAL_VPU_EX_SetCidx(MS_U32 u32Id,MS_BOOL bIsEVD)3677 void HAL_VPU_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD)
3678 {
3679 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3680 pVPUHalContext->u8Cidx[u8OffsetIdx] = _VPU_EX_DecideCidx(u8OffsetIdx, bIsEVD);
3681 return;
3682 }
3683 #endif
3684
3685 #ifdef VDEC3
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bIsNstreamMode)3686 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode)
3687 {
3688 MS_U32 i, max_bbu_cnt;
3689 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3690
3691 if(pTaskInfo == NULL)
3692 return retBBUId;
3693
3694 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3695 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3696
3697 BBU_STATE *bbu_state;
3698 SLQ_STATE *slq_state = &pVPUCtx->stMVD_SLQ_STATE[0];
3699 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3700
3701 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3702
3703 pVPUCtx->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3704
3705 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3706 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3707 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3708
3709 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3710 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUCtx->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3711
3712 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3713 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUCtx->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3714 */
3715 #if 1
3716 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3717 {
3718 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3719 if (bTSP)
3720 {
3721 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3722 {
3723 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3724 slq_state[u8TaskId].bTSP = TRUE;
3725 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3726 return u8TaskId;
3727 }
3728 }
3729 else
3730 {
3731 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3732 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3733 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3734 {
3735 if (slq_state[i].u32Used != 0)
3736 {
3737 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3738 {
3739 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3740 }
3741 }
3742 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3743 {
3744 avaliable_bbu_idx = i; // recored the first empty bbu
3745 }
3746 }
3747
3748 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // In Nstream mode, first priority is sharing bbu
3749 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3750 slq_state[shared_bbu_idx].bTSP = FALSE;
3751 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3752 return shared_bbu_idx;
3753 }
3754 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3755 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3756 slq_state[u8TaskId].bTSP = FALSE;
3757 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3758 return u8TaskId;
3759 }
3760 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3761 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3762 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3763 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3764 return avaliable_bbu_idx;
3765 }
3766 else {
3767 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3768 }
3769 }
3770 }
3771 #if SUPPORT_G2VP9
3772 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3773 {
3774 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3775 // Don't care the return value, G2_VP9 will not use it.
3776 return 0;
3777 }
3778 #endif
3779 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3780 {
3781 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3782 // Don't care the return value, VP8 will not use it.
3783 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3784 return u8Offset;
3785 //return 0;
3786 }
3787 else
3788 {
3789 switch (pTaskInfo->eDecType)
3790 {
3791 case E_VPU_EX_DECODER_EVD:
3792 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3793 bbu_state = &pVPUCtx->stEVD_BBU_STATE[0];
3794 break;
3795 case E_VPU_EX_DECODER_HVD:
3796 case E_VPU_EX_DECODER_RVD:
3797 case E_VPU_EX_DECODER_MVC:
3798 default:
3799 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3800 bbu_state = &pVPUCtx->stHVD_BBU_STATE[0];
3801 break;
3802 }
3803
3804 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3805 if (bTSP)
3806 {
3807 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3808 {
3809 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3810 bbu_state[u8TaskId].bTSP = TRUE;
3811 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3812 slq_state[u8TaskId].bTSP = TRUE;
3813 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3814 return u8TaskId;
3815 }
3816 }
3817 else
3818 {
3819 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3820 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3821 for (i = 0; i < max_bbu_cnt; i++)
3822 {
3823 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3824 {
3825 if (bbu_state[i].bTSP == FALSE)
3826 {
3827 shared_bbu_idx = i;
3828 }
3829 }
3830 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3831 {
3832 avaliable_bbu_idx = i;
3833 }
3834 }
3835 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // // In Nstream mode, first priority is sharing bbu
3836 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3837 return shared_bbu_idx;
3838 }
3839 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3840 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3841 return u8TaskId;
3842 }
3843 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3844 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3845 return avaliable_bbu_idx;
3846 }
3847 else {
3848 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3849 }
3850 }
3851 }
3852 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3853 MS_U32 j;
3854 MS_BOOL Got = FALSE;
3855 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3856 {
3857 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3858 {
3859 if(slq_state[i].u32Used != 0)
3860 {
3861 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3862 {
3863 retBBUId = i;
3864 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3865 slq_state[retBBUId].bTSP = bTSP;
3866 slq_state[retBBUId].bUsedbyMVD = TRUE;
3867 return retBBUId;
3868 }
3869 }
3870 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3871 {
3872 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3873 {
3874 if(pVPUCtx->stEVD_BBU_STATE[i].u32Used != 0 && pVPUCtx->stEVD_BBU_STATE[i].bTSP == FALSE)
3875 {
3876 Got = TRUE;
3877 retBBUId = i;
3878 }
3879 }
3880
3881 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3882 {
3883 if(pVPUCtx->stHVD_BBU_STATE[i].u32Used != 0 && pVPUCtx->stHVD_BBU_STATE[i].bTSP == FALSE)
3884 {
3885 Got = TRUE;
3886 retBBUId = i;
3887 }
3888 }
3889
3890 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3891 retBBUId = i;
3892 }
3893 }
3894 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3895 {
3896 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3897 slq_state[retBBUId].bTSP = bTSP;
3898 slq_state[retBBUId].bUsedbyMVD = TRUE;
3899 }
3900 }
3901 #if SUPPORT_G2VP9
3902 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3903 {
3904 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3905 // Don't care the return value, G2_VP9 will not use it.
3906 return 0;
3907 }
3908 #endif
3909 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3910 {
3911 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3912 // Don't care the return value, VP8 will not use it.
3913 return 0;
3914 }
3915 else // HVD/EVD case
3916 {
3917 switch (pTaskInfo->eDecType)
3918 {
3919 case E_VPU_EX_DECODER_EVD:
3920 case E_VPU_EX_DECODER_G2VP9:
3921 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3922 bbu_state = &pVPUCtx->stEVD_BBU_STATE[0];
3923 break;
3924 case E_VPU_EX_DECODER_HVD:
3925 case E_VPU_EX_DECODER_RVD:
3926 case E_VPU_EX_DECODER_MVC:
3927 default:
3928 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3929 bbu_state = &pVPUCtx->stHVD_BBU_STATE[0];
3930 break;
3931 }
3932
3933 for (i = 0; i < max_bbu_cnt; i++)
3934 {
3935 if(bbu_state[i].u32Used != 0)
3936 {
3937 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3938 {
3939 retBBUId = i;
3940 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3941 bbu_state[retBBUId].bTSP = bTSP;
3942 return retBBUId;
3943 }
3944 }
3945 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3946 {
3947 if(i < MAX_MVD_SLQ_COUNT)
3948 {
3949 if(!bTSP) //HVD/EVD first MM case
3950 {
3951 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3952 {
3953 retBBUId = i;
3954 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3955 bbu_state[retBBUId].bTSP = bTSP;
3956 return retBBUId;
3957 }
3958
3959 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3960 retBBUId = i;
3961 }
3962 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3963 {
3964 retBBUId = i;
3965 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3966 bbu_state[retBBUId].bTSP = bTSP;
3967 slq_state[retBBUId].bUsedbyMVD = FALSE;
3968 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3969 slq_state[retBBUId].bTSP = bTSP;
3970 return retBBUId;
3971 }
3972 }
3973 }
3974 }
3975 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3976 {
3977 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3978 bbu_state[retBBUId].bTSP = bTSP;
3979 if(bTSP)
3980 {
3981 slq_state[retBBUId].bUsedbyMVD = FALSE;
3982 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3983 slq_state[retBBUId].bTSP = bTSP;
3984 }
3985 }
3986 }
3987 #endif
3988 return retBBUId;
3989 }
3990
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3991 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3992 {
3993 if(pTaskInfo == NULL)
3994 return FALSE;
3995
3996 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3997 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
3998
3999 MS_U32 max_bbu_cnt;
4000 BBU_STATE *bbu_state;
4001 SLQ_STATE *slq_state = &pVPUCtx->stMVD_SLQ_STATE[0];
4002 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4003 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
4004
4005 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
4006 /* MS_U32 i;
4007 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
4008 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
4009
4010 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
4011 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUCtx->stEVD_BBU_STATE[i].u32Used,pVPUCtx->stEVD_BBU_STATE[i].bTSP);
4012
4013 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
4014 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUCtx->stHVD_BBU_STATE[i].u32Used,pVPUCtx->stHVD_BBU_STATE[i].bTSP);
4015 */
4016 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
4017 {
4018 // TO DO
4019 if(u32BBUId < MAX_MVD_SLQ_COUNT)
4020 {
4021 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4022 slq_state[u32BBUId].bTSP = FALSE;
4023 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4024 return TRUE;
4025 }
4026 }
4027 #if SUPPORT_G2VP9
4028 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
4029 {
4030 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4031 return TRUE;
4032 }
4033 #endif
4034 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4035 {
4036 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4037 return TRUE;
4038 }
4039 else
4040 {
4041 switch (pTaskInfo->eDecType)
4042 {
4043 case E_VPU_EX_DECODER_EVD:
4044 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4045 bbu_state = &pVPUCtx->stEVD_BBU_STATE[0];
4046 break;
4047 case E_VPU_EX_DECODER_HVD:
4048 case E_VPU_EX_DECODER_RVD:
4049 case E_VPU_EX_DECODER_MVC:
4050 default:
4051 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4052 bbu_state = &pVPUCtx->stHVD_BBU_STATE[0];
4053 break;
4054 }
4055
4056 if (u32BBUId < max_bbu_cnt)
4057 {
4058 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4059 bbu_state[u32BBUId].bTSP = FALSE;
4060 if (bTSP)
4061 {
4062 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4063 slq_state[u32BBUId].bTSP = FALSE;
4064 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4065 }
4066 return TRUE;
4067 }
4068 }
4069 return FALSE;
4070 }
4071
HAL_VPU_EX_GetVBBUVacancy(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4072 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4073 {
4074 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4075 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4076 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + u32VBBUAddr);
4077
4078 if (CHECK_NULL_PTR(pstVBBU))
4079 return 0;
4080 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4081 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4082 MS_U32 u32Vacancy = 0;
4083
4084 if (u32WrPtr == u32RdPtr)
4085 {
4086 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4087 }
4088 else if (u32WrPtr > u32RdPtr)
4089 {
4090 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4091 }
4092 else
4093 {
4094 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4095 }
4096
4097 return u32Vacancy;
4098 }
4099
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4100 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4101 {
4102 return MAX_VDEC_VBBU_ENTRY_COUNT;
4103 }
4104
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4105 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4106 {
4107 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4108 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4109 return pVPUCtx->u32FWCodeAddr;
4110 }
4111
4112
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4113 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4114 {
4115 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4116 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4117 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + u32VBBUAddr);
4118
4119 if (CHECK_NULL_PTR(pstVBBU))
4120 return FALSE;
4121
4122 MsOS_ReadMemory();
4123 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4124
4125 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4126 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4127 {
4128 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4129 }
4130 else
4131 {
4132 #if SUPPORT_G2VP9
4133 if (E_VPU_EX_DECODER_G2VP9 == pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype)
4134 {
4135 if (stEntry->u32Offset == 0)
4136 return 0;
4137 else
4138 return stEntry->u32Offset - pVPUCtx->u32BitstreamAddress[u8OffsetIdx];
4139 }
4140 else
4141 #endif
4142 {
4143 return stEntry->u32Offset;
4144 }
4145 }
4146 }
4147
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4148 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4149 {
4150 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4151 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4152 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + u32VBBUAddr);
4153 VDEC_VBBU_Entry *stEntry;
4154
4155 MsOS_ReadMemory();
4156 if (CHECK_NULL_PTR(pstVBBU))
4157 return 0;
4158
4159 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4160
4161 if (u32WrPtr == 0)
4162 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4163 else
4164 u32WrPtr--;
4165
4166 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4167
4168 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4169 #if SUPPORT_G2VP9
4170 if (E_VPU_EX_DECODER_G2VP9 == pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype)
4171 {
4172 if (stEntry->u32Offset == 0)
4173 return 0;
4174 else
4175 return stEntry->u32Offset + stEntry->u32Length - pVPUCtx->u32BitstreamAddress[u8OffsetIdx];
4176 }
4177 else
4178 #endif
4179 {
4180 return stEntry->u32Offset + stEntry->u32Length;
4181 }
4182 }
4183
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4184 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4185 {
4186 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4187 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4188 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + u32VBBUAddr);
4189
4190 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4191 return FALSE;
4192
4193 MsOS_ReadMemory();
4194 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4195 MS_U32 u32NewWrPtr;
4196
4197 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4198 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4199 {
4200 u32NewWrPtr = 0;
4201 }
4202
4203 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4204
4205 stEntry->u32Offset = stVpuPkt->u32Offset;
4206
4207 #if SUPPORT_G2VP9
4208 if (E_VPU_EX_DECODER_G2VP9 == pVPUCtx->_stVPUStream[u8OffsetIdx].eDecodertype)
4209 {
4210 stEntry->u32Offset += pVPUCtx->u32BitstreamAddress[u8OffsetIdx];
4211 }
4212 #endif
4213
4214 stEntry->u32Length = stVpuPkt->u32Length;
4215 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4216 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4217 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4218
4219 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4220
4221 pstVBBU->u32WrPtr = u32NewWrPtr;
4222
4223 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4224
4225 MsOS_FlushMemory();
4226
4227 return TRUE;
4228 }
4229
HAL_VPU_EX_IsVBBUEmpty(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4230 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4231 {
4232 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4233 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4234 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + u32VBBUAddr);
4235
4236 if (CHECK_NULL_PTR(pstVBBU))
4237 return FALSE;
4238
4239 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4240 }
4241
4242 ///-----------------------------------------------------------------------------
4243 /// specify the command send to Mail box or DRAM
4244 /// @return TRUE or FALSE
4245 /// - TRUE, Mail box
4246 /// - FALSE, Dram
4247 /// @param u32Cmd \b IN: Command is going to be sned
4248 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4249 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4250 {
4251 MS_BOOL bResult = TRUE;
4252
4253 switch (u32Cmd)
4254 {
4255 // *********** Runtime action Command
4256 /* case E_HVD_CMD_RELEASE_DISPQ:
4257 case E_HVD_CMD_UPDATE_DISPQ:
4258 case E_HVD_CMD_FLUSH_DEC_Q:
4259 case E_HVD_CMD_FLUSH:
4260 case E_HVD_CMD_PLAY:
4261 case E_HVD_CMD_PAUSE:
4262 case E_HVD_CMD_STOP:
4263 case E_HVD_CMD_STEP_DECODE:
4264 case E_HVD_CMD_SKIP_DEC:
4265 case E_HVD_CMD_DISP_I_DIRECT:*/
4266 // *********** Dual-Stream Create Task Command
4267 case E_DUAL_CMD_TASK0_HVD_BBU:
4268 case E_DUAL_CMD_TASK0_HVD_TSP:
4269 case E_DUAL_CMD_TASK0_MVD_SLQ:
4270 case E_DUAL_CMD_TASK0_MVD_TSP:
4271 case E_DUAL_CMD_TASK1_HVD_BBU:
4272 case E_DUAL_CMD_TASK1_HVD_TSP:
4273 case E_DUAL_CMD_MODE:
4274 #ifndef _WIN32
4275 case E_DUAL_CMD_TASK1_MVD_SLQ:
4276 case E_DUAL_CMD_TASK1_MVD_TSP:
4277 #endif
4278 case E_DUAL_CMD_DEL_TASK:
4279 case E_DUAL_CMD_SINGLE_TASK:
4280 case E_DUAL_VERSION:
4281 case E_DUAL_R2_CMD_EXIT:
4282 case E_DUAL_CMD_STC_MODE:
4283 #ifdef VDEC3
4284 case E_DUAL_R2_CMD_FBADDR:
4285 case E_DUAL_R2_CMD_FBSIZE:
4286 // *********** N-Streams
4287 case E_NST_CMD_TASK_HVD_TSP:
4288 case E_NST_CMD_TASK_HVD_BBU:
4289 case E_NST_CMD_TASK_MVD_TSP:
4290 case E_NST_CMD_TASK_MVD_SLQ:
4291 case E_NST_CMD_DEL_TASK:
4292 case E_NST_CMD_COMMON_MASK:
4293 case E_NST_CMD_COMMON_CMD1:
4294 #endif
4295 case E_DUAL_CMD_COMMON:
4296 {
4297 bResult = TRUE;
4298 }
4299 break;
4300 default:
4301 {
4302 bResult = FALSE;
4303 }
4304 break;
4305 }
4306
4307 return bResult;
4308 }
4309
4310 ///-----------------------------------------------------------------------------
4311 /// specify the command send to Mail box or DRAM
4312 /// @return TRUE or FALSE
4313 /// - TRUE, Mail box
4314 /// - FALSE, Dram
4315 /// @param u32Cmd \b IN: Command is going to be sned
4316 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4317 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4318 {
4319 MS_BOOL bResult = TRUE;
4320
4321 switch (u32Cmd)
4322 {
4323 // *********** Runtime action Command
4324 case E_HVD_CMD_RELEASE_DISPQ:
4325 case E_HVD_CMD_UPDATE_DISPQ:
4326 case E_HVD_CMD_FLUSH_DEC_Q:
4327 case E_HVD_CMD_PAUSE:
4328 case E_HVD_CMD_FLUSH:
4329 case E_HVD_CMD_PLAY:
4330 case E_HVD_CMD_STOP:
4331 case E_HVD_CMD_SKIP_DEC:
4332 case E_HVD_CMD_DISP_I_DIRECT:
4333 case E_HVD_CMD_STEP_DECODE:
4334 case E_HVD_CMD_INC_DISPQ_NUM:
4335 {
4336 bResult = TRUE;
4337 }
4338 break;
4339 default:
4340 {
4341 bResult = FALSE;
4342 }
4343 break;
4344 }
4345
4346 return bResult;
4347 }
4348
4349 ///-----------------------------------------------------------------------------
4350 /// Send message to HVD stream command queue
4351 /// @return TRUE or FALSE
4352 /// - TRUE, Success
4353 /// - FALSE, Failed
4354 /// @param u32DramAddr \b IN: address to be writen
4355 /// @param u32Msg \b IN: data to be writen
4356 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4357 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4358 {
4359 MS_BOOL bResult = TRUE;
4360
4361 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4362
4363 WRITE_LONG(u32DramAddr,u32Msg);
4364
4365 return bResult;
4366 }
4367
4368 ///-----------------------------------------------------------------------------
4369 /// Read task share memory to specify that task command queue is empty or not
4370 /// @return TRUE or FALSE
4371 /// - TRUE, Empty
4372 /// - FALSE, Non empty
4373 /// @param u32Id \b IN: Task information
4374 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4375 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4376 {
4377 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4378 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4379 if (!cmd_q)
4380 {
4381 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4382 return FALSE;
4383 }
4384
4385 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4386 }
4387
4388 ///-----------------------------------------------------------------------------
4389 /// Read task share memory to specify that task command queue is full or not
4390 /// @return TRUE or FALSE
4391 /// - TRUE, Full
4392 /// - FALSE, Non full
4393 /// @param u32Id \b IN: Task information
4394 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4395 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4396 {
4397 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4398 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4399 if (!cmd_q)
4400 {
4401 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4402 return TRUE;
4403 }
4404 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4405
4406 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4407 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4408
4409 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4410 }
4411
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4412 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4413 {
4414 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4415 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4416 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4417 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4418 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4419
4420 #if HVD_ENABLE_MVC
4421 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4422 {
4423 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4424 }
4425 #endif
4426
4427 if (CHECK_NULL_PTR(cmd_q))
4428 {
4429 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4430 return bResult;
4431 }
4432 MS_VIRT u32CmdQWdPtr;
4433
4434 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4435 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4436
4437 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4438 return E_HVD_COMMAND_QUEUE_FULL;
4439 else
4440 {
4441 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4442 }
4443
4444 switch (u8CmdType)
4445 {
4446 case E_HVD_CMDQ_CMD:
4447 {
4448 u32Msg |= (u8TaskID << 24);
4449 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4450
4451 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4452
4453 if (bResult)
4454 {
4455 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4456
4457 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4458 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4459
4460 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4461 }
4462 break;
4463 }
4464 case E_HVD_CMDQ_ARG:
4465 {
4466 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4467 if (bResult)
4468 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4469 break;
4470 }
4471 default:
4472 {
4473 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4474 break;
4475 }
4476 }
4477
4478 MsOS_FlushMemory();
4479
4480 return bResult;
4481 }
4482
4483 ///-----------------------------------------------------------------------------
4484 /// Read task share memory to specify that task display command queue is empty or not
4485 /// @return TRUE or FALSE
4486 /// - TRUE, Empty
4487 /// - FALSE, Non empty
4488 /// @param u32Id \b IN: Task information
4489 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4490 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4491 {
4492 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4493 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4494 if (!cmd_q)
4495 {
4496 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4497 return FALSE;
4498 }
4499
4500 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4501 }
4502
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4503 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4504 {
4505 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4506 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4507 if (!cmd_q)
4508 {
4509 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4510 return TRUE;
4511 }
4512
4513 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4514
4515 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4516 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4517
4518 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4519 }
4520
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4521 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4522 {
4523 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4524 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4525 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4526 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4527 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4528
4529 #if HVD_ENABLE_MVC
4530 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4531 {
4532 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4533 }
4534 #endif
4535
4536 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4537 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4538
4539 if (CHECK_NULL_PTR(cmd_q))
4540 {
4541 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4542 return bResult;
4543 }
4544
4545 MS_VIRT u32DISPCMDQWdPtr;
4546
4547 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4548 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4549
4550 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4551 return E_HVD_COMMAND_QUEUE_FULL;
4552 else
4553 {
4554 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUCtx->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4555 }
4556
4557 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUCtx->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4558
4559 switch (u8CmdType)
4560 {
4561 case E_HVD_CMDQ_CMD:
4562 {
4563 u32Msg |= (u8TaskID << 24);
4564 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4565
4566 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4567
4568 if (bResult)
4569 {
4570 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4571
4572 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4573 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4574
4575 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4576 }
4577 break;
4578 }
4579 case E_HVD_CMDQ_ARG:
4580 {
4581 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4582 if (bResult)
4583 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4584 break;
4585 }
4586 default:
4587 {
4588 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4589 break;
4590 }
4591 }
4592
4593 MsOS_FlushMemory();
4594
4595 return bResult;
4596 }
4597
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4598 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4599 {
4600 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4601 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4602 MS_U32 u32StAddr;
4603 MS_U8 u8TmpMiuSel;
4604
4605 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4606
4607 pVPUCtx->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4608
4609 return TRUE;
4610 }
4611 #endif
4612
HAL_VPU_EX_DynamicFBMode(MS_U32 u32Id,MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4613 void HAL_VPU_EX_DynamicFBMode(MS_U32 u32Id, MS_BOOL bEnable, MS_PHY u32address, MS_U32 u32Size)
4614 {
4615 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4616 VPU_Unit_Ctx *pVPUCtx = &pVPUHalContext->_stCtx[pVPUHalContext->u8Cidx[u8OffsetIdx]];
4617
4618 pVPUCtx->bEnableDymanicFBMode = bEnable;
4619
4620 if(u32address >= HAL_MIU1_BASE)
4621 {
4622 pVPUCtx->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4623 }
4624 else
4625 {
4626 pVPUCtx->u32DynamicFBAddress = u32address;
4627 }
4628
4629 pVPUCtx->u32DynamicFBSize = u32Size;
4630 }
4631
4632 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4633 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4634 {
4635 MS_S32 handle;
4636 switch(eClkPortType)
4637 {
4638 case E_VPU_EX_CLKPORT_MVD:
4639 {
4640 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4641 if(bEnable)
4642 {
4643 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4644 }
4645 else
4646 {
4647 Drv_Clkm_Clk_Gate_Disable(handle);
4648 }
4649 break;
4650 }
4651 case E_VPU_EX_CLKPORT_MVD_CORE:
4652 {
4653 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4654 if(bEnable)
4655 {
4656 Drv_Clkm_Set_Clk_Source(handle, "");
4657 }
4658 else
4659 {
4660 Drv_Clkm_Clk_Gate_Disable(handle);
4661 }
4662 break;
4663 }
4664 case E_VPU_EX_CLKPORT_MVD_PAS:
4665 {
4666 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4667 if(bEnable)
4668 {
4669 Drv_Clkm_Set_Clk_Source(handle, "");
4670 }
4671 else
4672 {
4673 Drv_Clkm_Clk_Gate_Disable(handle);
4674 }
4675 break;
4676 }
4677 case E_VPU_EX_CLKPORT_HVD:
4678 {
4679 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4680 if(bEnable)
4681 {
4682 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4683 }
4684 else
4685 {
4686 Drv_Clkm_Clk_Gate_Disable(handle);
4687 }
4688 break;
4689 }
4690 case E_VPU_EX_CLKPORT_HVD_IDB:
4691 {
4692 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4693 if(bEnable)
4694 {
4695 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4696 }
4697 else
4698 {
4699 Drv_Clkm_Clk_Gate_Disable(handle);
4700 }
4701 break;
4702 }
4703 case E_VPU_EX_CLKPORT_HVD_AEC:
4704 {
4705 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4706 if(bEnable)
4707 {
4708 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4709 }
4710 else
4711 {
4712 Drv_Clkm_Clk_Gate_Disable(handle);
4713 }
4714 break;
4715 }
4716 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4717 {
4718 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4719 if(bEnable)
4720 {
4721 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4722 }
4723 else
4724 {
4725 Drv_Clkm_Clk_Gate_Disable(handle);
4726 }
4727 break;
4728 }
4729 case E_VPU_EX_CLKPORT_VP8:
4730 {
4731 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4732 if(bEnable)
4733 {
4734 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4735 }
4736 else
4737 {
4738 Drv_Clkm_Clk_Gate_Disable(handle);
4739 }
4740 break;
4741 }
4742 case E_VPU_EX_CLKPORT_EVD:
4743 {
4744 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4745 if(bEnable)
4746 {
4747 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4748 }
4749 else
4750 {
4751 Drv_Clkm_Clk_Gate_Disable(handle);
4752 }
4753 break;
4754 }
4755 case E_VPU_EX_CLKPORT_EVD_PPU:
4756 {
4757 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4758 if(bEnable)
4759 {
4760 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4761 }
4762 else
4763 {
4764 Drv_Clkm_Clk_Gate_Disable(handle);
4765 }
4766 break;
4767 }
4768 case E_VPU_EX_CLKPORT_EVD_LITE:
4769 {
4770 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4771 if(bEnable)
4772 {
4773 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4774 }
4775 else
4776 {
4777 Drv_Clkm_Clk_Gate_Disable(handle);
4778 }
4779 break;
4780 }
4781 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4782 {
4783 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4784 if(bEnable)
4785 {
4786 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4787 }
4788 else
4789 {
4790 Drv_Clkm_Clk_Gate_Disable(handle);
4791 }
4792 break;
4793 }
4794 case E_VPU_EX_CLKPORT_VD_MHEG5:
4795 {
4796 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4797 if(bEnable)
4798 {
4799 Drv_Clkm_Set_Clk_Source(handle, "");
4800 }
4801 else
4802 {
4803 Drv_Clkm_Clk_Gate_Disable(handle);
4804 }
4805 break;
4806 }
4807 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4808 {
4809 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4810 if(bEnable)
4811 {
4812 Drv_Clkm_Set_Clk_Source(handle, "");
4813 }
4814 else
4815 {
4816 Drv_Clkm_Clk_Gate_Disable(handle);
4817 }
4818 break;
4819 }
4820 }
4821 }
4822 #endif //#ifdef CONFIG_MSTAR_CLKM
4823
4824 #if !defined(MSOS_TYPE_NUTTX)
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4825 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4826 {
4827 MS_SIZE FrameBufferSize = 0;
4828
4829 switch(eCodecType)
4830 {
4831 case E_VPU_EX_CODEC_TYPE_MPEG2:
4832 case E_VPU_EX_CODEC_TYPE_H263:
4833 case E_VPU_EX_CODEC_TYPE_MPEG4:
4834 case E_VPU_EX_CODEC_TYPE_DIVX311:
4835 case E_VPU_EX_CODEC_TYPE_DIVX412:
4836 case E_VPU_EX_CODEC_TYPE_FLV:
4837 FrameBufferSize = 0x1E00000;
4838 break;
4839 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4840 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4841 FrameBufferSize = 0x6C00000;
4842 break;
4843 case E_VPU_EX_CODEC_TYPE_RV8:
4844 case E_VPU_EX_CODEC_TYPE_RV9:
4845 FrameBufferSize = 0x1B00000;
4846 break;
4847 case E_VPU_EX_CODEC_TYPE_VP8:
4848 FrameBufferSize = 0x1500000;
4849 break;
4850 case E_VPU_EX_CODEC_TYPE_H264:
4851 FrameBufferSize = 0x8200000;
4852 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4853 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4854 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4855 break;
4856 case E_VPU_EX_CODEC_TYPE_AVS:
4857 FrameBufferSize = 0x1B00000;
4858 break;
4859 case E_VPU_EX_CODEC_TYPE_MJPEG:
4860 FrameBufferSize = 0x2800000;
4861 break;
4862 case E_VPU_EX_CODEC_TYPE_MVC:
4863 FrameBufferSize = 0x4200000;
4864 break;
4865 case E_VPU_EX_CODEC_TYPE_HEVC:
4866 #if SUPPORT_MSVP9
4867 case E_VPU_EX_CODEC_TYPE_VP9:
4868 #endif
4869 FrameBufferSize = 0xA000000;
4870 break;
4871 #if !SUPPORT_MSVP9
4872 case E_VPU_EX_CODEC_TYPE_VP9:
4873 FrameBufferSize = 0x7800000;
4874 break;
4875 #endif
4876 default:
4877 FrameBufferSize = 0;
4878 break;
4879 }
4880
4881 return FrameBufferSize;
4882 }
4883
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4884 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4885 {
4886 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4887 }
4888 #endif
4889
4890 #ifdef CMA_DRV_DIRECT_INIT
4891 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4892 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4893 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4894 {
4895 MS_SIZE FrameBufferSize = 0;
4896
4897 if (!offset || !length)
4898 return FALSE;
4899
4900 total_length -= unUseSize;
4901 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4902 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4903
4904 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4905
4906 if(FrameBufferSize == 0)
4907 {
4908 return FALSE;
4909 }
4910 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4911 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4912 if (total_length < FrameBufferSize)
4913 {
4914 *offset = unUseSize;
4915 *length = total_length;
4916 }
4917 else // todo, dual decode case
4918 {
4919 *offset = unUseSize;
4920 *length = FrameBufferSize;
4921 }
4922 return TRUE;
4923 }
4924 #endif
4925
4926 #else
4927 #include "halVPU_EX.h"
4928 #include "drvMMIO.h"
4929 #include "../hvd_lite/regHVD_EX.h"
4930 #include "halCHIP.h"
4931
4932 #if defined(MSOS_TYPE_NUTTX)
4933 extern int lib_lowprintf(const char *fmt, ...);
4934 #define PRINTF lib_lowprintf
4935 #elif defined(MSOS_TYPE_OPTEE)
4936 #define PRINTF printf
4937 #endif
4938 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
4939 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
4940
4941 MS_U8 u8FW_Binary[] = {
4942 #include "fwVPU.dat"
4943 };
4944
4945 MS_U32 u32HVDRegOSBase;
4946
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)4947 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
4948 {
4949 //PRINTF("do load code,u32DestAddr %x\n",addr);
4950 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
4951 MAsm_CPU_Sync();
4952 MsOS_FlushMemory();
4953
4954 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
4955 {
4956 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
4957 return FALSE;
4958 }
4959 return TRUE;
4960 }
4961
HAL_VPU_EX_SetLockDownRegister(void * param,MS_U8 u8IsHVD)4962 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param,MS_U8 u8IsHVD)
4963 {
4964 #if 1
4965 MS_U32 u32StAddr_main;
4966 MS_U32 u32StAddr_sub;
4967 MS_U32 u32Length_main;
4968 MS_U32 u32Length_sub;
4969 MS_U32 u32NonPMBankSize = 0;
4970 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
4971
4972 if(param == NULL)
4973 {
4974 return FALSE;
4975 }
4976
4977 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
4978
4979 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
4980
4981 // ES buffer
4982 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
4983 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
4984 u32Length_main = register_lockdown->Bitstream_Len_Main;
4985 u32Length_sub = register_lockdown->Bitstream_Len_Sub;
4986
4987 MS_U32 u32StartOffset;
4988 MS_U8 u8MiuSel;
4989
4990 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
4991 u32StAddr_main = u32StartOffset;
4992
4993 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
4994 u32StAddr_sub = u32StartOffset;
4995
4996 if(u8IsHVD == 1)
4997 {
4998 //Set HVD ES Buffer address and length
4999 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5000 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5001 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(REG_HVD_BASE), HVD_LWORD(u32Length_main >> 3));
5002 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(REG_HVD_BASE), HVD_HWORD(u32Length_main >> 3));
5003
5004 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
5005 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
5006 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(REG_HVD_BASE), HVD_LWORD(u32Length_sub >> 3));
5007 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(REG_HVD_BASE), HVD_HWORD(u32Length_sub >> 3));
5008
5009 PRINTF("HVD:%x,%x,%x,%x\n",u32StAddr_main,u32Length_main,u32StAddr_sub,u32Length_sub);
5010 }
5011 else
5012 {
5013 //Set EVD ES Buffer address and length
5014 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_EVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5015 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_EVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5016 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(REG_EVD_BASE), HVD_LWORD(u32Length_main >> 3));
5017 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(REG_EVD_BASE), HVD_HWORD(u32Length_main >> 3));
5018
5019 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_EVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
5020 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_EVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
5021 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(REG_EVD_BASE), HVD_LWORD(u32Length_sub >> 3));
5022 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(REG_EVD_BASE), HVD_HWORD(u32Length_sub >> 3));
5023 PRINTF("EVD:%x,%x,%x,%x\n",u32StAddr_main,u32Length_main,u32StAddr_sub,u32Length_sub);
5024 }
5025
5026 // Lock Down
5027 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5028 //~
5029 #endif
5030 return TRUE;
5031 }
5032
5033
5034
5035
5036 #endif
5037