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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHVD.h 98 /// @brief HVD Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HVD_DEF_H_ 103 #define _DRV_HVD_DEF_H_ 104 105 #include "drvHVD_Common.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Driver Capability 109 //------------------------------------------------------------------------------------------------- 110 111 // HW capability 112 #define HVD_HW_SVD 1 113 #define HVD_HW_HVD 2 114 #if defined(CHIP_T2) 115 #define HVD_HW_VERSION HVD_HW_SVD 116 #else 117 #define HVD_HW_VERSION HVD_HW_HVD 118 #endif 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 // Feature switch 124 #if defined(REDLION_LINUX_KERNEL_ENVI) 125 #define HVD_ENABLE_MUTEX_PROTECT 0 126 #define HVD_ENABLE_MIU_RST_PROTECT 1 127 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 128 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 129 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 130 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 131 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 132 #define HVD_ENABLE_MSOS_MIU1_BASE 0 133 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 134 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 135 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 136 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 137 #define HVD_ENABLE_TIME_MEASURE 0 138 #define HVD_ENABLE_REINIT_FAILED 1 139 #define HVD_ENABLE_RV_FEATURE 0 140 #else 141 #define HVD_ENABLE_MUTEX_PROTECT 1 142 #define HVD_ENABLE_MIU_RST_PROTECT 1 143 #if 1//defined( MSOS_TYPE_LINUX) 144 #define HVD_ENABLE_AUTO_SET_REG_BASE 1 145 #else 146 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 147 #endif 148 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) 149 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 150 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 151 #else 152 #define HVD_ENABLE_PATCH_ISFRAMERDY 1 153 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 154 #endif 155 #if defined(MSOS_TYPE_NOS) && (defined(CHIP_T3) || defined(CHIP_T8) || defined(CHIP_J2)) 156 #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 157 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 158 #else 159 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 160 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 161 #endif 162 163 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 164 165 #if defined(CHIP_JANUS) 166 #define HVD_ENABLE_MSOS_MIU1_BASE 0 167 #else 168 #define HVD_ENABLE_MSOS_MIU1_BASE 1 169 #endif 170 171 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 172 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 173 #define HVD_ENABLE_TIME_MEASURE 0 174 #define HVD_ENABLE_REINIT_FAILED 0 175 176 #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) 177 #define HVD_ENABLE_RV_FEATURE 0 178 #else 179 #define HVD_ENABLE_RV_FEATURE 1 180 #endif 181 182 #if defined(CHIP_T12) || \ 183 defined(CHIP_J2) || \ 184 defined(CHIP_A1) || \ 185 defined(CHIP_A2) || \ 186 defined(CHIP_A5) || \ 187 defined(CHIP_A5P) || \ 188 defined(CHIP_A7) || \ 189 defined(CHIP_A3) || \ 190 defined(CHIP_AMETHYST)|| \ 191 defined(CHIP_AGATE) || \ 192 defined(CHIP_EDISON) || \ 193 defined(CHIP_EMERALD)|| \ 194 defined(CHIP_EAGLE) || \ 195 defined(CHIP_EIFFEL) || \ 196 defined(CHIP_NIKE) || \ 197 defined(CHIP_MADISON) || \ 198 defined(CHIP_CLIPPERS) || \ 199 defined(CHIP_MIAMI) || \ 200 defined(CHIP_NUGGET) || \ 201 defined(CHIP_KAISER) || \ 202 defined(CHIP_NIKON) || \ 203 defined(CHIP_EINSTEIN)|| \ 204 defined(CHIP_NAPOLI) || \ 205 defined(CHIP_KERES) || \ 206 defined(CHIP_MONACO) || \ 207 defined(CHIP_MUJI) || \ 208 defined(CHIP_MUNICH) || \ 209 defined(CHIP_MONET) || \ 210 defined(CHIP_MANHATTAN) || \ 211 defined(CHIP_KANO) 212 #define HVD_ENABLE_MVC 1 213 #else 214 #define HVD_ENABLE_MVC 0 215 #endif 216 217 #endif 218 219 #if defined(REDLION_LINUX_KERNEL_ENVI) 220 #include "drvHVD_redlion.h" 221 #endif 222 223 #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) 224 #include "osalHVD_EX.h" 225 #endif 226 227 #if HVD_ENABLE_MSOS_MIU1_BASE 228 #include "halCHIP.h" 229 #endif 230 231 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF 232 #include "drvBDMA.h" 233 #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) 234 #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) 235 #endif 236 237 // debug switch 238 // DEBUG 239 #if defined (REDLION_LINUX_KERNEL_ENVI) 240 #define HVD_PRINT printk 241 #define HVD_ERR printk 242 #elif defined(MSOS_TYPE_ECOS) 243 #define HVD_PRINT diag_printf 244 #define HVD_ERR diag_printf 245 #elif defined (ANDROID) 246 #include <sys/mman.h> 247 #include <cutils/ashmem.h> 248 #include <cutils/log.h> 249 #ifndef LOGI // android 4.1 rename LOGx to ALOGx 250 #define HVD_PRINT ALOGI 251 #else 252 #define HVD_PRINT LOGI 253 #endif 254 #ifndef LOGE // android 4.1 rename LOGx to ALOGx 255 #define HVD_ERR ALOGE 256 #else 257 #define HVD_ERR LOGE 258 #endif 259 #else 260 #define HVD_PRINT printf 261 #define HVD_ERR printf 262 #endif 263 264 #define HVD_EX_MSG_MUST(format, args...) \ 265 do \ 266 { \ 267 if (u32UartCtrl & E_HVD_UART_CTRL_MUST) \ 268 { \ 269 HVD_ERR("[HVD][MUST]%s:", __FUNCTION__); \ 270 HVD_ERR(format, ##args); \ 271 } \ 272 } while (0) 273 274 #define HVD_EX_MSG_ERR(format, args...) \ 275 do \ 276 { \ 277 if (u32UartCtrl & E_HVD_UART_CTRL_ERR) \ 278 { \ 279 HVD_ERR("[HVD][ERR]%s:", __FUNCTION__); \ 280 HVD_ERR(format, ##args); \ 281 } \ 282 } while (0) 283 284 #if ((defined(CHIP_A1) || defined(CHIP_A7) || defined(CHIP_AMETHYST) || defined(CHIP_EMERALD) || defined(CHIP_NUGGET) || defined(CHIP_NIKON)) && defined (__aeon__)) 285 #define HVD_EX_MSG_INF(format, args...) 286 #define HVD_EX_MSG_DBG(format, args...) 287 #define HVD_EX_MSG_TRACE() 288 #else 289 #define HVD_EX_MSG_INF(format, args...) \ 290 do \ 291 { \ 292 if (u32UartCtrl & E_HVD_UART_CTRL_INFO) \ 293 { \ 294 HVD_PRINT("[HVD][INF]%s:", __FUNCTION__); \ 295 HVD_PRINT(format, ##args); \ 296 } \ 297 } while (0) 298 299 #define HVD_EX_MSG_DBG(format, args...) \ 300 do \ 301 { \ 302 if (u32UartCtrl & E_HVD_UART_CTRL_DBG) \ 303 { \ 304 HVD_PRINT("[HVD][DBG]%s:", __FUNCTION__); \ 305 HVD_PRINT(format, ##args); \ 306 } \ 307 } while (0) 308 309 #define HVD_EX_MSG_TRACE() \ 310 do \ 311 { \ 312 if (u32UartCtrl & E_HVD_UART_CTRL_TRACE) \ 313 { \ 314 HVD_PRINT("[HVD][TRA]%s:", __FUNCTION__); \ 315 } \ 316 } while (0) 317 #endif 318 319 // Configs 320 #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks 321 #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 322 323 #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 324 325 #define H265_RBSP_BUF_LEN 1024 326 327 // Util or Functions 328 #define HVD_MIN(a,b) (((a)<(b)) ? (a) : (b)) 329 #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) 330 #define HVD_LWORD(x) (MS_U16)((x)&0xffff) 331 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) 332 #define HVD_U32_MAX 0xffffffffUL 333 #define HVD_RV_BROKENBYUS_MASK 0x00800000 334 335 #ifdef MSOS_TYPE_LINUX 336 #if HVD_ENABLE_MSOS_SYSTEM_CALL 337 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 338 #else 339 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 340 #endif 341 #else 342 #define HVD_VA2PA(x) (x) 343 #endif 344 345 #if defined(REDLION_LINUX_KERNEL_ENVI) 346 #define HVD_PA2VA(x ) (MS_VIRT)MDrv_SYS_PA2NonCacheSeg((void*)(x)) 347 #else 348 #define HVD_PA2VA(x ) (MS_VIRT)MS_PA2KSEG1((MS_VIRT)(x)) 349 #endif 350 351 // Memory alignment 352 #define MEMALIGN(N, UNIT) ((((N)+(UNIT)-1)/(UNIT))*(UNIT)) 353 354 #if 0//def memcpy 355 #define HVD_memcpy(x , y , z) memcpy(x, y, z) 356 #else 357 358 #if 0 359 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 360 do { \ 361 MS_U32 i = 0; \ 362 volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ 363 volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ 364 for (i = 0; i < (u32Size); i++) \ 365 { \ 366 Dest[i] = Src[i]; \ 367 } \ 368 }while(0) 369 #else 370 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 371 do { \ 372 register unsigned long u32I=0; \ 373 register unsigned long u32Dst = (unsigned long)pDstAddr; \ 374 void * pSrc = (void *)pSrcAddr; \ 375 MS_U32 _u32memsize = u32Size; \ 376 if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ 377 { \ 378 for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ 379 { \ 380 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 381 } \ 382 } \ 383 else \ 384 { \ 385 for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ 386 { \ 387 ((volatile unsigned int *)u32Dst)[u32I] = ((volatile unsigned int *)pSrc)[u32I]; \ 388 } \ 389 if((_u32memsize)%4) \ 390 { \ 391 u32Dst += u32I*4; \ 392 pSrc = (void *)((unsigned long)pSrc + u32I*4); \ 393 for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ 394 { \ 395 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 396 } \ 397 } \ 398 } \ 399 }while(0) 400 #endif 401 402 #endif 403 404 405 406 #if HVD_ENABLE_MSOS_SYSTEM_CALL 407 #define HVD_Delay_ms(x) MsOS_DelayTask(x) 408 #define HVD_SYSTEM_DELAY_MS_TYPE 2 409 #elif defined(REDLION_LINUX_KERNEL_ENVI) 410 #define HVD_Delay_ms(x) msleep(x) 411 //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) 412 #define HVD_SYSTEM_DELAY_MS_TYPE 3 413 #else 414 #define HVD_Delay_ms(x) \ 415 do { \ 416 volatile MS_U32 ticks=0; \ 417 while( ticks < ( ((MS_U32)(x)) <<13) ) \ 418 { \ 419 ticks++; \ 420 } \ 421 } while(0) 422 #define HVD_SYSTEM_DELAY_MS_TYPE 0 423 #endif // HVD_ENABLE_MSOS_SYSTEM_CALL 424 425 426 #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ 427 do{ \ 428 MS_U32 i = 0; \ 429 MS_U32 j = 0; \ 430 MS_U8* temp = (MS_U8*)addr; \ 431 MS_U8 string[17] ; \ 432 HVD_EX_MSG_DBG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ 433 temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ 434 memset(string , 0 , sizeof(string)); \ 435 for (j = 0; j < (size >> 4); j++) \ 436 { \ 437 if (ascii) \ 438 { \ 439 for (i = 0; i < 16; i++) \ 440 { \ 441 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 442 string[i] = *(temp + i); \ 443 else \ 444 string[i] = '.'; \ 445 } \ 446 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ 447 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ 448 } \ 449 else \ 450 { \ 451 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ 452 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ 453 } \ 454 temp += 16; \ 455 } \ 456 HVD_EX_MSG_DBG("0x%08x " , j << 4); \ 457 memset(string , 0 , sizeof(string)); \ 458 for (i = 0; i < (size & 0x0f); i++) \ 459 { \ 460 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 461 string[i] = *(temp + i); \ 462 else \ 463 string[i] = '.'; \ 464 HVD_EX_MSG_DBG("%02x ", *(MS_U8*)(temp + i)); \ 465 } \ 466 if (ascii) \ 467 { \ 468 for (; i < 16 ; i++) \ 469 HVD_EX_MSG_DBG(" "); \ 470 HVD_EX_MSG_DBG(" %s\n" , string); \ 471 } \ 472 else \ 473 HVD_EX_MSG_DBG("\n"); \ 474 }while(0) 475 476 477 #if HVD_ENABLE_MSOS_SYSTEM_CALL 478 #define HVD_GetSysTime_ms() MsOS_GetSystemTime() 479 #define HVD_SYSTEM_CLOCK_TYPE 1 480 #elif defined(REDLION_LINUX_KERNEL_ENVI) 481 #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() 482 #define HVD_SYSTEM_CLOCK_TYPE 2 483 #else 484 #define HVD_GetSysTime_ms() 1 485 #define HVD_SYSTEM_CLOCK_TYPE 0 486 #endif // MsOS_GetSystemTime 487 488 #if HVD_ENABLE_MSOS_SYSTEM_CALL 489 #include "asmCPU.h" 490 #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() 491 #define HVD_MEMORY_BARRIER_TYPE 3 492 #else 493 #if defined (__mips__) 494 #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") 495 #define HVD_MEMORY_BARRIER_TYPE 1 496 #elif defined (__aeon__) 497 #ifdef __AEONR2__ 498 #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") 499 #define HVD_MEMORY_BARRIER_TYPE 22 500 #else 501 #if defined( CHIP_T2 ) 502 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") 503 #define HVD_MEMORY_BARRIER_TYPE 21 504 #else 505 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") 506 #define HVD_MEMORY_BARRIER_TYPE 23 507 #endif 508 #endif 509 #else 510 #define HAL_MEMORY_BARRIER() 511 #define HVD_MEMORY_BARRIER_TYPE 0 512 #endif 513 #endif 514 515 #define HVD_DRV_MODE_EXTERNAL_DS_BUFFER (1 << 0) 516 517 //------------------------------------------------------------------------------------------------- 518 // Type and Structure 519 //------------------------------------------------------------------------------------------------- 520 typedef void (*HVD_ISRCallBack)(MS_U32 u32Sid); 521 522 typedef enum 523 { 524 E_HVD_RETURN_FAIL=0, 525 E_HVD_RETURN_SUCCESS, 526 E_HVD_RETURN_INVALID_PARAMETER, 527 E_HVD_RETURN_ILLEGAL_ACCESS, 528 E_HVD_RETURN_HARDWARE_BREAKDOWN, 529 E_HVD_RETURN_OUTOF_MEMORY, 530 E_HVD_RETURN_UNSUPPORTED, 531 E_HVD_RETURN_TIMEOUT, 532 E_HVD_RETURN_NOTREADY, 533 E_HVD_RETURN_MEMORY_OVERWIRTE, 534 E_HVD_RETURN_ES_FULL, 535 E_HVD_RETURN_RE_INIT, 536 E_HVD_RETURN_NOT_RUNNING, 537 } HVD_Return; 538 539 typedef enum 540 { 541 // share memory 542 E_HVD_GDATA_SHARE_MEM=0x1000, 543 // switch 544 //E_HVD_GDATA_SEMAPHORE, 545 E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), 546 E_HVD_GDATA_MIU_SEL, 547 E_HVD_GDATA_FRAMEBUF_ADDR, 548 E_HVD_GDATA_FRAMEBUF_SIZE, 549 E_HVD_GDATA_FRAMEBUF2_ADDR, 550 E_HVD_GDATA_FRAMEBUF2_SIZE, 551 E_HVD_GDATA_CMA_USED, 552 E_HVD_GDATA_CMA_ALLOC_DONE, 553 // report 554 E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), 555 E_HVD_GDATA_U64PTS, 556 E_HVD_GDATA_DECODE_CNT, 557 E_HVD_GDATA_DATA_ERROR_CNT, 558 E_HVD_GDATA_DEC_ERROR_CNT, 559 E_HVD_GDATA_ERROR_CODE, 560 E_HVD_GDATA_VPU_IDLE_CNT, 561 E_HVD_GDATA_DISP_FRM_INFO, 562 E_HVD_GDATA_DEC_FRM_INFO, 563 E_HVD_GDATA_ES_LEVEL, 564 E_HVD_GDATA_PTS_STC_DIFF, 565 #if HVD_ENABLE_MVC 566 E_HVD_GDATA_DISP_FRM_INFO_SUB, 567 E_HVD_GDATA_DEC_FRM_INFO_SUB, 568 #endif 569 E_HVD_GDATA_HVD_HW_MAX_PIXEL, 570 E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS, 571 E_HVD_GDATA_TS_SEAMLESS_TARGET_POC, 572 573 // user data 574 E_HVD_GDATA_USERDATA_WPTR, 575 E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, 576 E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, 577 E_HVD_GDATA_USERDATA_PACKET_SIZE, 578 E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, 579 E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, 580 // report - modes 581 E_HVD_GDATA_IS_SHOW_ERR_FRM, 582 E_HVD_GDATA_IS_REPEAT_LAST_FIELD, 583 E_HVD_GDATA_IS_ERR_CONCEAL, 584 E_HVD_GDATA_IS_SYNC_ON, 585 E_HVD_GDATA_IS_PLAYBACK_FINISH, 586 E_HVD_GDATA_SYNC_MODE, 587 E_HVD_GDATA_SKIP_MODE, 588 E_HVD_GDATA_DROP_MODE, 589 E_HVD_GDATA_DISPLAY_DURATION, 590 E_HVD_GDATA_FRC_MODE, 591 E_HVD_GDATA_NEXT_PTS, 592 E_HVD_GDATA_DISP_Q_SIZE, 593 E_HVD_GDATA_DISP_Q_PTR, 594 E_HVD_GDATA_NEXT_DISP_FRM_INFO, 595 E_HVD_GDATA_REAL_FRAMERATE, 596 E_HVD_GDATA_IS_ORI_INTERLACE_MODE, 597 E_HVD_GDATA_FRM_PACKING_SEI_DATA, 598 E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, 599 E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE, 600 E_HVD_GDATA_FIELD_PIC_FLAG, 601 E_HVD_GDATA_FW_STATUS_FLAG, 602 E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT, 603 E_HVD_GDATA_DISPLAYCOLOURVOLUME_SEI_DATA, 604 E_HVD_GDATA_U64PTS_PRE_PARSE, 605 E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO, 606 607 // internal control 608 E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), 609 E_HVD_GDATA_IS_I_FRM_FOUND, 610 E_HVD_GDATA_IS_SYNC_START, 611 E_HVD_GDATA_IS_SYNC_REACH, 612 E_HVD_GDATA_FW_VERSION_ID, 613 E_HVD_GDATA_FW_IF_VERSION_ID, 614 E_HVD_GDATA_BBU_Q_NUMB, 615 E_HVD_GDATA_DEC_Q_NUMB, 616 E_HVD_GDATA_DISP_Q_NUMB, 617 E_HVD_GDATA_PTS_Q_NUMB, 618 E_HVD_GDATA_FW_INIT_DONE, 619 E_HVD_GDATA_FW_IS_IQMEM_SUPPORT, 620 E_HVD_GDATA_FW_IQMEM_CTRL, 621 E_HVD_GDATA_FW_FLUSH_STATUS, 622 E_HVD_GDATA_FW_CODEC_TYPE, 623 E_HVD_GDATA_FW_ES_BUF_STATUS, 624 E_HVD_GDATA_TS_SEAMLESS_STATUS, 625 E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG, 626 E_HVD_GDATA_GET_NOT_SUPPORT_INFO, 627 E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE, 628 629 // debug 630 E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), 631 E_HVD_GDATA_GOP_CNT, 632 E_HVD_GDATA_DISP_CNT, 633 E_HVD_GDATA_DROP_CNT, 634 E_HVD_GDATA_DISP_STC, 635 E_HVD_GDATA_VSYNC_CNT, 636 E_HVD_GDATA_MAIN_LOOP_CNT, 637 // AVC 638 E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), 639 E_HVD_GDATA_AVC_LOW_DELAY, 640 E_HVD_GDATA_AVC_VUI_DISP_INFO, 641 //E_HVD_GDATA_AVC_SPS_ADDR, 642 643 // SRAM 644 E_HVD_GDATA_SRAM=0x2000, 645 //E_HVD_GDATA_AVC_NAL_CNT, 646 647 // Mailbox or Reg 648 E_HVD_GDATA_MBOX=0x3000, 649 E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) 650 E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) 651 E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) 652 E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) 653 E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) 654 E_HVD_GDATA_ES_READ_PTR, // 655 E_HVD_GDATA_ES_WRITE_PTR, // 656 E_HVD_GDATA_BBU_READ_PTR, // 657 E_HVD_GDATA_BBU_WRITE_PTR, // 658 E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // 659 E_HVD_GDATA_VPU_PC_CNT, // 660 E_HVD_GDATA_ES_QUANTITY, 661 662 // FW def 663 E_HVD_GDATA_FW_DEF=0x4000, 664 E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? 665 E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, 666 E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, 667 E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, 668 E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, 669 E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, 670 E_HVD_GDATA_FW_DS_BUF_ADDR, 671 E_HVD_GDATA_FW_DS_BUF_SIZE, 672 E_HVD_GDATA_FW_DS_VECTOR_DEPTH, 673 E_HVD_GDATA_FW_DS_INFO_ADDR, 674 E_HVD_GDATA_FW_DS_IS_ENABLED, 675 E_HVD_GDATA_FW_VSYNC_BRIDGE_ADDR, 676 #ifdef VDEC3 677 E_HVD_GDATA_FW_VBBU_ADDR, 678 #endif 679 // BBU size 680 // default pitch number 681 // 682 } HVD_GetData; 683 684 typedef enum 685 { 686 // share memory 687 E_HVD_SDATA_SHARE_MEM = 0x1000, 688 // switch 689 E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100 + E_HVD_SDATA_SHARE_MEM), 690 E_HVD_SDATA_FRAMEBUF_SIZE, 691 E_HVD_SDATA_ERROR_CODE, 692 E_HVD_SDATA_DISP_INFO_TH, 693 E_HVD_SDATA_FW_FLUSH_STATUS, 694 E_HVD_SDATA_DMX_FRAMERATE, 695 E_HVD_SDATA_DMX_FRAMERATEBASE, 696 E_HVD_SDATA_MIU_SEL, 697 E_HVD_SDATA_FRAMEBUF2_ADDR, 698 E_HVD_SDATA_FRAMEBUF2_SIZE, 699 E_HVD_SDATA_CMA_USED, 700 E_HVD_SDATA_CMA_ALLOC_DONE, 701 E_HVD_SDATA_CMA_TWO_MIU, 702 E_HVD_SDATA_DV_XC_SHM_SIZE, 703 // display info 704 //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), 705 // report 706 //E_HVD_SDATA_PTS=0x0200, 707 // internal control 708 //E_HVD_SDATA_IDLE_CNT=0x0300, 709 // debug 710 //E_HVD_SDATA_SKIP_CNT=0x0400, 711 // RM 712 E_HVD_SDATA_RM_PICTURE_SIZES = (0x0500 | E_HVD_SDATA_SHARE_MEM), 713 714 // SRAM 715 // Mailbox or Reg 716 E_HVD_SDATA_MAILBOX = 0x3000, 717 E_HVD_SDATA_FW_CODE_TYPE = (0x0000 | E_HVD_SDATA_MAILBOX), 718 E_HVD_SDATA_TRIGGER_DISP, 719 E_HVD_SDATA_GET_DISP_INFO_DONE, 720 E_HVD_SDATA_GET_DISP_INFO_START, 721 722 // FW def 723 E_HVD_SDATA_FW_DEF = 0x4000, 724 E_HVD_SDATA_VIRTUAL_BOX_WIDTH, 725 E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, 726 //modify the state of the frame in DispQueue 727 E_HVD_SDATA_DISPQ_STATUS_VIEW, 728 E_HVD_SDATA_DISPQ_STATUS_DISP, 729 E_HVD_SDATA_DISPQ_STATUS_FREE, 730 E_HVD_SDATA_FW_IQMEM_CTRL, 731 E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, 732 E_HVD_SDATA_DV_INFO, 733 } HVD_SetData; 734 735 typedef enum 736 { 737 E_HVD_UART_CTRL_DISABLE = BIT(4), 738 E_HVD_UART_CTRL_ERR = BIT(0), 739 E_HVD_UART_CTRL_INFO = BIT(1), 740 E_HVD_UART_CTRL_DBG = BIT(2), 741 E_HVD_UART_CTRL_FW = BIT(3), 742 E_HVD_UART_CTRL_MUST = BIT(4), 743 E_HVD_UART_CTRL_TRACE = BIT(5), 744 } HVD_Uart_Ctrl; 745 746 typedef enum 747 { 748 E_HVD_INIT_HW_MASK = BMASK(3:0), ///< HW Type, should same as HVD_Codec_Type in fwHVD_if.h 749 E_HVD_INIT_HW_AVC = BITS(3:0, 0), ///< HW deflaut: AVC 0X00 750 E_HVD_INIT_HW_AVS = BITS(3:0, 1), ///< HW: AVS 0X01 751 E_HVD_INIT_HW_RM = BITS(3:0, 2), ///< HW: RM 0X10 752 E_HVD_INIT_HW_MVC = BITS(3:0, 3), ///< HW: MVC 0x11 753 E_HVD_INIT_HW_VP8 = BITS(3:0, 4), ///< HW: VP8 0X100 754 E_HVD_INIT_HW_MJPEG = BITS(3:0, 5), ///< HW: MJPEG 0x101 755 E_HVD_INIT_HW_VP6 = BITS(3:0, 6), ///< HW: VP6 0x110 756 E_HVD_INIT_HW_HEVC = BITS(3:0, 7), ///< HW: HEVC 0x111 757 E_HVD_INIT_HW_VP9 = BITS(3:0, 8), ///< HW: VP9 0x1000 758 E_HVD_INIT_MAIN_MASK = BMASK(5:4), ///< main type 759 E_HVD_INIT_MAIN_FILE_RAW = BITS(5:4, 0), ///< main type: default: 0X00 760 E_HVD_INIT_MAIN_FILE_TS = BITS(5:4, 1), ///< main type: 0X01 761 E_HVD_INIT_MAIN_LIVE_STREAM = BITS(5:4, 2), ///< main type: 0X10 762 E_HVD_INIT_INPUT_MASK = BMASK(6:6), ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode 763 E_HVD_INIT_INPUT_TSP = BITS(6:6, 0), ///< tsp input( default) 764 E_HVD_INIT_INPUT_DRV = BITS(6:6, 1), ///< driver input 765 E_HVD_INIT_START_CODE_MASK = BMASK(7:7), ///< AVC FILE MODE ONLY: mkv, mp4 container use. 766 E_HVD_INIT_START_CODE_REMAINED = BITS(7:7, 0), ///< start code remained.(Defualt) 767 E_HVD_INIT_START_CODE_REMOVED = BITS(7:7, 1), ///< start code removed. 768 E_HVD_INIT_UTOPIA_ENVI = BIT(8), ///< check MIU sel and set it 769 E_HVD_INIT_DBG_FW = BIT(9), ///< check FW is debug version or not 770 E_HVD_INIT_DUAL_ES_MASK = BMASK(10:10), ///< Dual ES buffer iput. 771 E_HVD_INIT_DUAL_ES_DISABLE = BITS(10:10, 0), ///< Disable Dual ES buffer input. 772 E_HVD_INIT_DUAL_ES_ENABLE = BITS(10:10, 1), ///< Enable Dual ES buffer input. 773 //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. 774 } HVD_Init_Mode_Flag; 775 776 typedef enum 777 { 778 E_HVD_PLAY_NORMAL, 779 E_HVD_PLAY_PAUSE, 780 E_HVD_PLAY_STEP_DISPLAY, 781 } HVD_Play_Type; 782 783 typedef enum 784 { 785 E_HVD_ESB_LEVEL_NORMAL = 0, 786 E_HVD_ESB_LEVEL_UNDER = BIT(0), 787 E_HVD_ESB_LEVEL_OVER = BIT(1), 788 } HVD_ESBuf_Level; 789 790 //----------------------------------------------------------------------------- 791 /// @brief \b Enum \b Name: HVD_FWInputSourceType 792 /// @brief \b Enum \b Description: The type of fw binary input source 793 //----------------------------------------------------------------------------- 794 typedef enum 795 { 796 E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. 797 E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. 798 E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. 799 } HVD_FWInputSourceType; 800 801 //----------------------------------------------------------------------------- 802 /// @brief \b Enum \b Name: HVD_FB_Reduction_Type 803 /// @brief \b Enum \b Description: The type of frame buffer reduction type 804 //----------------------------------------------------------------------------- 805 typedef enum 806 { 807 E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable 808 E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 809 E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 810 } HVD_FBReductionType; 811 812 typedef enum 813 { 814 E_VDEC_EX_MAIN_VIEW = 0, ///< MVC main view 815 E_VDEC_EX_SUB_VIEW, ///< MVC sub view 816 } VDEC_EX_View; 817 818 typedef enum 819 { 820 E_HVD_SECURE_MODE_NONE = 0, /// None secure 821 E_HVD_SECURE_MODE_TRUSTZONE /// Secure for TrustZone 822 } HVD_SECURE_MODE; 823 824 typedef enum 825 { 826 E_HWDEC_ISR_NONE = 0, 827 E_HWDEC_ISR_HVD = 1, // For HW Decoder check 828 E_HWDEC_ISR_EVD = 2, 829 E_HWDEC_ISR_G2VP9 = 3, 830 E_HWDEC_ISR_EVDLITE = 4, 831 } HWDEC_ISR_TYPE; 832 833 //HVD set MFcodec Mode 834 typedef enum 835 { 836 E_HVD_DEF_MFCODEC_DEFAULT = 0, 837 E_HVD_DEF_MFCODEC_FORCE_ENABLE, 838 E_HVD_DEF_MFCODEC_FORCE_DISABLE, 839 } HVD_MFCodec_mode; 840 841 //HVD set Display Mode 842 typedef enum 843 { 844 E_HVD_DISPLAY_MODE_DEFAULT, 845 E_HVD_DISPLAY_MODE_MCU, 846 E_HVD_DISPLAY_MODE_HARDWIRE, 847 }HVD_Display_mode; 848 849 typedef enum 850 { 851 E_HVD_DEF_FEATURE_DEFAULT = 0, 852 E_HVD_DEF_FEATURE_FORCE_MAIN_PROFILE = 1, //BIT0=1: HEVC Only support Main profile decode 853 } HVD_Feature; 854 855 typedef enum 856 { 857 // Indicates Dolby Vision stream profile is Unsupported. 858 E_DV_STREAM_PROFILE_ID_UNSUPPORTED = 0x0, 859 // Indicates Dolby Vision stream profile is "dvav.per". 860 E_DV_STREAM_PROFILE_ID_DVAV_PER = 0x1, 861 // Indicates Dolby Vision stream profile is "dvav.pen". 862 E_DV_STREAM_PROFILE_ID_DVAV_PEN = 0x2, 863 // Indicates Dolby Vision stream profile is "dvhe.der". 864 E_DV_STREAM_PROFILE_ID_DVHE_DER = 0x4, 865 // Indicates Dolby Vision stream profile is "dvhe.den". 866 E_DV_STREAM_PROFILE_ID_DVHE_DEN = 0x8, 867 // Indicates Dolby Vision stream profile is "dvhe.dtr". 868 E_DV_STREAM_PROFILE_ID_DVHE_DTR = 0x10, 869 // Indicates Dolby Vision stream profile is "dvhe.stn". 870 E_DV_STREAM_PROFILE_ID_DVHE_STN = 0x20, 871 // Indicates Dolby Vision stream profile is "dvhe.dth". 872 E_DV_STREAM_PROFILE_ID_DVHE_DTH = 0x40, 873 } DV_Stream_Profile; 874 875 typedef enum 876 { 877 // Indicates Dolby Vision stream level is unsupported. 878 E_DV_STREAM_LEVEL_ID_UNSUPPORTED = 0, 879 // Indicates Dolby Vision stream level is "HD24". 880 E_DV_STREAM_LEVEL_ID_HD24, 881 // Indicates Dolby Vision stream level is "HD30". 882 E_DV_STREAM_LEVEL_ID_HD30, 883 // Indicates Dolby Vision stream level is "FHD24". 884 E_DV_STREAM_LEVEL_ID_FHD24, 885 // Indicates Dolby Vision stream level is "FHD30". 886 E_DV_STREAM_LEVEL_ID_FHD30, 887 // Indicates Dolby Vision stream level is "FHD60". 888 E_DV_STREAM_LEVEL_ID_FHD60, 889 // Indicates Dolby Vision stream level is "UHD24". 890 E_DV_STREAM_LEVEL_ID_UHD24, 891 // Indicates Dolby Vision stream level is "UHD30". 892 E_DV_STREAM_LEVEL_ID_UHD30, 893 // Indicates Dolby Vision stream level is "UHD48". 894 E_DV_STREAM_LEVEL_ID_UHD48, 895 // Indicates Dolby Vision stream level is "UHD60". 896 E_DV_STREAM_LEVEL_ID_UHD60, 897 } DV_Stream_Level; 898 899 //----------------------------------------------------------------------------- 900 /// @brief \b Struct \b Name: HVD_EX_MemMap 901 /// @brief \b Struct \b Description: Store the HVD driver config 902 //----------------------------------------------------------------------------- 903 typedef struct 904 { 905 MS_PHY u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. 906 MS_PHY u32MIU2BaseAddr; //!< the physical memory start address of MIU 2 base address. 0: default value. 907 MS_VIRT u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM 908 MS_PHY u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. 909 MS_U32 u32FWBinarySize; //!< the FW code size 910 MS_VIRT u32VLCBinaryVAddr; //!< VLC table binary data buffer start address 911 MS_PHY u32VLCBinaryAddr; //!< VLC table binary data buffer start address 912 MS_U32 u32VLCBinarySize; //!<VLC table binary data buffer size 913 MS_VIRT u32CodeBufVAddr; //!< the virtual memory start address of code buffer 914 MS_PHY u32CodeBufAddr; //!< the physical memory start address of code buffer 915 MS_U32 u32CodeBufSize; //!< the code buffer size 916 MS_VIRT u32FrameBufVAddr; //!< the virtual memory start address of frame buffer 917 MS_PHY u32FrameBufAddr; //!< the physical memory start address of frame buffer 918 MS_U32 u32FrameBufSize; //!< the frame buffer size 919 MS_VIRT u32BitstreamBufVAddr; //!< the virtual memory start address of bit stream buffer 920 MS_PHY u32BitstreamBufAddr; //!< the physical memory start address of bit stream buffer 921 MS_U32 u32BitstreamBufSize; //!< the bit stream buffer size 922 MS_VIRT u32DrvProcessBufVAddr; //!< the virtual memory start address of driver process buffer 923 MS_PHY u32DrvProcessBufAddr; //!< the physical memory start address of driver process buffer 924 MS_U32 u32DrvProcessBufSize; //!< the driver process buffer size 925 MS_VIRT u32DynSacalingBufVAddr; //!< the virtual memory start address of dynamic scaling buffer 926 MS_PHY u32DynSacalingBufAddr; //!< the physical memory start address of dynamic scaling buffer 927 MS_U32 u32DynSacalingBufSize; //!< the dynamic scaling buffer size 928 HVD_FWInputSourceType eFWSourceType; //!< the input FW source type. 929 #ifdef VDEC3 930 MS_PHY u32TotalBitstreamBufAddr; 931 MS_U32 u32TotalBitstreamBufSize; 932 #endif 933 } HVD_EX_MemMap; 934 935 //----------------------------------------------------------------------------- 936 /// @brief \b Struct \b Name: HVD_Nal_Entry 937 /// @brief \b Struct \b Description: Store the information of one nal entry 938 //----------------------------------------------------------------------------- 939 typedef struct 940 { 941 MS_U32 u32NalID; ///< the ID nunber of this nal 942 MS_VIRT u32NalAddr; ///< the offset of this nal from bit stream buffer start address. unit: byte 943 MS_U32 u32NalSize; ///< the size of this nal. unit: byte 944 MS_U32 u32NalPTS; ///< the time stamp of this nal. unit: ms 945 MS_BOOL bRVBrokenPacket; ///< the RV only 946 } HVD_Nal_Entry; 947 948 //----------------------------------------------------------------------------- 949 /// @brief \b Struct \b Name: RV_FileInfo 950 /// @brief \b Struct \b Description: RV file information 951 //----------------------------------------------------------------------------- 952 typedef struct 953 { 954 MS_U16 RV_Version; ///< Real Video Bitstream version 955 MS_U16 ulNumSizes; ///< Real Video Number sizes 956 MS_U16 ulPicSizes_w[8]; ///< Real Video file width 957 MS_U16 ulPicSizes_h[8]; ///< Real Video file height 958 } RV_FileInfo; 959 960 //----------------------------------------------------------------------------- 961 /// @brief \b Struct \b Name: HVD_FB_Reduction_Mode 962 /// @brief \b Struct \b Description: Set up frame buffer reduction mode 963 //----------------------------------------------------------------------------- 964 typedef struct 965 { 966 HVD_FBReductionType eLumaFBReductionMode; ///< Luma frame buffer reduction mode. 967 HVD_FBReductionType eChromaFBReductionMode; ///< Chroma frame buffer reduction mode. 968 MS_U8 u8EnableAutoMode; /// 0: Disable, 1: Enable 969 } HVD_FBReductionMode; 970 971 //----------------------------------------------------------------------------- 972 /// @brief \b Struct \b Name: HVD_Init_Params 973 /// @brief \b Struct \b Description: Store the initialization settings 974 //----------------------------------------------------------------------------- 975 typedef struct 976 { 977 MS_U32 u32ModeFlag; ///< init mode flag, use HVD_INIT_* to setup HVD. 978 MS_U32 u32FrameRate; ///< frame rate. 979 MS_U32 u32FrameRateBase; ///< frame rate base. The value of u32FrameRate /u32FrameRateBase must be frames per sec. 980 MS_U8 u8MinFrmGap; ///< set the min frame gap. 981 MS_U8 u8SyncType; ///< HVD_EX_SyncType. sync type of current playback. 982 MS_U16 u16Pitch; ///< not zero: specify the pitch. 0: use default value. 983 MS_U32 u32MaxDecTick; ///< not zero: specify the max decode tick. 0: use default value. 984 MS_BOOL bSyncEachFrm; ///< TRUE: sync STC at each frame. FALSE: not sync each frame. 985 MS_BOOL bAutoFreeES; ///< TRUE: auto free ES buffer when ES buffer is full. FALSE: not do the auto free. 986 MS_BOOL bAutoPowerSaving; ///< TRUE: auto power saving. FALSE: not do the auto power saving. 987 MS_BOOL bDynamicScaling; ///< TRUE: enable Dynamic Scaling. FALSE: disable Dynamic Scaling. 988 MS_BOOL bFastDisplay; ///< TRUE: enable Fast Display. FALSE: disable Fast Display. 989 MS_BOOL bUserData; ///< TRUE: enable processing User data. FALSE: disable processing User data. 990 MS_U8 u8TurboInit; ///< HVD_TurboInitLevel. set the turbo init mode. 991 MS_U8 u8TimeUnit; ///< HVD_Time_Unit_Type.set the type of input/output time unit. 992 MS_U16 u16DecoderClock; ///< HVD decoder clock speed. 0: default value. non-zero: any nearist clock. 993 MS_U16 u16ChipECONum; ///< Chip revision, ECO number. 994 RV_FileInfo* pRVFileInfo; ///< pointer to RV file info 995 HVD_FBReductionMode stFBReduction; ///< HVD Frame buffer reduction type 996 } HVD_Init_Params; 997 998 //----------------------------------------------------------------------------- 999 /// @brief \b Struct \b Name: HVD_BBU_Info 1000 /// @brief \b Struct \b Description: Store the packet information 1001 //----------------------------------------------------------------------------- 1002 typedef struct 1003 { 1004 MS_VIRT u32Staddr; ///< Packet offset from bitstream buffer base address. unit: byte. 1005 MS_U32 u32Length; ///< Packet size. unit: byte. 1006 MS_VIRT u32Staddr2; ///< Packet offset from bitstream buffer base address. unit: byte. 1007 MS_U32 u32Length2; ///< Packet size. unit: byte. 1008 MS_U32 u32TimeStamp; ///< Packet time stamp. unit: ms. 1009 MS_U32 u32ID_L; ///< Packet ID low part. 1010 MS_U32 u32ID_H; ///< Packet ID high part. 1011 MS_U32 u32AllocLength; ///< Allocated Packet size. unit: byte. 1012 MS_U32 u32OriPktAddr; ///< Original packet offset from bitstream buffer base address. unit: byte. 1013 MS_BOOL bRVBrokenPacket; ///< the RV only 1014 } HVD_BBU_Info; 1015 1016 //----------------------------------------------------------------------------- 1017 /// @brief \b Struct \b Name: HVD_Alive_Status 1018 /// @brief \b Struct \b Description: Store the decoder living information 1019 //----------------------------------------------------------------------------- 1020 typedef struct 1021 { 1022 MS_U32 u32DecCnt; 1023 MS_U32 u32SkipCnt; 1024 MS_U32 u32IdleCnt; 1025 MS_U32 u32MainLoopCnt; 1026 } HVD_Alive_Status; 1027 1028 //----------------------------------------------------------------------------- 1029 /// @brief \b Struct \b Name: HVD_DISP_INFO_THRESHOLD 1030 /// @brief \b Struct \b Description: Store the disp information threshold. 1031 //----------------------------------------------------------------------------- 1032 typedef struct 1033 { 1034 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 1035 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 1036 MS_U32 u32MvopUpBound; //mvop filter upper bound 1037 MS_U32 u32MvopLowBound; //mvop filter lower bound 1038 } HVD_Disp_Info_TH; 1039 1040 //----------------------------------------------------------------------------- 1041 /// @brief \b Struct \b Name: HVD_Settings 1042 /// @brief \b Struct \b Description: Store the settings of user requirment 1043 //----------------------------------------------------------------------------- 1044 typedef struct 1045 { 1046 // TODO: currently only DTV settings. Need to add more settings for MM. 1047 // Mode 1048 HVD_Disp_Info_TH DispInfoTH; 1049 MS_U32 u32IsrEvent; 1050 MS_BOOL bEnISR; 1051 1052 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 1053 MS_U8 bIsShowErrFrm; 1054 MS_U8 u8FrcMode; //HVD_EX_FrmRateConvMode 1055 1056 MS_BOOL bIsErrConceal; 1057 MS_BOOL bAutoFreeES; 1058 MS_BOOL bDisDeblocking; 1059 MS_BOOL bDisQuarterPixel; 1060 1061 MS_U8 bIsSyncOn; 1062 MS_U32 u32SyncTolerance; 1063 MS_U32 u32SyncRepeatTH; 1064 MS_U32 u32SyncVideoDelay; 1065 MS_U32 u32SyncFreeRunTH; 1066 MS_U32 u32MiuBurstLevel; 1067 } HVD_Settings; 1068 1069 //----------------------------------------------------------------------------- 1070 /// @brief \b Struct \b Name: HVD_CC_Info 1071 /// @brief \b Struct \b Description: HVD Close Caption Infomation. 1072 //----------------------------------------------------------------------------- 1073 typedef struct 1074 { 1075 MS_U8 u8UserDataMode; 1076 MS_U8 u8ParsingStatus; 1077 MS_BOOL b708Enable; 1078 MS_BOOL b608InfoEnhance; 1079 //MS_BOOL bBufMiu1[2]; 1080 MS_U8 u8BufMiuSel[2]; 1081 MS_BOOL bOverFlow[2]; 1082 MS_PHY u32RingBufStartPAddr[2];//physical address 1083 MS_U32 u32RingBufLen[2]; 1084 MS_U32 volatile u32RingBufVacancy[2]; 1085 MS_PHY volatile u32RingBufRPAddr[2], u32RingBufWPAddr[2];//physical address 1086 MS_U32 volatile u32FWUsrDataRIdx, u32FWUsrDataWIdx; 1087 MS_U32 u32PktLen708; 1088 MS_VIRT u32PktHdrAddr708; 1089 MS_U8 u8CC608buf[512]; 1090 MS_U8 u8CC708buf[512]; 1091 } HVD_CC_Info; 1092 1093 typedef struct 1094 { 1095 MS_U16 u16TmpRef; 1096 MS_U16 u16PicStruct; 1097 MS_U32 u32Pts; 1098 MS_U8 u8UsrDataCnt; 1099 } HVD_CC_608EnhanceInfo; 1100 1101 1102 //----------------------------------------------------------------------------- 1103 /// @brief \b Struct \b Name: HVD_ISR_Ctrl 1104 /// @brief \b Struct \b Description: HVD driver ISR control. 1105 //----------------------------------------------------------------------------- 1106 typedef struct 1107 { 1108 MS_BOOL bRegISR; 1109 MS_BOOL bInISR; 1110 MS_U32 u32ISRInfo; 1111 MS_U32 u32IntCount; 1112 HVD_ISRCallBack pfnISRCallBack; 1113 MS_BOOL bDisableISRFlag; 1114 MS_BOOL bIsHvdIsr; 1115 MS_BOOL bIsG2Vp9Isr; 1116 HWDEC_ISR_TYPE eHWDecIsr; //HVD, EVD, G2VP9 ISR 1117 } HVD_ISR_Ctrl; 1118 1119 //----------------------------------------------------------------------------- 1120 /// @brief \b Struct \b Name: HVD_EX_Drv_Ctrl 1121 /// @brief \b Struct \b Description: HVD driver internal control. 1122 //----------------------------------------------------------------------------- 1123 typedef struct 1124 { 1125 // init stage 1126 MS_BOOL bUsed; 1127 HVD_EX_MemMap MemMap; ///< HVD memory config 1128 HVD_Init_Params InitParams; ///< HVD init settings 1129 MS_BOOL bNoDrvProccBuf; 1130 MS_BOOL bAutoRmLastZeroByte; 1131 MS_BOOL bCannotAccessMIU256; 1132 MS_U32 u32CmdTimeout; ///< HVD FW command timeout 1133 void *pLastFrmInfo; 1134 void *pLastFrmInfo_ext; 1135 1136 // reset stage 1137 MS_U32 u32CtrlMode; ///< HVD run-time control flag 1138 MS_U32 u32DummyWriteBuf; ///< For dummy write MIU action. 1139 //MS_U32 u32CPUNonCacheMask; ///< CPU non-cache mask 1140 MS_U32 u32NULLPacketSize; ///< to store the size of AVI null packet pattern 1141 MS_VIRT u32NULLPacketAddr; ///< to store the start address of AVI null packet pattern from bitstream buffer base. 1142 MS_U32 u32RV_FlushPacketSize; ///< to store the size of rm flush packet pattern 1143 MS_U32 u32RV_FlushPacketAddr; ///< to store the start address of rm flush packet pattern from bitstream buffer base. 1144 MS_U32 u32StepDecodeCnt; 1145 //MS_U32 u32LastBBUPTS; 1146 //MS_U32 u32DummyDataSize; ///< buffer size of dummy data. 1147 //MS_U32 u32RestSizeofPushDummy; 1148 //MS_U32 u32AddrPushDummy; 1149 MS_U32 u32LastESRptr; 1150 MS_U32 u32BBUTblInBitstreamBufAddr; 1151 MS_U32 u32BBUPacketCnt; 1152 MS_U32 u32BBUWptr_Fired; 1153 MS_U32 u32LastErrCode; 1154 //MS_BOOL bPushingDummy; 1155 MS_BOOL bIsDispInfoChg; 1156 MS_BOOL bFrmRateSupported; 1157 HVD_Nal_Entry LastNal; 1158 HVD_Alive_Status LivingStatus; 1159 1160 // recovery stage 1161 MS_BOOL bStepDecoding; 1162 HVD_Settings Settings; 1163 1164 MS_U8 bTurboFWMode; //TRUE:not reload FW more than once if pre-decoder is the same. 1165 1166 // ISR control 1167 HVD_ISR_Ctrl HVDISRCtrl; 1168 MS_U32 u32Sid; // stream ID 1169 1170 // user data 1171 MS_U32 u32UsrDataRd; 1172 MS_U32 u32UsrDataWr; 1173 HVD_CC_Info CloseCaptionInfo; 1174 1175 MS_U32 u32FlushRstPtr; ///< flush rst ptr: 0: init, 1:after flush and before push packet 1176 1177 // Secure Mode 1178 MS_U8 u8SecureMode; // Enum HVD_SECURE_MODE 1179 MS_U8 u8SettingMode; // Record Setting mode 1180 MS_U8 u8Resv[2]; 1181 MS_U32 u32ExternalDSbuf; // External DS buffer 1182 MS_U8 u8CodeMiuSel; 1183 MS_U8 u8ESMiuSel; 1184 MS_U8 u8FrmMiuSel; 1185 MS_U8 u8Frm2MiuSel; 1186 MS_U8 u8DrvProccMiuSel; 1187 #ifdef VDEC3 1188 MS_BOOL bNStreamMode; 1189 MS_U32 u32BBUId; 1190 #endif 1191 MS_BOOL bDirectSTCModeEnabled; 1192 } HVD_EX_Drv_Ctrl; 1193 1194 typedef void(*P_SC_ISR_Proc)(MS_U8 u8SCID); 1195 1196 typedef struct 1197 { 1198 MS_BOOL bEnable; 1199 MS_U32 u32IapGnBufAddr; 1200 MS_U32 u32IapGnBufSize; 1201 } HVD_EX_IapGnBufShareBWMode; 1202 1203 typedef struct 1204 { 1205 MS_BOOL bOnePendingBuffer; 1206 MS_BOOL bFrameRateHandling; 1207 MS_U32 u32PreSetFrameRate; 1208 HVD_EX_IapGnBufShareBWMode stIapGnShBWMode; 1209 MS_BOOL bDisableTspInBbuMode; 1210 HVD_MFCodec_mode eMFCodecMode; 1211 MS_BOOL bForce8BitMode; 1212 HVD_Feature eVdecFeature; 1213 HVD_Display_mode eDisplayMode; 1214 MS_BOOL bCalFrameRate; 1215 } HVD_Pre_Ctrl; 1216 1217 //------------------------------------------------------------------------------------------------- 1218 // Function and Variable 1219 //------------------------------------------------------------------------------------------------- 1220 extern MS_U32 u32UartCtrl; 1221 //extern MS_U32 u32InitSysTimeBase; 1222 1223 #endif // _DRV_HVD_DEF_H_ 1224 1225