1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
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10 // permission has been granted by MStar.
11 //
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14 // comply with all applicable laws and regulations:
15 //
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20 //
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32 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
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89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 #if defined(SUPPORT_HVD_SUB)
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "drvHVD_Common.h"
101 #include "drvHVD_def.h"
102 #include "drvHVD_sub_def.h"
103 #include "fwHVD_if.h"
104
105 // Internal Definition
106 #include "regHVD.h"
107 #include "halHVD.h"
108 #include "halHVD_sub.h"
109 #include "halVPU.h"
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114
115 //-------------------------------------------------------------------------------------------------
116 // Local Defines
117 //-------------------------------------------------------------------------------------------------
118 #define RV_VLC_TABLE_SIZE 0x20000
119
120 #if HVD_ENABLE_EMBEDDED_FW_BINARY
121
122 static MS_U8 u8HVD_FW_Binary[] =
123 {
124 #include "fwHVD.dat"
125 };
126 #if HVD_ENABLE_RV_FEATURE
127 static MS_U8 u8HVD_VLC_Binary[] =
128 {
129 #include "fwHVD_VLC.dat"
130 };
131 #endif
132
133 #endif
134
135 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
136 static MS_U32 u32PTSRptrAddr=0;
137 static MS_U32 u32PTSWptrAddr=0;
138 static MS_U32 u32PTSPreWptr=0;
139 static HVD_PTS_Entry PTSEntry;
140 static MS_U32 u32PTSByteCnt=0;
141 static MS_U32 u32BBUWptr=0;
142 static MS_U32 u32BBURptr=0;
143 static MS_U8 g_hvd_nal_fill_pair[2][8] = {{0,0,0,0,0,0,0,0}, { 0,0,0,0,0,0,0,0}};
144 static MS_U32 u32BBUEntryNum=0;
145 static MS_U32 u32BBUEntryNumTH=0;
146 static MS_U32 u32RV_VLCTableAddr=0; // offset from Frame buffer start address
147 //---------------------------------- Mutex settings -----------------------------------------
148 #if HAL_HVD_ENABLE_MUTEX_PROTECT
149 static MS_S32 s32HVDMutexID=-1;
150 static MS_U8 _u8HVD_Sub_Mutex[] = {"HVD_Sub_Mutex"};
151
152 #define _HAL_HVD_MutexCreate() \
153 if( s32HVDMutexID < 0 ) \
154 { \
155 s32HVDMutexID = OSAL_HVD_MutexCreate( _u8HVD_Sub_Mutex ); \
156 }
157 #define _HAL_HVD_MutexDelete() \
158 if( s32HVDMutexID >= 0 ) \
159 { \
160 OSAL_HVD_MutexDelete(s32HVDMutexID); \
161 s32HVDMutexID = -1; \
162 }
163 #define _HAL_HVD_Entry() \
164 if( s32HVDMutexID >= 0 ) \
165 { \
166 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
167 { \
168 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
169 } \
170 }
171 #define _HAL_HVD_Return(_ret) \
172 { \
173 if( s32HVDMutexID >= 0 ) \
174 { \
175 OSAL_HVD_MutexRelease(s32HVDMutexID); \
176 } \
177 return _ret; \
178 }
179 #define _HAL_HVD_Release() \
180 { \
181 if( s32HVDMutexID >= 0 ) \
182 { \
183 OSAL_HVD_MutexRelease(s32HVDMutexID); \
184 } \
185 }
186
187
188 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
189
190 #define _HAL_HVD_MutexCreate()
191 #define _HAL_HVD_MutexDelete()
192 #define _HAL_HVD_Entry()
193 #define _HAL_HVD_Return(_ret) {return _ret;}
194 #define _HAL_HVD_Release()
195
196 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
197
198 //------------------------------ MIU SETTINGS ----------------------------------
199 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
200 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
201 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
202 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
203
204 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
205 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
206 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
207 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
208
209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
210 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
213
214 #define _HVD_MIU_SetReqMask( miu_clients, mask ) \
215 do { \
216 if (HVD_##miu_clients##_ON_MIU1 == 0) \
217 _MaskMiuReq_##miu_clients( mask ); \
218 else \
219 _MaskMiu1Req_##miu_clients( mask ); \
220 }while(0)
221
222 // check RM is supported or not
223 #define HVD_HW_RUBBER3 (HAL_HVD_Get_HWVersionID()& BIT(14) )
224 //-------------------------------------------------------------------------------------------------
225 // Local Structures
226 //-------------------------------------------------------------------------------------------------
227
228
229 //-------------------------------------------------------------------------------------------------
230 // Global Variables
231 //-------------------------------------------------------------------------------------------------
232
233
234 //-------------------------------------------------------------------------------------------------
235 // Local Variables
236 //-------------------------------------------------------------------------------------------------
237 static volatile HVD_ShareMem* pHVDShareMem=NULL;
238 static HVD_Drv_Ctrl* pHVDCtrl_Hal=NULL;
239 static MS_U32 u32HVDCmdTimeout=0;
240 static MS_U32 u32VPUClockType = 144;
241 static MS_U32 u32HVDClockType = 144;
242
243 #if defined (__aeon__)
244 static MS_U32 u32HVDRegOSBase=0xA0200000;
245 #else
246 static MS_U32 u32HVDRegOSBase=0xBF200000;
247 #endif
248
249 #if defined(UDMA_FPGA_ENVI)
250 static HVD_ShareMem UDMA_pc_HVDShareMem;
251 static MS_U32 UDMA_fpga_HVDShareMemAddr=0;
252 #endif
253 //-------------------------------------------------------------------------------------------------
254 // Debug Functions
255 //-------------------------------------------------------------------------------------------------
256
257
258 //-------------------------------------------------------------------------------------------------
259 // Local Functions
260 //-------------------------------------------------------------------------------------------------
261 MS_U32 _HAL_HVD_Sub_GetBBUQNumb(void);
262
263
_HAL_HVD_Sub_GetBBUReadptr(void)264 static MS_U16 _HAL_HVD_Sub_GetBBUReadptr(void)
265 {
266 MS_U16 u16Ret=0;
267 //_HAL_HVD_Entry();
268 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , 0 , HVD_REG_POLL_NAL_RPTR_BIT );
269 _HVD_WriteWordMask( HVD_REG_POLL_NAL_RPTR , HVD_REG_POLL_NAL_RPTR_BIT , HVD_REG_POLL_NAL_RPTR_BIT );
270 u16Ret = _HVD_Read2Byte( HVD_REG_NAL_RPTR_HI_BS2 );
271 //_HAL_HVD_Return( u16Ret);
272 return u16Ret;
273 }
274
_HAL_HVD_Sub_SetBBUWriteptr(MS_U16 u16BBUNewWptr)275 static void _HAL_HVD_Sub_SetBBUWriteptr(MS_U16 u16BBUNewWptr )
276 {
277 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2, u16BBUNewWptr );
278 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR , HVD_REG_NAL_WPTR_SYNC , HVD_REG_NAL_WPTR_SYNC); // set bit 3
279 }
280
_HAL_HVD_Sub_MBoxSend(MS_U8 u8MBox,MS_U32 u32Msg)281 static MS_BOOL _HAL_HVD_Sub_MBoxSend(MS_U8 u8MBox, MS_U32 u32Msg)
282 {
283 MS_BOOL bResult = TRUE;
284 switch(u8MBox)
285 {
286 case E_HVD_HI_0:
287 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L, u32Msg);
288 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
289 break;
290
291 case E_HVD_HI_1:
292 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L, u32Msg);
293 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET, HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
294 break;
295 case E_HVD_VPU_HI_0:
296 bResult=HAL_VPU_MBoxSend( VPU_HI_MBOX0 , u32Msg );
297 break;
298
299 case E_HVD_VPU_HI_1:
300 bResult=HAL_VPU_MBoxSend( VPU_HI_MBOX1 , u32Msg );
301 break;
302 default:
303 bResult = FALSE;
304 break;
305 }
306
307 return bResult;
308 }
309
_HAL_HVD_Sub_MBoxReady(MS_U8 u8MBox)310 static MS_BOOL _HAL_HVD_Sub_MBoxReady(MS_U8 u8MBox)
311 {
312 MS_BOOL bResult = TRUE;
313 switch(u8MBox)
314 {
315 case E_HVD_HI_0:
316 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY, HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
317 break;
318 case E_HVD_HI_1:
319 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY, HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
320 break;
321 case E_HVD_RISC_0:
322 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY, HVD_REG_RISC_MBOX0_RDY) ? TRUE: FALSE;
323 break;
324 case E_HVD_RISC_1:
325 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY, HVD_REG_RISC_MBOX1_RDY) ? TRUE: FALSE;
326 break;
327 case E_HVD_VPU_HI_0:
328 bResult = HAL_VPU_MBoxRdy( VPU_HI_MBOX0);
329 break;
330 case E_HVD_VPU_HI_1:
331 bResult = HAL_VPU_MBoxRdy( VPU_HI_MBOX1);
332 break;
333 case E_HVD_VPU_RISC_0:
334 bResult = HAL_VPU_MBoxRdy( VPU_RISC_MBOX0);
335 break;
336 case E_HVD_VPU_RISC_1:
337 bResult = HAL_VPU_MBoxRdy( VPU_RISC_MBOX1);
338 break;
339 default:
340 break;
341 }
342 return bResult;
343 }
344
_HAL_HVD_Sub_MBoxRead(MS_U8 u8MBox,MS_U32 * u32Msg)345 static MS_BOOL _HAL_HVD_Sub_MBoxRead(MS_U8 u8MBox, MS_U32 *u32Msg)
346 {
347 MS_BOOL bResult = TRUE;
348 switch(u8MBox)
349 {
350 case E_HVD_HI_0:
351 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L);
352 break;
353 case E_HVD_HI_1:
354 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L);
355 break;
356 case E_HVD_RISC_0:
357 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L);
358 break;
359 case E_HVD_RISC_1:
360 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L);
361 break;
362 case E_HVD_VPU_RISC_0:
363 bResult=HAL_VPU_MBoxRead( VPU_RISC_MBOX0 , u32Msg );
364 break;
365 case E_HVD_VPU_RISC_1:
366 bResult=HAL_VPU_MBoxRead( VPU_RISC_MBOX1 , u32Msg );
367 break;
368 default:
369 bResult = FALSE;
370 break;
371 }
372 return bResult;
373 }
374
_HAL_HVD_Sub_MBoxClear(MS_U8 u8MBox)375 static void _HAL_HVD_Sub_MBoxClear(MS_U8 u8MBox)
376 {
377 switch(u8MBox)
378 {
379 case E_HVD_RISC_0:
380 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR , HVD_REG_RISC_MBOX0_CLR);
381 break;
382 case E_HVD_RISC_1:
383 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR , HVD_REG_RISC_MBOX1_CLR);
384 break;
385 case E_HVD_VPU_RISC_0:
386 HAL_VPU_MBoxClear( VPU_RISC_MBOX0 );
387 break;
388 case E_HVD_VPU_RISC_1:
389 HAL_VPU_MBoxClear( VPU_RISC_MBOX1 );
390 break;
391 default:
392 break;
393 }
394 }
395
HAL_HVD_Sub_Dump_HW_Status(MS_U32 numb)396 void HAL_HVD_Sub_Dump_HW_Status(MS_U32 numb)
397 {
398 MS_U32 i=0;
399 MS_U32 value=0;
400 HVD_SUB_MSG_DEG("HVD Dump HW status:");
401 for( i=0 ; i <= numb ; i++ )
402 {
403 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
404 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
405 value |= ((MS_U32)_HVD_Read2Byte(HVD_REG_DEBUG_DAT_H))<<16;
406 if( value == 0 )
407 {
408 break;
409 }
410 HVD_SUB_MSG_DEG(" %lx" , value );
411 if( ((i % 8)+1) ==8)
412 {
413 HVD_SUB_MSG_DEG(" |%lu\n" , i +1 );
414 }
415 }
416 HVD_SUB_MSG_DEG("\nHVD Dump HW status End: total number:%lu\n" , i );
417 }
418
_HAL_HVD_Sub_GetPC(void)419 static MS_U32 _HAL_HVD_Sub_GetPC(void)
420 {
421 MS_U32 u32PC=0;
422 u32PC = HAL_VPU_GetProgCnt();
423 // HVD_SUB_MSG_DEG("<gdbg>pc0 =0x%lx\n",u32PC);
424 return u32PC;
425 }
426
_HAL_HVD_Sub_GetFWState(void)427 static MS_U32 _HAL_HVD_Sub_GetFWState(void)
428 {
429 MS_U32 u32Ret=0;
430 if( _HAL_HVD_Sub_MBoxRead(HAL_HVD_REG_FW_STATE , &u32Ret ))
431 {
432 return u32Ret;
433 }
434 else
435 {
436 return 0;
437 }
438 }
439
_HAL_HVD_Sub_GetESWritePtr(void)440 static MS_U32 _HAL_HVD_Sub_GetESWritePtr(void)
441 {
442 MS_U32 data=0;
443 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
444 {
445 data=pHVDCtrl_Hal->LastNal.u32NalAddr+pHVDCtrl_Hal->LastNal.u32NalSize;
446 if( data > pHVDCtrl_Hal->MemMap.u32BitstreamBufSize)
447 {
448 data-=pHVDCtrl_Hal->MemMap.u32BitstreamBufSize;
449 HVD_SUB_MSG_ERR( "HVD HAL: _HAL_HVD_Sub_GetESWritePtr(): app should not put this kind of packet\n");
450 }
451 }
452 else
453 {
454 data =pHVDShareMem->u32ESWritePtr;
455 }
456 return data;
457 }
458
_HAL_HVD_Sub_GetESReadPtr(MS_BOOL bDbug)459 static MS_U32 _HAL_HVD_Sub_GetESReadPtr(MS_BOOL bDbug)
460 {
461 MS_U32 data=0;
462
463 if(((pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK)==E_HVD_INIT_INPUT_DRV)
464 || (TRUE == bDbug))
465 {
466 // set reg_poll_nal_rptr 0
467 _HVD_WriteWordMask(HVD_REG_ESB_RPTR_BS2, 0, HVD_REG_ESB_RPTR_POLL);
468 // set reg_poll_nal_rptr 1
469 _HVD_WriteWordMask(HVD_REG_ESB_RPTR_BS2, HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
470 // read reg_nal_rptr_hi
471 #if 0
472 if( HVD_HW_RUBBER3 )
473 {
474 data=_HVD_Read2Byte( HVD_REG_ESB_RPTR_BS2 ) & 0xFF80;
475 data>>=7;
476 data |= _HVD_Read2Byte( HVD_REG_ESB_RPTR_H_BS2 ) << 9;
477 }
478 else // rubber2
479 #endif
480 //_HAL_HVD_Entry();
481 data=_HVD_Read2Byte( HVD_REG_ESB_RPTR_BS2 ) & 0xFFC0;
482 data>>=6;
483 data |= _HVD_Read2Byte( HVD_REG_ESB_RPTR_H_BS2 ) << 10;
484 //_HAL_HVD_Release();
485 // patch for XDemux
486 #if 0
487 /*
488 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
489 {
490 MS_U32 u32ESWptr=_HAL_HVD_Sub_GetESWritePtr();
491 MS_U32 u32ESWptrtmp=data<<3;
492 if( ( pHVDCtrl_Hal->u32LastESRptr < u32ESWptr )
493 && ( u32ESWptrtmp > u32ESWptr ) )
494 {
495 HVD_SUB_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32ESWptrtmp , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
496 }
497 }
498 */
499 if( data >= 1)
500 {
501 data -=1;
502 }
503 else
504 {
505 data=(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize>>3)-1;
506 }
507
508 data<<=3;// unit
509
510 #else
511 data<<=3;// unit
512 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag&E_HVD_INIT_INPUT_MASK )==E_HVD_INIT_INPUT_DRV)
513 {
514 MS_U32 u32ESWptr=_HAL_HVD_Sub_GetESWritePtr();
515 if( ( pHVDCtrl_Hal->u32LastESRptr < u32ESWptr )
516 && ( data > u32ESWptr ) )
517 {
518 //HVD_SUB_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
519 data = u32ESWptr;
520 }
521 else if( ( pHVDCtrl_Hal->u32LastESRptr == u32ESWptr )
522 && ( data > u32ESWptr ) )
523 {
524 //HVD_SUB_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
525 data = u32ESWptr;
526 }
527 else if( _HAL_HVD_Sub_GetBBUQNumb() ==0 && (( data - u32ESWptr )< 16) && (( _HAL_HVD_Sub_GetFWState() & E_HVD_FW_STATE_MASK )==E_HVD_FW_PLAY))
528 {
529 //HVD_SUB_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, u32ESWptr );
530 data = u32ESWptr;
531 }
532 }
533 #endif
534 // remove illegal pointer
535 #if 1
536 if( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize !=0) && (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr !=0) )
537 {
538 MS_U32 u32PacketStaddr = data + pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
539 if( ( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr ) &&
540 (u32PacketStaddr < (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr + pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize)) ) )
541 {
542 //HVD_SUB_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , data , pHVDCtrl_Hal->u32LastESRptr, pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr , pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize );
543 data = pHVDCtrl_Hal->u32LastESRptr;
544 }
545 }
546 #endif
547 }
548 else
549 {
550 data =pHVDShareMem->u32ESReadPtr;
551 }
552
553 pHVDCtrl_Hal->u32LastESRptr = data;
554 //return data;
555 return data;
556 }
557
_HAL_HVD_Sub_SetCMDArg(MS_U32 u32Arg)558 static MS_BOOL _HAL_HVD_Sub_SetCMDArg(MS_U32 u32Arg)
559 {
560 MS_U16 u16TimeOut = 0xFFFF;
561 MS_BOOL bResult = FALSE;
562
563 //HVD_SUB_MSG_DEG("Send argument 0x%lx to HVD \n", u32Arg);
564 while(--u16TimeOut)
565 {
566 if( _HAL_HVD_Sub_MBoxReady(HAL_HVD_CMD_MBOX)&&
567 _HAL_HVD_Sub_MBoxReady(HAL_HVD_CMD_ARG_MBOX))
568 {
569 bResult = _HAL_HVD_Sub_MBoxSend(HAL_HVD_CMD_ARG_MBOX, u32Arg);
570 break;
571 }
572 }
573 return bResult;
574 }
575
_HAL_HVD_Sub_SetCMD(MS_U32 u32Cmd)576 static MS_BOOL _HAL_HVD_Sub_SetCMD(MS_U32 u32Cmd)
577 {
578 MS_U16 u16TimeOut = 0xFFFF;
579 MS_BOOL bResult = FALSE;
580
581 //HVD_SUB_MSG_DEG("Send CMD 0x%lx to HVD \n", u32Cmd);
582 while(--u16TimeOut)
583 {
584 if(_HAL_HVD_Sub_MBoxReady(HAL_HVD_CMD_MBOX))
585 {
586 bResult = _HAL_HVD_Sub_MBoxSend(HAL_HVD_CMD_MBOX, u32Cmd);
587 break;
588 }
589 }
590 return bResult;
591 }
592
_HAL_HVD_Sub_SendCmd(MS_U32 u32Cmd,MS_U32 u32CmdArg)593 static HVD_Return _HAL_HVD_Sub_SendCmd( MS_U32 u32Cmd , MS_U32 u32CmdArg)
594 {
595 MS_U32 u32timeout= HVD_GetSysTime_ms() +u32HVDCmdTimeout ;
596 while( !_HAL_HVD_Sub_SetCMDArg( u32CmdArg ) )
597 {
598 if( HVD_GetSysTime_ms() > u32timeout )
599 {
600 HVD_SUB_MSG_ERR( "HVD cmd:%lx ;cmd arg timeout:%lx\n" , u32Cmd , u32CmdArg );
601 return E_HVD_RETURN_TIMEOUT;
602 }
603 if( u32Cmd == E_HVD_CMD_STOP )
604 {
605 _HAL_HVD_Sub_MBoxSend(HAL_HVD_CMD_MBOX, E_HVD_CMD_STOP);
606 _HAL_HVD_Sub_MBoxSend(HAL_HVD_CMD_ARG_MBOX, 0);
607 HVD_SUB_MSG_ERR( "HVD cmd force stop:%lx ;cmd arg:%lx\n" , u32Cmd , u32CmdArg );
608 return E_HVD_RETURN_SUCCESS;
609 }
610 //_HAL_HVD_Sub_GetPC();
611 HAL_HVD_Sub_Dump_FW_Status();
612 HAL_HVD_Sub_Dump_HW_Status(HVD_U32_MAX);
613 }
614 u32timeout= HVD_GetSysTime_ms() +u32HVDCmdTimeout ;
615 while( !_HAL_HVD_Sub_SetCMD( u32Cmd ) )
616 {
617 if( HVD_GetSysTime_ms() > u32timeout )
618 {
619 HVD_SUB_MSG_ERR( " cmd timeout: %lx\n" , u32Cmd );
620 return E_HVD_RETURN_TIMEOUT;
621 }
622 //_HAL_HVD_Sub_GetPC();
623 HAL_HVD_Sub_Dump_FW_Status();
624 HAL_HVD_Sub_Dump_HW_Status(HVD_U32_MAX);
625 }
626 return E_HVD_RETURN_SUCCESS;
627 }
628
_HAL_HVD_Sub_SetMIUProtectMask(MS_BOOL bEnable)629 static void _HAL_HVD_Sub_SetMIUProtectMask(MS_BOOL bEnable)
630 {
631 #if HAL_HVD_ENABLE_MIU_PROTECT
632 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
633 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
634 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
635 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
636 HAL_VPU_MIU_RW_Protect( bEnable );
637 //HVD_Delay_ms(1);
638 #endif
639 return;
640 }
641
_HAL_HVD_Sub_RstMVDParser(void)642 static void _HAL_HVD_Sub_RstMVDParser(void)
643 {
644 _HAL_HVD_Sub_SetMIUProtectMask(TRUE);
645 // _HVD_WriteRegBit(MVD_REG_STAT_CTRL, 1, MVD_REG_CTRL_RST|MVD_REG_CTRL_INIT);
646 _HVD_WriteWordMask(MVD_REG_STAT_CTRL, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU);
647 HVD_Delay_ms(1); // Delay 2ms to make MVD reset complete
648 _HVD_WriteWordMask(MVD_REG_STAT_CTRL, 0, MVD_REG_CTRL_RST|MVD_REG_DISCONNECT_MIU);
649 _HAL_HVD_Sub_SetMIUProtectMask(FALSE);
650 return;
651 }
652
_HAL_HVD_Sub_SVD_Release(void)653 static void _HAL_HVD_Sub_SVD_Release(void)
654 {
655 // release SW reset
656 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
657
658 // release cpu rst
659 HAL_VPU_SwRstRelse();
660 }
661
_HAL_HVD_Sub_SetBufferAddr(void)662 static void _HAL_HVD_Sub_SetBufferAddr(void)
663 {
664 MS_U16 u16Reg = 0;
665 MS_U32 u32StAddr = 0;
666 MS_BOOL bBitMIU1 = FALSE;
667 MS_BOOL bCodeMIU1 = FALSE;
668
669 // nal table settngs
670 if(pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
671 {
672 bCodeMIU1 = TRUE;
673 }
674 if(pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
675 {
676 bBitMIU1 = TRUE;
677 }
678 if(bBitMIU1 != bCodeMIU1)
679 {
680 u32StAddr = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr +
681 pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
682
683 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
684 {
685 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
686 }
687 }
688 else
689 {
690 u32StAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr +
691 HVD_BBU_DRAM_ST_ADDR;
692
693 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
694 {
695 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
696 }
697 }
698 HVD_SUB_MSG_DEG("_HAL_HVD_Sub_SetBufferAddr: nal StAddr:%lx \n", u32StAddr);
699 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2, (MS_U16)(u32StAddr >> 3));
700 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2, (MS_U16)(u32StAddr >> 19));
701 // -1 is for NAL_TAB_LEN counts from zero.
702 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2, (MS_U16)(u32BBUEntryNum - 1));
703
704 // ES buffer
705 u32StAddr = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
706 if(u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
707 {
708 u32StAddr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
709 }
710 HVD_SUB_MSG_DEG("_HAL_HVD_Sub_SetBufferAddr: ESb StAddr:%lx \n", u32StAddr);
711 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr >> 3));
712 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr >> 3));
713
714 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2,
715 HVD_LWORD(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize >> 3));
716 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2,
717 HVD_HWORD(pHVDCtrl_Hal->MemMap.u32BitstreamBufSize >> 3));
718
719 // others
720 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2);
721 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
722 {
723 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
724 }
725 else
726 {
727 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
728 }
729 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
730 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
731 {
732 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
733 }
734 else // AVS or AVC
735 {
736 if((pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
737 {
738 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
739 }
740 else // start code remained
741 {
742 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
743 }
744 }
745 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
746 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2, u16Reg);
747
748 // MIF offset
749 #if 0
750 {
751 MS_U16 offaddr=0;
752 u32StAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
753 if( u32StAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
754 {
755 u32StAddr-=pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
756 }
757 HVD_SUB_MSG_DEG("_HAL_HVD_Sub_SetBufferAddr: MIF offset:%lx \n" , u32StAddr);
758 offaddr = (MS_U16)((u32StAddr )>>20);
759 offaddr &= BMASK( HVD_REG_MIF_OFFSET_L_BITS_BS2 :0 );//0x1FF; // 9 bits(L + H)
760 u16Reg=_HVD_Read2Byte(HVD_REG_MIF_BBU_BS2) ;
761 u16Reg&= ~HVD_REG_MIF_OFFSET_H_BS2 ;
762 u16Reg&=~(BMASK( HVD_REG_MIF_OFFSET_L_BITS_BS2 :0)) ;
763 if(offaddr & BIT( HVD_REG_MIF_OFFSET_L_BITS_BS2 ) )
764 {
765 u16Reg |= HVD_REG_MIF_OFFSET_H_BS2;
766 }
767 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2,
768 (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS_BS2 :0))));
769 }
770 #endif
771 }
772
_HAL_HVD_Sub_GetESLevel(void)773 static MS_U32 _HAL_HVD_Sub_GetESLevel(void)
774 {
775 MS_U32 u32Wptr = 0;
776 MS_U32 u32Rptr = 0;
777 MS_U32 u32CurMBX=0;
778 MS_U32 u32ESsize =0;
779 MS_U32 u32Ret=E_HVD_ESB_LEVEL_NORMAL;
780
781 u32Wptr = _HAL_HVD_Sub_GetESWritePtr();
782 u32Rptr = _HAL_HVD_Sub_GetESReadPtr(FALSE);
783 u32ESsize = pHVDCtrl_Hal->MemMap.u32BitstreamBufSize;
784 if(u32Rptr >= u32Wptr)
785 {
786 u32CurMBX = u32Rptr - u32Wptr;
787 }
788 else
789 {
790 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
791 }
792
793 if( u32CurMBX == 0)
794 {
795 u32Ret = E_HVD_ESB_LEVEL_UNDER;
796 }
797 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
798 {
799 u32Ret = E_HVD_ESB_LEVEL_OVER;
800 }
801 else
802 {
803 u32CurMBX = u32ESsize - u32CurMBX;
804 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
805 {
806 u32Ret = E_HVD_ESB_LEVEL_UNDER;
807 }
808 }
809 return u32Ret;
810 }
811
_HAL_HVD_Sub_SwCPURst(void)812 MS_BOOL _HAL_HVD_Sub_SwCPURst(void)
813 {
814 MS_U16 u16Timeout = 1000;
815
816 _HAL_HVD_Sub_SetMIUProtectMask(TRUE);
817
818 // re-setup clock.
819 HAL_HVD_Sub_PowerCtrl(TRUE);
820
821 HAL_VPU_SwRst();
822 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST);
823
824 while(u16Timeout)
825 {
826 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN))
827 == (HVD_REG_RESET_SWRST_FIN))
828 {
829 break;
830 }
831 u16Timeout--;
832 }
833
834 _HAL_HVD_Sub_SetMIUProtectMask(FALSE);
835
836 if( !u16Timeout )
837 {
838 HVD_SUB_MSG_ERR("_HAL_HVD_Sub_SwCPURst timeout \n");
839 }
840
841 return (u16Timeout>0) ? TRUE : FALSE;
842 }
843
_HAL_HVD_Sub_LoadVLCTable(HVD_FWInputSourceType eType)844 MS_BOOL _HAL_HVD_Sub_LoadVLCTable(HVD_FWInputSourceType eType )
845 {
846 #if HVD_ENABLE_RV_FEATURE
847 if( eType == E_HVD_FW_INPUT_SOURCE_FLASH )
848 {
849 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
850 HVD_SUB_MSG_DEG("HVD Loading VLC outF2D: dest:0x%lx source:%lx size:%lx\n", (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufAddr+u32RV_VLCTableAddr ,
851 ((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
852 if( pHVDCtrl_Hal->MemMap.u32VLCBinarySize != 0 )
853 {
854 SPIDMA_Dev cpyflag=E_SPIDMA_DEV_MIU1;
855 if( pHVDCtrl_Hal->MemMap.u32FrameBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
856 {
857 cpyflag = E_SPIDMA_DEV_MIU1;
858 }
859 else
860 {
861 cpyflag = E_SPIDMA_DEV_MIU0;
862 }
863 if( !HVD_FLASHcpy( (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufAddr+u32RV_VLCTableAddr , pHVDCtrl_Hal->MemMap.u32VLCBinaryAddr , pHVDCtrl_Hal->MemMap.u32VLCBinarySize , cpyflag ) )
864 {
865 HVD_SUB_MSG_ERR("HVD ERR: HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , (MS_U32)cpyflag );
866 return FALSE;
867 }
868 }
869 else
870 {
871 HVD_SUB_MSG_ERR("HVD ERR: During copy VLC from Flash to Dram, the source size of FW is zero\n");
872 return FALSE;
873 }
874 #else
875 HVD_SUB_MSG_ERR("HVD ERR: driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
876 return FALSE;
877 #endif
878 }
879 else
880 {
881 if( eType == E_HVD_FW_INPUT_SOURCE_DRAM)
882 {
883 if( (pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr!= 0) && ( pHVDCtrl_Hal->MemMap.u32VLCBinarySize!= 0 ) )
884 {
885 HVD_SUB_MSG_DEG("HVD Loading VLC outD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ,
886 ((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
887 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ),
888 (void*)(((MS_U32)pHVDCtrl_Hal->MemMap.u32VLCBinaryVAddr)) , pHVDCtrl_Hal->MemMap.u32VLCBinarySize);
889 }
890 else
891 {
892 HVD_SUB_MSG_ERR("HVD ERR: During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
893 return FALSE;
894 }
895 }
896 else
897 {
898 #if HVD_ENABLE_EMBEDDED_FW_BINARY
899 HVD_SUB_MSG_DEG("HVD Loading VLC inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr,
900 ((MS_U32)u8HVD_VLC_Binary) , (MS_U32)sizeof(u8HVD_VLC_Binary) );
901 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32FrameBufVAddr+u32RV_VLCTableAddr ),
902 (void*)((MS_U32)u8HVD_VLC_Binary) , sizeof(u8HVD_VLC_Binary) );
903 #else
904 HVD_SUB_MSG_ERR("HVD ERR: driver not enable to use embedded VLC binary.\n");
905 return FALSE;
906 #endif
907 }
908 }
909 #endif
910 return TRUE;
911 }
912
_HAL_HVD_Sub_SetRegCPU(void)913 MS_BOOL _HAL_HVD_Sub_SetRegCPU(void)
914 {
915 MS_U32 u32FirmVer = 0;
916 MS_U32 u32Timeout = 20000;
917 MS_BOOL bNeedReloadFW = TRUE;
918
919 HVD_SUB_MSG_DEG("HVD HW ver id: 0x%04lx\n", HAL_HVD_Sub_Get_HWVersionID() );
920
921 if(!_HAL_HVD_Sub_SwCPURst())
922 {
923 HVD_SUB_MSG_ERR("HVD reset failed...\n");
924 return FALSE;
925 }
926 #if HVD_ENABLE_TIME_MEASURE
927 HVD_SUB_MSG_MUST( "HVD Time Measure:%d (%s %d) \n" , HVD_GetSysTime_ms() - u32SubInitSysTimeBase , __FUNCTION__, __LINE__ );
928 #endif
929
930 //Check whether need to reload fw or not
931 if((TRUE == pHVDCtrl_Hal->bTurboFWMode)
932 && (FALSE == HAL_VPU_IsNeedReload(E_VPU_DECODER_HVD)))
933 {
934 bNeedReloadFW = FALSE;
935 }
936
937 if(TRUE == bNeedReloadFW)
938 {
939 //If we need to reload fw, need to reset vpu fw decoder type first.
940 HAL_VPU_SetFWDecoder(E_VPU_DECODER_NONE);
941
942 // load binary
943 if( pHVDCtrl_Hal->MemMap.eFWSourceType == E_HVD_FW_INPUT_SOURCE_FLASH )
944 {
945 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM
946 HVD_SUB_MSG_DEG("HVD Loading FW outF2D: dest:0x%lx source:%lx size:%lx\n", (MS_U32)pHVDCtrl_Hal->MemMap.u32CodeBufAddr ,
947 ((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinarySize);
948 if( pHVDCtrl_Hal->MemMap.u32FWBinarySize != 0 )
949 {
950 SPIDMA_Dev cpyflag=E_SPIDMA_DEV_MIU1;
951 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
952 {
953 cpyflag = E_SPIDMA_DEV_MIU1;
954 }
955 else
956 {
957 cpyflag = E_SPIDMA_DEV_MIU0;
958 }
959 if( !HVD_FLASHcpy( pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , cpyflag ) )
960 {
961 HVD_SUB_MSG_ERR("HVD ERR: HVD_BDMAcpy Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32FWBinaryAddr , pHVDCtrl_Hal->MemMap.u32FWBinarySize , (MS_U32)cpyflag );
962 return FALSE;
963 }
964 }
965 else
966 {
967 HVD_SUB_MSG_ERR("HVD ERR: During copy FW from Flash to Dram, the source size of FW is zero\n");
968 return FALSE;
969 }
970 #else
971 HVD_SUB_MSG_ERR("HVD ERR: driver not enable to use BDMA copy FW Bin from flash 2 sdram.\n");
972 return FALSE;
973 #endif
974 }
975 else
976 {
977 if( pHVDCtrl_Hal->MemMap.eFWSourceType == E_HVD_FW_INPUT_SOURCE_DRAM)
978 {
979 if( (pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr != 0) && ( pHVDCtrl_Hal->MemMap.u32FWBinarySize != 0 ) )
980 {
981 HVD_SUB_MSG_DEG("HVD Loading FW outD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ,
982 ((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr) , (MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinarySize);
983 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ),
984 (void*)(((MS_U32)pHVDCtrl_Hal->MemMap.u32FWBinaryVAddr)) , pHVDCtrl_Hal->MemMap.u32FWBinarySize);
985 }
986 else
987 {
988 HVD_SUB_MSG_ERR("HVD ERR: During copy FW from out Dram to Dram, the source size or virtual address of FW is zero\n");
989 return FALSE;
990 }
991 }
992 else
993 {
994 #if HVD_ENABLE_EMBEDDED_FW_BINARY
995 HVD_SUB_MSG_DEG("HVD Loading FW inD2D: dest:0x%lx source:%lx size:%lx\n", pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ,
996 ((MS_U32)u8HVD_FW_Binary) , (MS_U32)sizeof(u8HVD_FW_Binary) );
997 HVD_memcpy( (void*)( pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ),
998 (void*)((MS_U32)u8HVD_FW_Binary), sizeof(u8HVD_FW_Binary) );
999 #else
1000 HVD_SUB_MSG_ERR("HVD ERR: driver not enable to use embedded FW binary.\n");
1001 return FALSE;
1002 #endif
1003 }
1004 }
1005
1006 if( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK )
1007 == E_HVD_INIT_HW_RM )
1008 {
1009 if( _HAL_HVD_Sub_LoadVLCTable( pHVDCtrl_Hal->MemMap.eFWSourceType ) == FALSE)
1010 {
1011 return FALSE;
1012 }
1013 }
1014 _HVD_Sub_Chip_Flush_Memory();
1015 //HVD_SUB_MSG_DEG("HVD FW data compare: dest:0x%lx %lx %lx source:%lx %lx %lx\n",
1016 // *(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+160) ,*(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+164),*(MS_U32*)(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr+168),
1017 // *(MS_U32*)(u8HVD_FW_Binary+160) ,*(MS_U32*)(u8HVD_FW_Binary+164),*(MS_U32*)(u8HVD_FW_Binary+168));
1018
1019 //When complete loading fw, set vpu fw decoder type
1020 HAL_VPU_SetFWDecoder(E_VPU_DECODER_HVD);
1021
1022 HVD_SUB_MSG_DEG("HVD Load FW done\n" );
1023 }
1024
1025 {
1026 MS_U32 u32Addr = 0;
1027 u32Addr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1028 /* //From JANUS and the later chip, need not set the offset when VPU setting.
1029 if( u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1030 {
1031 u32Addr-=pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1032 }
1033 */
1034 HVD_SUB_MSG_DEG("_HAL_HVD_Sub_SetRegCPU: VPU settings:%lx \n" , u32Addr);
1035 HAL_VPU_CPUSetting(u32Addr);
1036 }
1037
1038 //HVD4, from JANUS and later chip
1039 switch( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) )
1040 {
1041 case E_HVD_INIT_HW_AVS:
1042 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_AVS_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1043 break;
1044 case E_HVD_INIT_HW_RM:
1045 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RM_MODE , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1046 if( pHVDCtrl_Hal->InitParams.pRVFileInfo->RV_Version )// RV 9,10
1047 {
1048 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_HK_RV9_DEC_MODE , HVD_REG_RESET_HK_RV9_DEC_MODE );
1049 }
1050 else // RV 8
1051 {
1052 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_RV9_DEC_MODE );
1053 }
1054 break;
1055 //case E_HVD_INIT_HW_AVC:
1056 default:
1057 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_HK_AVS_MODE|HVD_REG_RESET_HK_RM_MODE );
1058 break;
1059 }
1060
1061 //T8: use miu128bit
1062 HVD_SUB_MSG_DEG("(be)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET));
1063 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
1064 HVD_SUB_MSG_DEG("(af)Miu128 bits Status = %x <<<<<<<\n",_HVD_Read2Byte(HVD_REG_RESET));
1065
1066 _HAL_HVD_Sub_SetBufferAddr();
1067 _HAL_HVD_Sub_RstMVDParser();
1068
1069 // release sw and cpu rst
1070 _HAL_HVD_Sub_SVD_Release();
1071 HVD_SUB_MSG_DEG("HVD CPU/HW release done\n" );
1072
1073 while(u32Timeout)
1074 {
1075 u32FirmVer =HAL_HVD_Sub_GetData(E_HVD_GDATA_FW_INIT_DONE);
1076 if( u32FirmVer != 0)
1077 {
1078 u32FirmVer =HAL_HVD_Sub_GetData(E_HVD_GDATA_FW_VERSION_ID);
1079 break;
1080 }
1081 u32Timeout--;
1082 HVD_Delay_ms(1);
1083 }
1084 if(u32Timeout > 0)
1085 {
1086 HVD_SUB_MSG_DEG("HVD firmware version binary:0x%lx if:0x%lx\n", u32FirmVer , (MS_U32)HVD_FW_VERSION);
1087 }
1088 else
1089 {
1090 _HAL_HVD_Sub_GetPC();
1091 HVD_SUB_MSG_ERR("Cannot get HVD firmware version !!%x %lx \n" , (MS_S16)_HVD_Read2Byte(HVD_REG_RESET) , HAL_HVD_Sub_GetData(E_HVD_GDATA_FW_VERSION_ID));
1092 return FALSE;
1093 }
1094 #if HVD_ENABLE_TIME_MEASURE
1095 HVD_SUB_MSG_MUST( "HVD Time Measure:%d (%s %d) \n" , HVD_GetSysTime_ms() - u32SubInitSysTimeBase , __FUNCTION__, __LINE__ );
1096 #endif
1097
1098 return TRUE;
1099 }
1100
_HAL_HVD_Sub_UpdatePTSTable(HVD_BBU_Info * pInfo)1101 HVD_Return _HAL_HVD_Sub_UpdatePTSTable(HVD_BBU_Info* pInfo)
1102 {
1103 MS_U32 u32PTSWptr=HVD_U32_MAX;
1104 MS_U32 u32PTSRptr=HVD_U32_MAX;
1105 MS_U32 u32DestAddr=0;
1106 // update R & W ptr
1107 u32PTSRptr=HAL_VPU_MemRead( u32PTSRptrAddr );
1108 //HVD_SUB_MSG_DEG("HVD PTS table RPtr:%lx Wptr:%lx\n" ,u32PTSRptr , HAL_VPU_MemRead( u32PTSWptrAddr ) );
1109 if( u32PTSRptr >= MAX_PTS_TABLE_SIZE )
1110 {
1111 HVD_SUB_MSG_ERR("HVD ERR: PTS table Read Ptr(%lx) > max table size(%lx) \n" ,u32PTSRptr ,(MS_U32)MAX_PTS_TABLE_SIZE);
1112 return E_HVD_RETURN_FAIL;
1113 }
1114 // check queue is full or not
1115 u32PTSWptr = u32PTSPreWptr + 1;
1116 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
1117 if( u32PTSWptr == u32PTSRptr )
1118 {
1119 HVD_SUB_MSG_ERR("HVD ERR: PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n" ,u32PTSRptr,u32PTSWptr , u32PTSPreWptr );
1120 return E_HVD_RETURN_FAIL;
1121 }
1122 // add one PTS entry
1123 PTSEntry.u32ByteCnt =u32PTSByteCnt&HVD_BYTE_COUNT_MASK;
1124 PTSEntry.u32ID_L=pInfo->u32ID_L;
1125 PTSEntry.u32ID_H=pInfo->u32ID_H;
1126 PTSEntry.u32PTS=pInfo->u32TimeStamp;
1127 #if defined(UDMA_FPGA_ENVI)
1128 u32DestAddr=(pHVDCtrl_Hal->MemMap.u32CodeBufAddr ) +HVD_PTS_TABLE_ST_OFFSET+(u32PTSPreWptr*sizeof(HVD_PTS_Entry));
1129 HVD_UDMA_memcpy( (void*)u32DestAddr , &PTSEntry , sizeof(HVD_PTS_Entry ) );
1130 #else
1131 u32DestAddr=(pHVDCtrl_Hal->MemMap.u32CodeBufVAddr ) +HVD_PTS_TABLE_ST_OFFSET+(u32PTSPreWptr*sizeof(HVD_PTS_Entry));
1132 HVD_memcpy( (void*)u32DestAddr , &PTSEntry , sizeof(HVD_PTS_Entry ) );
1133 _HVD_Sub_Chip_Flush_Memory();
1134 #endif
1135 // update Write ptr
1136 if( !HAL_VPU_MemWrite( u32PTSWptrAddr , u32PTSPreWptr) )
1137 {
1138 HVD_SUB_MSG_ERR("HVD ERR: PTS table SRAM write failed\n" );
1139 return E_HVD_RETURN_FAIL;
1140 }
1141 u32PTSPreWptr=u32PTSWptr;
1142 return E_HVD_RETURN_SUCCESS;
1143 }
1144
_HAL_HVD_Sub_UpdateESWptr(MS_U32 nal_offset,MS_U32 nal_len)1145 HVD_Return _HAL_HVD_Sub_UpdateESWptr(MS_U32 nal_offset , MS_U32 nal_len)
1146 {
1147 //---------------------------------------------------
1148 // item format in nal table:
1149 // reserved |borken| nal_offset | nal_len
1150 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
1151 //---------------------------------------------------
1152 MS_U32 addr=0;
1153 MS_U32 u32BBUNewWptr = 0;
1154 MS_U8 item[8];
1155
1156 // MS_U8 pbuf[HVD_MAX_PACKET_SIZE]; // temp buffer
1157 u32BBUNewWptr=u32BBUWptr;
1158 u32BBUNewWptr++;
1159 u32BBUNewWptr%=u32BBUEntryNum;
1160
1161 // prepare nal entry
1162 item[0] = nal_len & 0xff;
1163 item[1] = (nal_len >> 8) & 0xff;
1164 item[2] = ((nal_len >> 16) & 0x1f ) | ((nal_offset<<5) & 0xe0);
1165 item[3] = (nal_offset>>3) & 0xff;
1166 item[4] = (nal_offset>>11) & 0xff;
1167 item[5] = (nal_offset>>19) & 0xff;
1168 item[6] = (nal_offset>>27) & 0x07; //including broken bit
1169 item[7] = 0;
1170
1171 // add nal entry
1172 #if defined(UDMA_FPGA_ENVI)
1173 if(u32BBUWptr%2==0)
1174 {
1175 g_hvd_nal_fill_pair[0][0] = item[0];
1176 g_hvd_nal_fill_pair[0][1] = item[1];
1177 g_hvd_nal_fill_pair[0][2] = item[2];
1178 g_hvd_nal_fill_pair[0][3] = item[3];
1179 g_hvd_nal_fill_pair[0][4] = item[4];
1180 g_hvd_nal_fill_pair[0][5] = item[5];
1181 g_hvd_nal_fill_pair[0][6] = item[6];
1182 g_hvd_nal_fill_pair[0][7] = item[7];
1183 g_hvd_nal_fill_pair[1][0] = 0;
1184 g_hvd_nal_fill_pair[1][1] = 0;
1185 g_hvd_nal_fill_pair[1][2] = 0;
1186 g_hvd_nal_fill_pair[1][3] = 0;
1187 g_hvd_nal_fill_pair[1][4] = 0;
1188 g_hvd_nal_fill_pair[1][5] = 0;
1189 g_hvd_nal_fill_pair[1][6] = 0;
1190 g_hvd_nal_fill_pair[1][7] = 0;
1191 }
1192 else
1193 {
1194 g_hvd_nal_fill_pair[1][0] = item[0];
1195 g_hvd_nal_fill_pair[1][1] = item[1];
1196 g_hvd_nal_fill_pair[1][2] = item[2];
1197 g_hvd_nal_fill_pair[1][3] = item[3];
1198 g_hvd_nal_fill_pair[1][4] = item[4];
1199 g_hvd_nal_fill_pair[1][5] = item[5];
1200 g_hvd_nal_fill_pair[1][6] = item[6];
1201 g_hvd_nal_fill_pair[1][7] = item[7];
1202 }
1203 addr = gSubHVDCtrl.MemMap.u32CodeBufAddr + HVD_BBU_DRAM_ST_ADDR + ((u32BBUWptr-(u32BBUWptr%2))<<3);
1204 HVD_UDMA_memcpy((void*)addr, (void*)g_hvd_nal_fill_pair, 16);
1205 #else
1206 addr = (pHVDCtrl_Hal->MemMap.u32CodeBufVAddr)+ HVD_BBU_DRAM_ST_ADDR + (u32BBUWptr<<3);
1207 HVD_memcpy((void*)addr, (void*)item, 8);
1208 _HVD_Sub_Chip_Flush_Memory();
1209 //HVD_SUB_MSG_DEG( "in UpdateESWptr:%lx %lx %lx\n" , addr , pHVDCtrl_Hal->MemMap.u32CodeBufVAddr , u32BBUWptr );
1210 #endif
1211 // add nal ptr
1212 //_HAL_HVD_Sub_SetBBUWriteptr( HVD_LWORD(u32BBUNewWptr) );
1213 u32BBUWptr = u32BBUNewWptr;
1214
1215 return E_HVD_RETURN_SUCCESS;
1216
1217 }
1218
_HAL_HVD_Sub_GetVUIDispInfo(void)1219 static MS_U32 _HAL_HVD_Sub_GetVUIDispInfo(void)
1220 {
1221 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC)
1222 {
1223 MS_U32 VUIstaddr = 0;
1224 MS_U16 u16Count=0;
1225 MS_U32 *pData = (MS_U32 *)(&g_hvd_VUIINFO);
1226 _HVD_Sub_Chip_Read_Memory();
1227 VUIstaddr=pHVDShareMem->u32AVC_VUIDispInfo_Addr;
1228 for(u16Count =0; u16Count < sizeof(HVD_AVC_VUI_DISP_INFO); u16Count+=4)
1229 {
1230 *pData = HAL_VPU_MemRead(VUIstaddr + u16Count);
1231 pData++;
1232 }
1233 }
1234 else
1235 {
1236 HVD_memset( &g_hvd_VUIINFO , 0 , sizeof(HVD_AVC_VUI_DISP_INFO) );
1237 }
1238 return (MS_U32 )(&g_hvd_VUIINFO);
1239 }
1240
_HAL_HVD_Sub_GetBBUQNumb(void)1241 MS_U32 _HAL_HVD_Sub_GetBBUQNumb(void)
1242 {
1243 MS_U32 u32ReadPtr=0;
1244 MS_U32 eRet=0;
1245
1246 u32ReadPtr =_HAL_HVD_Sub_GetBBUReadptr();
1247 //HVD_SUB_MSG_DEG("_HAL_HVD_Sub_GetBBUQNumb:%lx %lx %lx\n" , u32ReadPtr , u32BBUWptr ,(MS_U32)u32BBUEntryNum );
1248 if( u32BBUWptr >= u32ReadPtr )
1249 {
1250 eRet = u32BBUWptr - u32ReadPtr;
1251 }
1252 else
1253 {
1254 eRet = u32BBUEntryNum -( u32ReadPtr -u32BBUWptr );
1255 }
1256 return eRet;
1257 }
1258
_HAL_HVD_Sub_GetPTSQNumb(void)1259 MS_U32 _HAL_HVD_Sub_GetPTSQNumb(void)
1260 {
1261 MS_U32 u32ReadPtr=0;
1262 MS_U32 eRet=0;
1263 u32ReadPtr=HAL_VPU_MemRead( u32PTSRptrAddr );
1264 if( u32ReadPtr >= MAX_PTS_TABLE_SIZE )
1265 {
1266 HVD_SUB_MSG_ERR("HVD ERR: GetPTSQNumb: PTS table Read Ptr(%lx) > max table size(%lx) \n" ,u32ReadPtr ,(MS_U32)MAX_PTS_TABLE_SIZE);
1267 return 0;
1268 }
1269 //HVD_SUB_MSG_DEG("_HAL_HVD_Sub_GetBBUQNumb:%lx %lx %lx\n" , u32ReadPtr , u32BBUWptr ,(MS_U32)u32BBUEntryNum );
1270 if( u32PTSPreWptr >= u32ReadPtr )
1271 {
1272 eRet = u32PTSPreWptr - u32ReadPtr;
1273 }
1274 else
1275 {
1276 eRet = MAX_PTS_TABLE_SIZE -( u32ReadPtr -u32PTSPreWptr );
1277 }
1278 return eRet;
1279 }
1280
HAL_HVD_Sub_EnableISR(MS_BOOL bEnable)1281 void HAL_HVD_Sub_EnableISR(MS_BOOL bEnable)
1282 {
1283 if(bEnable)
1284 {
1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK);
1286 }
1287 else
1288 {
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
1290 }
1291 return;
1292 }
1293
HAL_HVD_Sub_CheckMIUSel(MS_BOOL bChange)1294 void HAL_HVD_Sub_CheckMIUSel(MS_BOOL bChange)
1295 {
1296 #if 1
1297 return;
1298 #else
1299 #if defined(CHIP_U3)
1300 if( pHVDCtrl_Hal->InitParams.bDynamicScaling )
1301 {
1302 if( pHVDCtrl_Hal->MemMap.u32DynSacalingBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1303 {
1304 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1305 {
1306 HVD_SUB_MSG_ERR("HVD Drv Err: dynamic scaling address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1307 if( bChange )
1308 {
1309 // VPU qdma WR
1310 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1311 }
1312 }
1313 }
1314 else
1315 {
1316 if( ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1317 {
1318 HVD_SUB_MSG_ERR("HVD Drv Err: dynamic scaling address(%lx) is at MIU0, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1319 if( bChange )
1320 {
1321 // VPU qdma WR
1322 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1323 }
1324 }
1325 }
1326 }
1327 #endif
1328
1329 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1330 {
1331 #if defined(CHIP_U3)
1332 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) == BIT(9)) )
1333 {
1334 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU d-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)));
1335 if( bChange )
1336 {
1337 // VPU d-cache WR
1338 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(9), BIT(9));
1339 }
1340 }
1341 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) == BIT(13)) )
1342 {
1343 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(13)) );
1344 if( bChange )
1345 {
1346 // VPU qdma WR
1347 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(13), BIT(13));
1348 }
1349 }
1350 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) == BIT(13)) )
1351 {
1352 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU i-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(13)) );
1353 if( bChange )
1354 {
1355 // VPU i-cache WR
1356 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(13), BIT(13));
1357 }
1358 }
1359 #endif
1360 #if defined(CHIP_T3)
1361 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) == BIT(7)) )
1362 {
1363 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU d-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(7)) );
1364 if( bChange )
1365 {
1366 // VPU d-cache WR
1367 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(7), BIT(7));
1368 }
1369 }
1370 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) == BIT(8)) )
1371 {
1372 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU qdma WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(8)) );
1373 if( bChange )
1374 {
1375 // VPU qdma WR
1376 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(8), BIT(8));
1377 }
1378 }
1379 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) == BIT(9)) )
1380 {
1381 HVD_SUB_MSG_ERR("HVD Drv Err: code start address(%lx) is at MIU1, but MIU sel is set(VPU i-cache WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr, (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(9)) );
1382 if( bChange )
1383 {
1384 // VPU i-cache WR
1385 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(9), BIT(9));
1386 }
1387 }
1388 #endif
1389 }
1390 if( pHVDCtrl_Hal->MemMap.u32FrameBufAddr>= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1391 {
1392 #if defined(CHIP_U3)
1393 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) )
1394 {
1395 HVD_SUB_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(HVD RW) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)));
1396 if( bChange )
1397 {
1398 // HVD RW
1399 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(12), BIT(12));
1400 }
1401 }
1402 #endif
1403 #if defined(CHIP_T3)
1404 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)) )
1405 {
1406 HVD_SUB_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(HVD RW) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) );
1407 if( bChange )
1408 {
1409 // HVD RW
1410 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(10), BIT(10));
1411 }
1412 }
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) )
1414 {
1415 HVD_SUB_MSG_ERR("HVD Drv Err: Frame Buf address(%lx) is at MIU1, but MIU sel is set(MVD WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) );
1416 if( bChange )
1417 {
1418 // MVD WR
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4));
1420 }
1421 }
1422 #endif
1423 }
1424 if( pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr>= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
1425 {
1426 #if defined(CHIP_U3)
1427 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(0)) == BIT(0)) )
1428 {
1429 HVD_SUB_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(HVD BBU R) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(0)) );
1430 if( bChange )
1431 {
1432 // HVD BBU R
1433 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(0), BIT(0));
1434 }
1435 }
1436 if( !((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)) )
1437 {
1438 HVD_SUB_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(MVD WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr, (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) );
1439 if( bChange )
1440 {
1441 // MVD WR
1442 _HVD_WriteWordMask(MIU0_REG_SEL2 , BIT(6), BIT(6));
1443 }
1444 }
1445 #endif
1446 #if defined(CHIP_T3)
1447 if( !((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(11)) == BIT(11)) )
1448 {
1449 HVD_SUB_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(HVD BBU R) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(11)) );
1450 if( bChange )
1451 {
1452 // HVD BBU R
1453 _HVD_WriteWordMask(MIU0_REG_SEL0 , BIT(11), BIT(11));
1454 }
1455 }
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) )
1457 {
1458 HVD_SUB_MSG_ERR("HVD Drv Err: Bitstream Buf address(%lx) is at MIU1, but MIU sel is set(MVD BBU WR) to MIU0. (MIU1 base:%lx) (reg:%lx)\n" , pHVDCtrl_Hal->MemMap.u32CodeBufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) );
1459 if( bChange )
1460 {
1461 // MVD BBU WR
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5));
1463 }
1464 }
1465 #endif
1466 }
1467 #endif
1468 }
1469
HAL_HVD_Sub_Get_HWVersionID(void)1470 MS_U32 HAL_HVD_Sub_Get_HWVersionID(void)
1471 {
1472 return _HVD_Read2Byte(HVD_REG_REV_ID);
1473 }
1474
HAL_HVD_Sub_PowerCtrl(MS_BOOL bEnable)1475 void HAL_HVD_Sub_PowerCtrl(MS_BOOL bEnable)
1476 {
1477 if( bEnable)
1478 {
1479 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS , TOP_CKG_HVD_DIS );
1480 }
1481 else
1482 {
1483 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS , TOP_CKG_HVD_DIS );
1484 }
1485 // fix to not inverse
1486 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV , TOP_CKG_HVD_INV );
1487 switch( u32HVDClockType )
1488 {
1489 case 172:
1490 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ , TOP_CKG_HVD_CLK_MASK);
1491 break;
1492 case 160:
1493 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ , TOP_CKG_HVD_CLK_MASK);
1494 break;
1495 case 144:
1496 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_144MHZ , TOP_CKG_HVD_CLK_MASK);
1497 break;
1498 case 123:
1499 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_123MHZ , TOP_CKG_HVD_CLK_MASK);
1500 break;
1501 default:
1502 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ , TOP_CKG_HVD_CLK_MASK);
1503 break;
1504 }
1505 return;
1506 }
1507
HAL_HVD_Sub_InitRegBase(MS_U32 u32RegBase)1508 void HAL_HVD_Sub_InitRegBase(MS_U32 u32RegBase)
1509 {
1510 u32HVDRegOSBase = u32RegBase;
1511 HAL_VPU_InitRegBase( u32RegBase );
1512 }
1513
HAL_HVD_Sub_InitVariables(MS_U32 drvctrl)1514 HVD_Return HAL_HVD_Sub_InitVariables(MS_U32 drvctrl)
1515 {
1516 HVD_Drv_Ctrl *pHVDCtrl_in = (HVD_Drv_Ctrl*)drvctrl;
1517
1518 // local variables
1519 u32PTSPreWptr = 0;
1520 u32PTSRptrAddr = 0;
1521 u32PTSWptrAddr = 0;
1522 u32PTSByteCnt = 0;
1523 u32BBUWptr = 0;
1524 u32BBURptr = 0;
1525
1526 HVD_memset((void *) g_hvd_nal_fill_pair, 0, 16);
1527
1528 // global variables
1529 u32HVDCmdTimeout = pHVDCtrl_in->u32CmdTimeout;
1530 pHVDCtrl_Hal = pHVDCtrl_in;
1531 u32VPUClockType = (MS_U32)pHVDCtrl_in->InitParams.u16DecoderClock;
1532 u32HVDClockType = (MS_U32)pHVDCtrl_in->InitParams.u16DecoderClock;
1533 // Create mutex
1534 _HAL_HVD_MutexCreate();
1535
1536 // fill HVD init variables
1537 #if defined(UDMA_FPGA_ENVI)
1538 pHVDShareMem = &UDMA_pc_HVDShareMem;
1539 UDMA_fpga_HVDShareMemAddr = pHVDCtrl_in->MemMap.u32CodeBufVAddr + HVD_SHARE_MEM_ST_OFFSET ;
1540 #else
1541 pHVDShareMem = (volatile HVD_ShareMem *)((pHVDCtrl_in->MemMap.u32CodeBufVAddr) + HVD_SHARE_MEM_ST_OFFSET);
1542 #endif
1543
1544 #if HVD_ENABLE_RV_FEATURE
1545 if( ((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM )
1546 {
1547 u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
1548 u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
1549 if (pHVDCtrl_Hal->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
1550 {
1551 u32RV_VLCTableAddr = pHVDCtrl_Hal->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
1552 pHVDCtrl_Hal->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
1553 }
1554 else
1555 {
1556 HVD_SUB_MSG_ERR("HAL_HVD_InitVariables failed: frame buffer size too small. FB:%lx min:%lx\n",
1557 (MS_U32)pHVDCtrl_Hal->MemMap.u32FrameBufSize, (MS_U32)RV_VLC_TABLE_SIZE);
1558 return E_HVD_RETURN_INVALID_PARAMETER;
1559 }
1560 }
1561 else
1562 #endif
1563 {
1564 u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
1565 u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
1566 u32RV_VLCTableAddr = 0;
1567 }
1568
1569 if( (( (pHVDCtrl_in->MemMap.u32CodeBufVAddr )<= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32CodeBufVAddr )+ pHVDCtrl_in->MemMap.u32CodeBufSize)))
1570 || (( (pHVDCtrl_in->MemMap.u32BitstreamBufVAddr)<= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in->MemMap.u32BitstreamBufSize)))
1571 || (( (pHVDCtrl_in->MemMap.u32FrameBufVAddr) <= (MS_U32)pHVDShareMem)&& ( (MS_U32)pHVDShareMem <= ((pHVDCtrl_in->MemMap.u32FrameBufVAddr) + pHVDCtrl_in->MemMap.u32FrameBufSize))) )
1572 {
1573 HVD_SUB_MSG_DEG("input memory: %lx %lx %lx %lx\n",
1574 pHVDCtrl_in->MemMap.u32CodeBufAddr,
1575 pHVDCtrl_in->MemMap.u32FrameBufAddr,
1576 pHVDCtrl_in->MemMap.u32BitstreamBufAddr,
1577 pHVDCtrl_in->MemMap.u32MIU1BaseAddr);
1578 return E_HVD_RETURN_SUCCESS;
1579 }
1580 else
1581 {
1582 HVD_SUB_MSG_ERR("HAL_HVD_InitVariables failed: %lx %lx %lx %lx %lx\n",
1583 (MS_U32)pHVDShareMem,
1584 pHVDCtrl_in->MemMap.u32CodeBufVAddr,
1585 pHVDCtrl_in->MemMap.u32FrameBufVAddr,
1586 pHVDCtrl_in->MemMap.u32BitstreamBufVAddr,
1587 pHVDCtrl_in->MemMap.u32MIU1BaseAddr);
1588 return E_HVD_RETURN_INVALID_PARAMETER;
1589 }
1590 }
1591
HAL_HVD_Sub_InitShareMem(void)1592 HVD_Return HAL_HVD_Sub_InitShareMem(void)
1593 {
1594 MS_U32 u32Addr = 0;
1595
1596 HVD_memset((volatile void *)pHVDShareMem, 0, sizeof(HVD_ShareMem));
1597 u32Addr = pHVDCtrl_Hal->MemMap.u32FrameBufAddr;
1598 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1599 {
1600 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1601 }
1602 pHVDShareMem->u32FrameRate = pHVDCtrl_Hal->InitParams.u32FrameRate;
1603 pHVDShareMem->u32FrameRateBase = pHVDCtrl_Hal->InitParams.u32FrameRateBase;
1604 pHVDShareMem->u32FrameBufAddr = u32Addr;
1605 pHVDShareMem->u32FrameBufSize = pHVDCtrl_Hal->MemMap.u32FrameBufSize;
1606 pHVDShareMem->DispInfo.u16DispWidth = 1;
1607 pHVDShareMem->DispInfo.u16DispHeight = 1;
1608 pHVDShareMem->u32CodecType = pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
1609 pHVDShareMem->u32CPUClock = u32VPUClockType;
1610 pHVDShareMem->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
1611 pHVDShareMem->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
1612 //Chip info
1613 pHVDShareMem->u16ChipID = E_MSTAR_CHIP_T8;
1614 pHVDShareMem->u16ChipECONum = 0;
1615
1616 if (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_FILE_RAW)
1617 {
1618 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_FILE;
1619 }
1620 else if (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_FILE_TS)
1621 {
1622 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
1623 }
1624 else
1625 {
1626 pHVDShareMem->u8SrcMode = E_HVD_SRC_MODE_DTV;
1627 }
1628
1629 #if 1 //From T4 and the later chips, QDMA can support the address more than MIU1 base.
1630 pHVDShareMem->u32FWBaseAddr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1631 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pHVDShareMem->u32FWBaseAddr);
1632 #else
1633 u32Addr = pHVDCtrl_Hal->MemMap.u32CodeBufAddr;
1634 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1635 {
1636 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1637 }
1638 pHVDShareMem->u32FWBaseAddr = u32Addr;
1639 #endif
1640 // RM only
1641 #if HVD_ENABLE_RV_FEATURE
1642 if( (((pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
1643 && (pHVDCtrl_Hal->InitParams.pRVFileInfo != NULL) )
1644 {
1645 MS_U32 i = 0;
1646 for(i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
1647 {
1648 pHVDShareMem->pRM_PictureSize[i].u16Width = pHVDCtrl_Hal->InitParams.pRVFileInfo->ulPicSizes_w[i];
1649 pHVDShareMem->pRM_PictureSize[i].u16Height = pHVDCtrl_Hal->InitParams.pRVFileInfo->ulPicSizes_h[i];
1650 }
1651 pHVDShareMem->u8RM_Version = (MS_U8)pHVDCtrl_Hal->InitParams.pRVFileInfo->RV_Version;
1652 pHVDShareMem->u8RM_NumSizes = (MS_U8)pHVDCtrl_Hal->InitParams.pRVFileInfo->ulNumSizes;
1653 u32Addr = pHVDCtrl_Hal->MemMap.u32FrameBufAddr + u32RV_VLCTableAddr;
1654 if (u32Addr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1655 {
1656 u32Addr -= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr;
1657 }
1658 pHVDShareMem->u32RM_VLCTableAddr = u32Addr;
1659 }
1660 #endif
1661 #if defined(UDMA_FPGA_ENVI)
1662 HVD_UDMA_memcpy((void *)UDMA_fpga_HVDShareMemAddr,
1663 &UDMA_pc_HVDShareMem,
1664 sizeof(HVD_Display_Info));
1665 #endif
1666 _HVD_Sub_Chip_Flush_Memory();
1667 return E_HVD_RETURN_SUCCESS;
1668 }
1669
HAL_HVD_Sub_InitRegCPU(void)1670 HVD_Return HAL_HVD_Sub_InitRegCPU( void)
1671 {
1672 MS_BOOL bInitRet=FALSE;
1673
1674 //_HAL_HVD_Entry();
1675 // Init VPU
1676 {
1677 VPU_Init_Params VPUInitParams = { E_VPU_CLOCK_160MHZ , FALSE , -1, VPU_DEFAULT_MUTEX_TIMEOUT, FALSE};
1678 switch( u32VPUClockType )
1679 {
1680 case 160:
1681 VPUInitParams.eClockSpeed=E_VPU_CLOCK_160MHZ;
1682 break;
1683 case 144:
1684 VPUInitParams.eClockSpeed=E_VPU_CLOCK_144MHZ;
1685 break;
1686 case 108:
1687 VPUInitParams.eClockSpeed=E_VPU_CLOCK_108MHZ;
1688 break;
1689 case 72:
1690 VPUInitParams.eClockSpeed=E_VPU_CLOCK_72MHZ;
1691 break;
1692 default:
1693 break;
1694 }
1695 #if HAL_HVD_ENABLE_MUTEX_PROTECT
1696 VPUInitParams.s32VPUMutexID = s32HVDMutexID;
1697 #endif
1698
1699 if(pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr)
1700 {
1701 VPUInitParams.bInMIU1 = TRUE;
1702 }
1703 else
1704 {
1705 VPUInitParams.bInMIU1 = FALSE;
1706 }
1707
1708 HAL_VPU_Init(&VPUInitParams);
1709 }
1710 HAL_HVD_Sub_MVD_PowerCtrl( TRUE );
1711 #if 0
1712 // check MVD power on
1713 if( _HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS) )
1714 {
1715 HVD_SUB_MSG_INFO( "HVD warning: MVD is not power on before HVD init.\n" );
1716 _HVD_WriteWordMask(REG_TOP_MVD, 0 , TOP_CKG_MHVD_DIS );
1717 HVD_Delay_ms(1);
1718 }
1719 // Check VPU power on
1720 if( _HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS) )
1721 {
1722 HVD_SUB_MSG_INFO( "HVD warning: VPU is not power on before HVD init.\n" );
1723 _HVD_WriteWordMask(REG_TOP_VPU, 0 , TOP_CKG_VPU_DIS );
1724 HVD_Delay_ms(1);
1725 }
1726 // check HVD power on
1727 if( _HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS) )
1728 {
1729 HVD_SUB_MSG_INFO( "HVD warning: HVD is not power on before HVD init.\n" );
1730 HAL_HVD_PowerCtrl(TRUE);
1731 HVD_Delay_ms(1);
1732 }
1733 #endif
1734 bInitRet = _HAL_HVD_Sub_SetRegCPU();
1735 if( !bInitRet )
1736 {
1737 //_HAL_HVD_Return( E_HVD_RETURN_FAIL);
1738 return E_HVD_RETURN_FAIL;
1739 }
1740 bInitRet=HAL_HVD_Sub_RstPTSCtrlVariable();
1741 if( !bInitRet )
1742 {
1743 //_HAL_HVD_Return( E_HVD_RETURN_FAIL);
1744 return E_HVD_RETURN_FAIL;
1745 }
1746 //_HAL_HVD_Return( E_HVD_RETURN_SUCCESS);
1747 return E_HVD_RETURN_SUCCESS;
1748 }
1749
HAL_HVD_Sub_SetData(HVD_SetData u32type,MS_U32 u32Data)1750 HVD_Return HAL_HVD_Sub_SetData( HVD_SetData u32type , MS_U32 u32Data)
1751 {
1752 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
1753 //_HAL_HVD_Entry();
1754 switch(u32type)
1755 {
1756 // share memory
1757 // switch
1758 case E_HVD_SDATA_FRAMEBUF_ADDR:
1759 pHVDShareMem->u32FrameBufAddr = u32Data;
1760 break;
1761 case E_HVD_SDATA_FRAMEBUF_SIZE:
1762 pHVDShareMem->u32FrameBufSize= u32Data;
1763 break;
1764 case E_HVD_SDATA_RM_PICTURE_SIZES:
1765 HVD_memcpy( (volatile void*)pHVDShareMem->pRM_PictureSize, (void*)((HVD_PictureSize*)u32Data) , HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof( HVD_PictureSize ) );
1766 break;
1767 case E_HVD_SDATA_ERROR_CODE:
1768 pHVDShareMem->u16ErrCode= (MS_U16)u32Data;
1769 break;
1770 case E_HVD_SDATA_DISP_INFO_TH:
1771 HVD_memcpy((volatile void*)&(pHVDShareMem->DispThreshold), (void*)((HVD_DISP_THRESHOLD*)u32Data), sizeof(HVD_DISP_THRESHOLD) );
1772 break;
1773 // SRAM
1774
1775 // Mailbox
1776 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
1777 if( u32Data != 0)
1778 {
1779 _HAL_HVD_Sub_MBoxSend( HAL_HVD_REG_DISP_CTL , 1 );
1780 }
1781 else
1782 {
1783 _HAL_HVD_Sub_MBoxSend( HAL_HVD_REG_DISP_CTL , 0 );
1784 }
1785 break;
1786
1787 case E_HVD_SDATA_GET_DISP_INFO_DONE:
1788 _HAL_HVD_Sub_MBoxClear( HAL_HVD_REG_DISP_INFO_CHANGE );
1789 break;
1790
1791 case E_HVD_SDATA_GET_DISP_INFO_START:
1792 _HAL_HVD_Sub_MBoxClear( HAL_HVD_REG_DISP_INFO_COPYED );
1793 break;
1794
1795 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
1796 pHVDShareMem->u32VirtualBoxWidth = u32Data;
1797 break;
1798
1799 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
1800 pHVDShareMem->u32VirtualBoxHeight = u32Data;
1801 break;
1802
1803 default:
1804 break;
1805 }
1806
1807 #if defined(UDMA_FPGA_ENVI)
1808 if( u32type & E_HVD_SDATA_SHARE_MEM )
1809 {
1810 HVD_UDMA_memcpy( (void*)UDMA_fpga_HVDShareMemAddr , &UDMA_pc_HVDShareMem , sizeof(HVD_Display_Info ) );
1811 }
1812 #endif
1813 _HVD_Sub_Chip_Flush_Memory();
1814
1815 //_HAL_HVD_Return( eRet);
1816 return eRet;
1817 }
1818
HAL_HVD_Sub_GetData(HVD_GetData eType)1819 MS_U32 HAL_HVD_Sub_GetData( HVD_GetData eType )
1820 {
1821 MS_U32 u32Ret=0;
1822 //_HAL_HVD_Entry();
1823 #if defined(UDMA_FPGA_ENVI)
1824 if( eType & E_HVD_SDATA_SHARE_MEM )
1825 {
1826 HVD_UDMA_memcpy( &UDMA_pc_HVDShareMem , (void*)UDMA_fpga_HVDShareMemAddr , sizeof(HVD_Display_Info ) );
1827 }
1828 #endif
1829 _HVD_Sub_Chip_Read_Memory();
1830 switch( eType )
1831 {
1832 // share memory
1833 // switch
1834 case E_HVD_GDATA_DISP_INFO_ADDR:
1835 u32Ret = (MS_U32)(&pHVDShareMem->DispInfo);
1836 break;
1837 // report
1838 case E_HVD_GDATA_PTS:
1839 u32Ret=pHVDShareMem->DispFrmInfo.u32TimeStamp;
1840 break;
1841 case E_HVD_GDATA_DECODE_CNT:
1842 u32Ret=pHVDShareMem->u32DecodeCnt;
1843 break;
1844 case E_HVD_GDATA_DATA_ERROR_CNT:
1845 u32Ret=pHVDShareMem->u32DataErrCnt;
1846 break;
1847 case E_HVD_GDATA_DEC_ERROR_CNT:
1848 u32Ret=pHVDShareMem->u32DecErrCnt;
1849 break;
1850 case E_HVD_GDATA_ERROR_CODE:
1851 u32Ret=(MS_U32)(pHVDShareMem->u16ErrCode);
1852 break;
1853 case E_HVD_GDATA_VPU_IDLE_CNT:
1854 u32Ret=pHVDShareMem->u32VPUIdleCnt;
1855 break;
1856 case E_HVD_GDATA_DISP_FRM_INFO:
1857 u32Ret=(MS_U32)(&(pHVDShareMem->DispFrmInfo));
1858 break;
1859 case E_HVD_GDATA_DEC_FRM_INFO:
1860 u32Ret=(MS_U32)(&(pHVDShareMem->DecoFrmInfo));
1861 break;
1862 case E_HVD_GDATA_ES_LEVEL:
1863 u32Ret=(MS_U32)(_HAL_HVD_Sub_GetESLevel());
1864 break;
1865
1866 // user data
1867 case E_HVD_GDATA_USERDATA_WPTR:
1868 u32Ret=(MS_U32)(pHVDShareMem->u32UserCCIdxWrtPtr);
1869 break;
1870 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
1871 u32Ret=(MS_U32)(pHVDShareMem->u8UserCCIdx);
1872 break;
1873 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
1874 u32Ret=(MS_U32)(pHVDShareMem->u32UserCCBase);
1875 break;
1876 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
1877 u32Ret=(MS_U32)(sizeof(DTV_BUF_type));
1878 break;
1879 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
1880 u32Ret=(MS_U32)(USER_CC_IDX_SIZE);
1881 break;
1882 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
1883 u32Ret=(MS_U32)(USER_CC_DATA_SIZE);
1884 break;
1885 // report - modes
1886 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
1887 u32Ret=pHVDShareMem->ModeStatus.bIsShowErrFrm;
1888 break;
1889 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
1890 u32Ret=pHVDShareMem->ModeStatus.bIsRepeatLastField;
1891 break;
1892 case E_HVD_GDATA_IS_ERR_CONCEAL:
1893 u32Ret=pHVDShareMem->ModeStatus.bIsErrConceal;
1894 break;
1895 case E_HVD_GDATA_IS_SYNC_ON:
1896 u32Ret=pHVDShareMem->ModeStatus.bIsSyncOn;
1897 break;
1898 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
1899 u32Ret=pHVDShareMem->ModeStatus.bIsPlaybackFinish;
1900 break;
1901 case E_HVD_GDATA_SYNC_MODE:
1902 u32Ret=pHVDShareMem->ModeStatus.u8SyncType;
1903 break;
1904 case E_HVD_GDATA_SKIP_MODE:
1905 u32Ret=pHVDShareMem->ModeStatus.u8SkipMode;
1906 break;
1907 case E_HVD_GDATA_DROP_MODE:
1908 u32Ret=pHVDShareMem->ModeStatus.u8DropMode;
1909 break;
1910 case E_HVD_GDATA_DISPLAY_DURATION:
1911 u32Ret=pHVDShareMem->ModeStatus.s8DisplaySpeed;
1912 break;
1913 case E_HVD_GDATA_FRC_MODE:
1914 u32Ret=pHVDShareMem->ModeStatus.u8FrcMode;
1915 break;
1916 case E_HVD_GDATA_NEXT_PTS:
1917 u32Ret=pHVDShareMem->u32NextPTS;
1918 break;
1919
1920 // internal control
1921 case E_HVD_GDATA_IS_1ST_FRM_RDY:
1922 u32Ret=pHVDShareMem->bIs1stFrameRdy;
1923 break;
1924 case E_HVD_GDATA_IS_I_FRM_FOUND:
1925 u32Ret=pHVDShareMem->bIsIFrmFound;
1926 break;
1927 case E_HVD_GDATA_IS_SYNC_START:
1928 u32Ret=pHVDShareMem->bIsSyncStart;
1929 break;
1930 case E_HVD_GDATA_IS_SYNC_REACH:
1931 u32Ret=pHVDShareMem->bIsSyncReach;
1932 break;
1933 case E_HVD_GDATA_FW_VERSION_ID:
1934 u32Ret=pHVDShareMem->u32FWVersionID;
1935 break;
1936 case E_HVD_GDATA_FW_IF_VERSION_ID:
1937 u32Ret=pHVDShareMem->u32FWIfVersionID;
1938 break;
1939 case E_HVD_GDATA_BBU_Q_NUMB:
1940 u32Ret=_HAL_HVD_Sub_GetBBUQNumb();
1941 break;
1942 case E_HVD_GDATA_DEC_Q_NUMB:
1943 u32Ret=pHVDShareMem->u16DecQNumb;
1944 break;
1945 case E_HVD_GDATA_DISP_Q_NUMB:
1946 u32Ret=pHVDShareMem->u16DispQNumb;
1947 break;
1948 case E_HVD_GDATA_PTS_Q_NUMB:
1949 u32Ret=_HAL_HVD_Sub_GetPTSQNumb();
1950 break;
1951 case E_HVD_GDATA_FW_INIT_DONE:
1952 u32Ret=pHVDShareMem->bInitDone;
1953 break;
1954
1955 // debug
1956 case E_HVD_GDATA_SKIP_CNT:
1957 u32Ret=pHVDShareMem->u32SkipCnt;
1958 break;
1959 case E_HVD_GDATA_GOP_CNT:
1960 u32Ret=pHVDShareMem->u32DropCnt;
1961 break;
1962 case E_HVD_GDATA_DISP_CNT:
1963 u32Ret= pHVDShareMem->u32DispCnt;
1964 break;
1965 case E_HVD_GDATA_DROP_CNT:
1966 u32Ret= pHVDShareMem->u32DropCnt;
1967 break;
1968 case E_HVD_GDATA_DISP_STC:
1969 u32Ret= pHVDShareMem->u32DispSTC;
1970 break;
1971 case E_HVD_GDATA_VSYNC_CNT:
1972 u32Ret= pHVDShareMem->u32VsyncCnt;
1973 break;
1974 case E_HVD_GDATA_MAIN_LOOP_CNT:
1975 u32Ret= pHVDShareMem->u32MainLoopCnt;
1976 break;
1977
1978 // AVC
1979 case E_HVD_GDATA_AVC_LEVEL_IDC:
1980 u32Ret=pHVDShareMem->u16AVC_SPS_LevelIDC;
1981 break;
1982 case E_HVD_GDATA_AVC_LOW_DELAY:
1983 u32Ret=pHVDShareMem->u8AVC_SPS_LowDelayHrdFlag;
1984 break;
1985 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
1986 u32Ret=_HAL_HVD_Sub_GetVUIDispInfo();
1987 break;
1988
1989 // SRAM
1990
1991 // Mailbox
1992 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
1993 u32Ret=_HAL_HVD_Sub_GetFWState();
1994 break;
1995 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
1996 u32Ret=_HAL_HVD_Sub_MBoxReady( HAL_HVD_REG_DISP_INFO_COPYED );
1997 break;
1998 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
1999 u32Ret=_HAL_HVD_Sub_MBoxReady( HAL_HVD_REG_DISP_INFO_CHANGE );
2000 break;
2001 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
2002 _HAL_HVD_Sub_MBoxRead(HAL_HVD_REG_ISR_HVD , &u32Ret );
2003 break;
2004 case E_HVD_GDATA_VPU_ISR_STATUS: // VPU RISC MBOX 1 (value only)
2005 _HAL_HVD_Sub_MBoxRead(HAL_HVD_REG_ISR_VPU , &u32Ret );
2006 break;
2007 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
2008 if( _HAL_HVD_Sub_MBoxReady( HAL_HVD_REG_DISP_CTL ) )
2009 {
2010 u32Ret = TRUE;
2011 }
2012 else
2013 {
2014 u32Ret = FALSE;
2015 }
2016 break;
2017 case E_HVD_GDATA_ES_READ_PTR: //
2018 u32Ret= _HAL_HVD_Sub_GetESReadPtr(FALSE);
2019 break;
2020 case E_HVD_GDATA_ES_WRITE_PTR: //
2021 u32Ret= _HAL_HVD_Sub_GetESWritePtr();
2022 break;
2023 case E_HVD_GDATA_BBU_READ_PTR:
2024 u32Ret= _HAL_HVD_Sub_GetBBUReadptr();
2025 break;
2026 case E_HVD_GDATA_BBU_WRITE_PTR:
2027 u32Ret= u32BBUWptr;
2028 break;
2029 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
2030 u32Ret= pHVDCtrl_Hal->u32BBUWptr_Fired;
2031 break;
2032
2033 case E_HVD_GDATA_VPU_PC_CNT:
2034 u32Ret= _HAL_HVD_Sub_GetPC();
2035 break;
2036
2037
2038 // FW def
2039 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
2040 u32Ret=HVD_MAX3( HVD_FW_AVC_DUMMY_FIFO , HVD_FW_AVS_DUMMY_FIFO , HVD_FW_RM_DUMMY_FIFO );
2041 break;
2042
2043 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
2044 u32Ret=HVD_FW_AVC_MAX_VIDEO_DELAY;
2045 break;
2046 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
2047 u32Ret=u32BBUEntryNumTH ;
2048 break;
2049 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
2050 u32Ret=u32BBUEntryNum ;
2051 break;
2052 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
2053 u32Ret=MAX_PTS_TABLE_SIZE;
2054 break;
2055 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
2056 u32Ret=HVD_DUMMY_WRITE_ADDR ;
2057 break;
2058 case E_HVD_GDATA_FW_DS_BUF_ADDR:
2059 u32Ret=HVD_DYNAMIC_SCALING_ADDR ;
2060 break;
2061 case E_HVD_GDATA_FW_DS_BUF_SIZE:
2062 u32Ret=HVD_DYNAMIC_SCALING_SIZE ;
2063 break;
2064 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
2065 u32Ret=HVD_DYNAMIC_SCALING_DEPTH ;
2066 break;
2067 case E_HVD_GDATA_FW_DS_INFO_ADDR:
2068 u32Ret=HVD_SCALER_INFO_ADDR;
2069 break;
2070
2071 default:
2072 break;
2073 }
2074 //_HAL_HVD_Return( u32Ret);
2075 return u32Ret;
2076 }
2077
HAL_HVD_Sub_SetCmd(HVD_User_Cmd u32Cmd,MS_U32 u32CmdArg)2078 HVD_Return HAL_HVD_Sub_SetCmd( HVD_User_Cmd u32Cmd , MS_U32 u32CmdArg)
2079 {
2080 HVD_Return eRet=E_HVD_RETURN_SUCCESS;
2081 _HAL_HVD_Entry();
2082
2083 // old SVD cmds
2084 if( (MS_U32)u32Cmd < E_HVD_CMD_SVD_BASE )
2085 {
2086 //if( (MS_U32)u32Cmd < E_HVD_CMD_SVD_BASE )
2087 {
2088 HVD_SUB_MSG_ERR("HVD Err: Old SVD FW cmd(%lx %lx) used in HVD.\n" , (MS_U32)u32Cmd ,u32CmdArg );
2089 }
2090 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
2091 }
2092 HVD_SUB_MSG_DEG("HVD DBG: Send cmd:0x%lx Arg:0x%lx\n", (MS_U32)u32Cmd , (MS_U32)u32CmdArg );
2093 eRet=_HAL_HVD_Sub_SendCmd( (MS_U32)u32Cmd , u32CmdArg );
2094 _HAL_HVD_Return( eRet);
2095 }
2096
HAL_HVD_Sub_DeInit(void)2097 HVD_Return HAL_HVD_Sub_DeInit(void)
2098 {
2099 HVD_Return eRet=E_HVD_RETURN_FAIL;
2100 //MS_U32 u32FWState=0;
2101 //MS_U32 Timer=50; // ms
2102 #if HVD_ENABLE_TIME_MEASURE
2103 MS_U32 ExitTimeCnt=0;
2104 ExitTimeCnt = HVD_GetSysTime_ms();
2105 #endif
2106 eRet=HAL_HVD_Sub_SetCmd(E_HVD_CMD_PAUSE, 0);
2107 if (E_HVD_RETURN_SUCCESS != eRet)
2108 HVD_SUB_MSG_ERR("HVDERR %s(%d) HVD fail to PAUSE %d\n", __FUNCTION__, __LINE__, eRet);
2109
2110 eRet=HAL_HVD_Sub_SetCmd(E_HVD_CMD_STOP, 0);
2111 _HAL_HVD_MutexDelete();
2112 /*
2113 while(Timer)
2114 {
2115 HVD_Delay_ms(1);
2116 u32FWState=HAL_HVD_GetData( E_HVD_GDATA_FW_STATE );
2117 switch( (pHVDCtrl_Hal->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK )
2118 {
2119 case E_HVD_INIT_HW_AVC:
2120 if( u32FWState == E_HVD_FW_STOP_DONE)
2121 {
2122 Timer=1;
2123 }
2124 break;
2125 case E_HVD_INIT_HW_AVS:
2126 if( u32FWState == E_HVD_FW_STOP)
2127 {
2128 Timer=1;
2129 }
2130 break;
2131 default:
2132 break;
2133 }
2134 Timer--;
2135 };
2136 */
2137 #if HVD_ENABLE_TIME_MEASURE
2138 HVD_SUB_MSG_DEG( "HVD Stop Time(Wait FW):%d\n" , HVD_GetSysTime_ms()-ExitTimeCnt );
2139 #endif
2140 //check MAU idle before reset VPU
2141 {
2142 MS_U32 mau_idle_cnt = 100;// ms
2143 while(mau_idle_cnt)
2144 {
2145 if(TRUE == HAL_VPU_MAU_IDLE())
2146 {
2147 break;
2148 }
2149 mau_idle_cnt--;
2150 HVD_Delay_ms(1);
2151 }
2152
2153 if(mau_idle_cnt == 0)
2154 {
2155 HVD_MSG_ERR("MAU idle time out~~~~~\n");
2156 }
2157 }
2158 HVD_MSG_DEG("%s(%d) HVD hold CPU\n", __FUNCTION__, __LINE__);
2159 HAL_VPU_SwRst(); //CPU hold
2160 {
2161 MS_U16 u16Timeout = 1000;
2162 _HAL_HVD_Sub_SetMIUProtectMask(TRUE);
2163 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST , HVD_REG_RESET_SWRST);
2164 while(u16Timeout)
2165 {
2166 if( (_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN))
2167 == (HVD_REG_RESET_SWRST_FIN))
2168 {
2169 break;
2170 }
2171 u16Timeout--;
2172 }
2173
2174 _HAL_HVD_Sub_RstMVDParser();
2175
2176 //HAL_VPU_PowerCtrl(FALSE);
2177 HAL_VPU_DeInit();
2178 HAL_HVD_Sub_PowerCtrl(FALSE);
2179 HAL_HVD_Sub_MVD_PowerCtrl( FALSE );
2180
2181 _HAL_HVD_Sub_SetMIUProtectMask(FALSE);
2182 }
2183 //HAL_HVD_Sub_MVD_PowerCtrl( FALSE );
2184 return eRet;
2185 }
2186
HAL_HVD_Sub_PushPacket(HVD_BBU_Info * pInfo)2187 HVD_Return HAL_HVD_Sub_PushPacket(HVD_BBU_Info* pInfo )
2188 {
2189 HVD_Return eRet=E_HVD_RETURN_UNSUPPORTED;
2190 MS_U32 u32Addr=0;
2191 //_HAL_HVD_Entry();
2192
2193 eRet=_HAL_HVD_Sub_UpdatePTSTable(pInfo);
2194 if( eRet != E_HVD_RETURN_SUCCESS )
2195 {
2196 //_HAL_HVD_Return( eRet);
2197 return eRet;
2198 }
2199
2200 //T8: for 128 bit memory. BBU need to get 2 entry at a time.
2201 eRet=_HAL_HVD_Sub_UpdateESWptr( 0 , 0);
2202 if( eRet != E_HVD_RETURN_SUCCESS )
2203 {
2204 //_HAL_HVD_Return( eRet);
2205 return eRet;
2206 }
2207
2208 u32Addr = pInfo->u32Staddr;
2209 if( pInfo->bRVBrokenPacket )
2210 {
2211 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT) ;
2212 }
2213 eRet=_HAL_HVD_Sub_UpdateESWptr( u32Addr , pInfo->u32Length);
2214 if( eRet != E_HVD_RETURN_SUCCESS )
2215 {
2216 //_HAL_HVD_Return( eRet);
2217 return eRet;
2218 }
2219 u32PTSByteCnt+=pInfo->u32Length;
2220
2221 // do not add local pointer
2222 #if 1
2223 if( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize !=0) && (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr !=0) )
2224 {
2225 MS_U32 u32PacketStaddr = pInfo->u32Staddr + pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr;
2226 if( !( (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr ) &&
2227 (u32PacketStaddr < (pHVDCtrl_Hal->MemMap.u32DrvProcessBufAddr + pHVDCtrl_Hal->MemMap.u32DrvProcessBufSize)) ) )
2228 {
2229 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32Staddr;
2230 pHVDCtrl_Hal->LastNal.u32NalSize= pInfo->u32Length;
2231 }
2232 else
2233 {
2234 //null packet
2235 pHVDCtrl_Hal->LastNal.u32NalAddr= pInfo->u32OriPktAddr;
2236 pHVDCtrl_Hal->LastNal.u32NalSize= 0;
2237 }
2238 }
2239 else
2240 {
2241 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32Staddr;
2242 pHVDCtrl_Hal->LastNal.u32NalSize= pInfo->u32Length;
2243 }
2244 #else
2245 pHVDCtrl_Hal->LastNal.u32NalAddr = pInfo->u32Staddr;
2246 pHVDCtrl_Hal->LastNal.u32NalSize= pInfo->u32Length;
2247 #endif
2248 pHVDCtrl_Hal->LastNal.bRVBrokenPacket=pInfo->bRVBrokenPacket;
2249
2250 pHVDCtrl_Hal->u32BBUPacketCnt++;
2251 return eRet;
2252 }
2253
HAL_HVD_Sub_Enable_ISR(MS_BOOL bEnable)2254 void HAL_HVD_Sub_Enable_ISR(MS_BOOL bEnable)
2255 {
2256 if(bEnable)
2257 {
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK );
2259 }
2260 else
2261 {
2262 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK );
2263 }
2264 }
2265
HAL_HVD_Sub_SetForceISR(MS_BOOL bEnable)2266 void HAL_HVD_Sub_SetForceISR(MS_BOOL bEnable)
2267 {
2268 if( bEnable )
2269 {
2270 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
2271 }
2272 else
2273 {
2274 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_FORCE);
2275 }
2276 }
2277
HAL_HVD_Sub_SetClearISR(void)2278 void HAL_HVD_Sub_SetClearISR(void)
2279 {
2280 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_CLR , HVD_REG_RISC_ISR_CLR);
2281 }
2282
HAL_HVD_Sub_IsISROccured(void)2283 MS_BOOL HAL_HVD_Sub_IsISROccured(void)
2284 {
2285 return (MS_BOOL)(_HVD_Read2Byte( HVD_REG_RISC_MBOX_RDY )& HVD_REG_RISC_ISR_VALID );
2286 }
2287
HAL_HVD_Sub_IsEnableISR(void)2288 MS_BOOL HAL_HVD_Sub_IsEnableISR(void)
2289 {
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK)
2291 {
2292 return FALSE;
2293 }
2294 else
2295 {
2296 return TRUE;
2297 }
2298 }
2299
HAL_HVD_Sub_RstPTSCtrlVariable(void)2300 MS_BOOL HAL_HVD_Sub_RstPTSCtrlVariable(void)
2301 {
2302 if( (pHVDCtrl_Hal->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV )
2303 {
2304 #if defined(UDMA_FPGA_ENVI)
2305 HVD_UDMA_memcpy( (void*)UDMA_fpga_HVDShareMemAddr , &UDMA_pc_HVDShareMem , sizeof(HVD_Display_Info ) );
2306 #endif
2307 _HVD_Sub_Chip_Read_Memory();
2308
2309 u32PTSRptrAddr=pHVDShareMem->u32PTStableRptrAddr;
2310 u32PTSWptrAddr=pHVDShareMem->u32PTStableWptrAddr;
2311 u32PTSByteCnt = pHVDShareMem->u32PTStableByteCnt;
2312 u32PTSPreWptr=HAL_VPU_MemRead( u32PTSWptrAddr );
2313 HVD_SUB_MSG_DEG( "HVD hal:PTS table: WptrAddr:%lx RptrAddr:%lx ByteCnt:%lx PreWptr:%lx\n" , u32PTSWptrAddr , u32PTSRptrAddr ,u32PTSByteCnt ,u32PTSPreWptr );
2314 }
2315 return TRUE;
2316 }
2317
HAL_HVD_Sub_FlushRstShareMem(void)2318 MS_BOOL HAL_HVD_Sub_FlushRstShareMem(void)
2319 {
2320 HVD_memset( &pHVDShareMem->DecoFrmInfo , 0 , sizeof(HVD_Frm_Information) );
2321 _HVD_Sub_Chip_Flush_Memory();
2322 return TRUE;
2323 }
2324
HAL_Sub_IsBBUEntryOdd(void)2325 MS_BOOL HAL_Sub_IsBBUEntryOdd(void)
2326 {
2327 MS_U32 preWptr = u32BBUWptr;
2328 if( preWptr == 0 )
2329 {
2330 preWptr = u32BBUEntryNum-1;
2331 }
2332 else
2333 {
2334 preWptr--;
2335 }
2336 return (MS_BOOL)(preWptr%2);
2337 }
2338
2339
HAL_HVD_Sub_UartSwitch2FW(MS_BOOL bEnable)2340 void HAL_HVD_Sub_UartSwitch2FW( MS_BOOL bEnable )
2341 {
2342 if( bEnable)
2343 {
2344 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
2345 }
2346 else
2347 {
2348 #if defined (__aeon__)
2349 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
2350 #else // defined (__mips__)
2351 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
2352 #endif
2353 }
2354 }
2355
HAL_HVD_Sub_GetData_Dbg(MS_U32 u32Addr)2356 MS_U32 HAL_HVD_Sub_GetData_Dbg( MS_U32 u32Addr )
2357 {
2358 return 0;
2359 }
2360
HAL_HVD_Sub_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)2361 void HAL_HVD_Sub_SetData_Dbg( MS_U32 u32Addr , MS_U32 u32Data)
2362 {
2363 return ;
2364 }
2365
HAL_HVD_Sub_GetCorretClock(MS_U16 u16Clock)2366 MS_U16 HAL_HVD_Sub_GetCorretClock(MS_U16 u16Clock)
2367 {
2368 //if( u16Clock == 0 )
2369 return 144;
2370 //if( )
2371 }
2372
HAL_HVD_Sub_UpdateESWptr_Fire(void)2373 void HAL_HVD_Sub_UpdateESWptr_Fire(void)
2374 {
2375 MS_BOOL bBitMIU1 = FALSE;
2376 MS_BOOL bCodeMIU1 = FALSE;
2377 if( pHVDCtrl_Hal->MemMap.u32CodeBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
2378 {
2379 bCodeMIU1=TRUE;
2380 }
2381 if( pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr >= pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr )
2382 {
2383 bBitMIU1=TRUE;
2384 }
2385 if( bBitMIU1 != bCodeMIU1 )
2386 {
2387 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
2388 BDMA_Result bdmaRlt;
2389 MS_U32 u32DstAdd=0 , u32SrcAdd=0 , u32tabsize=0;
2390 u32DstAdd = pHVDCtrl_Hal->MemMap.u32BitstreamBufAddr+pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
2391 u32SrcAdd = pHVDCtrl_Hal->MemMap.u32CodeBufAddr + HVD_BBU_DRAM_ST_ADDR;
2392 u32tabsize = u32BBUEntryNum << 3;
2393 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
2394 _HVD_Sub_Chip_Flush_Memory();
2395 bdmaRlt = HVD_dmacpy( u32DstAdd, u32SrcAdd, u32tabsize);
2396 if (E_BDMA_OK != bdmaRlt)
2397 {
2398 HVD_SUB_MSG_ERR("HVD Err:MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
2399 }
2400 #else
2401 MS_U32 u32DstAdd=0 , u32SrcAdd=0 , u32tabsize=0;
2402 u32DstAdd = pHVDCtrl_Hal->MemMap.u32BitstreamBufVAddr+pHVDCtrl_Hal->u32BBUTblInBitstreamBufAddr;
2403 u32SrcAdd = pHVDCtrl_Hal->MemMap.u32CodeBufVAddr + HVD_BBU_DRAM_ST_ADDR;
2404 u32tabsize = u32BBUEntryNum << 3;
2405 HVD_memcpy( u32DstAdd, u32SrcAdd, u32tabsize);
2406 _HVD_Sub_Chip_Flush_Memory();
2407 #endif
2408 }
2409 // HVD_SUB_MSG_INFO( "HVD Push packet fire:%lu st:%lx size:%lx BBU:%lu %lu\n", pHVDCtrl_Hal->u32BBUPacketCnt , pHVDCtrl_Hal->LastNal.u32NalAddr , pHVDCtrl_Hal->LastNal.u32NalSize , (MS_U32)_HAL_HVD_Sub_GetBBUReadptr() , u32BBUWptr );
2410 _HAL_HVD_Sub_SetBBUWriteptr( HVD_LWORD(u32BBUWptr) );
2411 pHVDCtrl_Hal->u32BBUWptr_Fired = u32BBUWptr;
2412 }
2413
HAL_HVD_Sub_MVD_PowerCtrl(MS_BOOL bEnable)2414 void HAL_HVD_Sub_MVD_PowerCtrl(MS_BOOL bEnable)
2415 {
2416 if( bEnable )
2417 {
2418 _HVD_WriteWordMask(REG_TOP_MVD, 0 , TOP_CKG_MHVD_DIS );
2419 _HVD_WriteWordMask(REG_TOP_MVD2, 0 , TOP_CKG_MHVD2_DIS );
2420 }
2421 else
2422 {
2423 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS , TOP_CKG_MHVD_DIS );
2424 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS , TOP_CKG_MHVD2_DIS );
2425 }
2426 }
2427
HAL_HVD_Sub_Dump_FW_Status(void)2428 void HAL_HVD_Sub_Dump_FW_Status(void)
2429 {
2430 MS_U32 tmp1=0;
2431 MS_U32 tmp2=0;
2432 _HVD_Sub_Chip_Read_Memory();
2433
2434 _HAL_HVD_Sub_MBoxRead( HAL_HVD_CMD_MBOX , &tmp1 );
2435 _HAL_HVD_Sub_MBoxRead( HAL_HVD_CMD_ARG_MBOX , &tmp2 );
2436 HVD_SUB_MSG_DEG("=====HVD Dump Systime:%lu FW Ver:%lx status: %lx Err Code: %lx PC: %lx =====\n" , HVD_GetSysTime_ms() , pHVDShareMem->u32FWVersionID , _HAL_HVD_Sub_GetFWState() , (MS_U32)pHVDShareMem->u16ErrCode , HAL_VPU_GetProgCnt() );
2437
2438 HVD_SUB_MSG_DEG("Time: STC:%lu DispT:%lu Dec:%lu PTS(skip,seek):%lu; Last Cmd:%lx _Arg:%lx _Rdy1:%lx _Rdy2:%lx\n" ,
2439 pHVDShareMem->u32DispSTC , pHVDShareMem->DispFrmInfo.u32TimeStamp , pHVDShareMem->DecoFrmInfo.u32TimeStamp , pHVDShareMem->u32CurrentPts,
2440 tmp1 , tmp2 , (MS_U32)_HAL_HVD_Sub_MBoxReady(HAL_HVD_CMD_MBOX) , (MS_U32)_HAL_HVD_Sub_MBoxReady(HAL_HVD_CMD_ARG_MBOX) );
2441
2442 HVD_SUB_MSG_DEG("Flag: InitDone:%d SPS_change:%d IFrm:%d 1stFrmRdy:%d Sync_Start:%d _Reach:%d \n" ,
2443 pHVDShareMem->bInitDone , _HAL_HVD_Sub_MBoxReady( HAL_HVD_REG_DISP_INFO_CHANGE ) , pHVDShareMem->bIsIFrmFound , pHVDShareMem->bIs1stFrameRdy ,
2444 pHVDShareMem->bIsSyncStart , pHVDShareMem->bIsSyncReach );
2445
2446 HVD_SUB_MSG_DEG("Queue: BBU:%lu Dec:%d Disp:%d ESR:%lu ESRfromFW:%lu ESW:%lu ESLevel:%lu\n" ,
2447 _HAL_HVD_Sub_GetBBUQNumb() , pHVDShareMem->u16DecQNumb , pHVDShareMem->u16DispQNumb ,
2448 _HAL_HVD_Sub_GetESReadPtr(TRUE), pHVDShareMem->u32ESReadPtr, _HAL_HVD_Sub_GetESWritePtr() , _HAL_HVD_Sub_GetESLevel() );
2449
2450 HVD_SUB_MSG_DEG("Counter: Dec:%lu Disp:%lu Err_Data:%lu _Dec:%lu Skip:%lu Drop:%lu Idle:%lu Main:%lu Vsync:%lu\n" ,
2451 pHVDShareMem->u32DecodeCnt , pHVDShareMem->u32DispCnt , pHVDShareMem->u32DataErrCnt ,
2452 pHVDShareMem->u32DecErrCnt , pHVDShareMem->u32SkipCnt , pHVDShareMem->u32DropCnt ,
2453 pHVDShareMem->u32VPUIdleCnt , pHVDShareMem->u32MainLoopCnt, pHVDShareMem->u32VsyncCnt);
2454 HVD_SUB_MSG_DEG("Mode: ShowErr:%d RepLastField:%d SyncOn:%d FileEnd:%d Skip:%d Drop:%d DispSpeed:%d FRC:%d BlueScreen:%d FreezeImg:%d 1Field:%d\n" ,
2455 pHVDShareMem->ModeStatus.bIsShowErrFrm , pHVDShareMem->ModeStatus.bIsRepeatLastField ,
2456 pHVDShareMem->ModeStatus.bIsSyncOn , pHVDShareMem->ModeStatus.bIsPlaybackFinish ,
2457 pHVDShareMem->ModeStatus.u8SkipMode , pHVDShareMem->ModeStatus.u8DropMode ,
2458 pHVDShareMem->ModeStatus.s8DisplaySpeed , pHVDShareMem->ModeStatus.u8FrcMode ,
2459 pHVDShareMem->ModeStatus.bIsBlueScreen , pHVDShareMem->ModeStatus.bIsFreezeImg ,
2460 pHVDShareMem->ModeStatus.bShowOneField);
2461 HVD_SUB_MSG_DEG("====================================\n" );
2462 }
2463
HAL_HVD_Sub_GetBBUEntry(MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)2464 void HAL_HVD_Sub_GetBBUEntry( MS_U32 u32Idx , MS_U32* u32NalOffset , MS_U32* u32NalSize )
2465 {
2466 MS_U8* addr=NULL;
2467 if( u32Idx >= u32BBUEntryNum )
2468 {
2469 return;
2470 }
2471 addr = (MS_U8*)((pHVDCtrl_Hal->MemMap.u32CodeBufVAddr)+ HVD_BBU_DRAM_ST_ADDR + (u32Idx<<3));
2472 *u32NalSize = *(addr +2) & 0x1f;
2473 *u32NalSize <<=8;
2474 *u32NalSize |= *(addr +1) & 0xff;
2475 *u32NalSize <<=8;
2476 *u32NalSize |= *(addr) & 0xff;
2477
2478 *u32NalOffset = ((MS_U32)(*(addr+2) & 0xe0)) >> 5;
2479 *u32NalOffset |= ((MS_U32)(*(addr+3) & 0xff)) << 3;
2480 *u32NalOffset |= ((MS_U32)(*(addr+4) & 0xff)) << 11;
2481 *u32NalOffset |= ((MS_U32)(*(addr+5) & 0xff)) << 19;
2482 }
2483
HAL_HVD_Sub_Dump_BBUs(MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)2484 void HAL_HVD_Sub_Dump_BBUs( MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry )
2485 {
2486 MS_U32 u32CurIdx=0;
2487 MS_BOOL bFinished=FALSE;
2488 MS_U32 u32NalOffset=0 ;
2489 MS_U32 u32NalSize=0;
2490 if( (u32StartIdx >= u32BBUEntryNum) || (u32EndIdx >= u32BBUEntryNum) )
2491 {
2492 return;
2493 }
2494 u32CurIdx = u32StartIdx;
2495 do
2496 {
2497 if( u32CurIdx == u32EndIdx )
2498 {
2499 bFinished =TRUE;
2500 }
2501 HAL_HVD_Sub_GetBBUEntry( u32CurIdx , &u32NalOffset , &u32NalSize );
2502 if( (bShowEmptyEntry ==FALSE) ||
2503 ( bShowEmptyEntry && (u32NalOffset ==0) && (u32NalSize ==0) ))
2504 {
2505 HVD_SUB_MSG_DEG( "HVD BBU Entry: Idx:%lu Offset:%lx Size:%lx\n", u32CurIdx , u32NalOffset , u32NalSize );
2506 }
2507 u32CurIdx++;
2508 if( u32CurIdx >= u32BBUEntryNum )
2509 {
2510 u32CurIdx%=u32BBUEntryNum;
2511 }
2512 }while(bFinished == TRUE);
2513 }
2514
2515 #endif //defined(SUPPORT_HVD_SUB)
2516