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Searched refs:MHz (Results 1 – 25 of 40) sorted by relevance

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/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.h19 #define MPLL_HZ (800 * MHz)
27 #define PPLL_HZ (200 * MHz)
28 #define GPLL_HZ (1188 * MHz)
29 #define ACLK_SECURE_FLASH_S_HZ (297 * MHz)
31 #define PCLK_SECURE_FLASH_S_HZ (99 * MHz)
32 #define PCLK_TOP_S_HZ (99 * MHz)
33 #define HCLK_VO_S_HZ (99 * MHz)
34 #define PCLK_DDR_HZ (99 * MHz)
35 #define PCLK_PDPMU_S_HZ (100 * MHz)
36 #define HCLK_PDPMU_S_HZ (100 * MHz)
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c1267 return 350 * MHz; in clk_scmi_aclk_secure_ns_get_rate()
1269 return 200 * MHz; in clk_scmi_aclk_secure_ns_get_rate()
1271 return 100 * MHz; in clk_scmi_aclk_secure_ns_get_rate()
1283 if (rate >= 350 * MHz) in clk_scmi_aclk_secure_ns_set_rate()
1285 else if (rate >= 200 * MHz) in clk_scmi_aclk_secure_ns_set_rate()
1287 else if (rate >= 100 * MHz) in clk_scmi_aclk_secure_ns_set_rate()
1311 return 150 * MHz; in clk_scmi_hclk_secure_ns_get_rate()
1313 return 100 * MHz; in clk_scmi_hclk_secure_ns_get_rate()
1315 return 50 * MHz; in clk_scmi_hclk_secure_ns_get_rate()
1327 if (rate >= 150 * MHz) in clk_scmi_hclk_secure_ns_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.h14 #define MHz (1000 * KHz) macro
15 #define GHz (1000 * MHz)
/rk3399_ARM-atf/docs/plat/st/
H A Dstm32mp1.rst27 - A Cortex-A7 @ 650 MHz
28 - C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
29 - D Cortex-A7 @ 900 MHz
30 - F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
36 - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN…
37 - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
38 - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
42 - A Basic + Cortex-A7 @ 650 MHz
43 - C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
44 - D Basic + Cortex-A7 @ 800 MHz
[all …]
/rk3399_ARM-atf/fdts/
H A Dstm32mp13-ddr3-1x4Gb-1066-binF.dtsi6 * 1x DDR3L 4Gb, 16-bit, 533MHz.
10 * freq 533MHz
19 #define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53"
H A Dstm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi6 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
10 * freq 533MHz
19 #define DDR_MEM_NAME "DDR3L 32bits 2x4Gb 533MHz"
H A Dstm32mp15xx-dhcor-som.dtsi264 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
277 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
290 /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ /* @TOCHECK */
291 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
H A Dstm32mp151a-prtt1a.dts147 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
160 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
173 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
H A Dstm32mp153c-lxa-fairytux2.dts63 /* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
73 /* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
H A Dstm32mp157c-lxa-tac.dts63 /* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
73 /* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
H A Dstm32mp15xx-osd32.dtsi261 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
274 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
287 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
H A Dcorstone700.dtsi58 /* Reference 24MHz clock x 2 */
66 /* UART clock - 32MHz */
H A Dstm32mp157a-avenger96.dts251 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
264 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
277 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
H A Dstm32mp15xx-dkx.dtsi240 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
253 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
266 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
H A Dstm32mp135f-dk.dts235 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
248 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */
261 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */
H A Dstm32mp157c-ed1.dts238 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
251 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
264 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
H A Dstm32mp15xx-dhcom-som.dtsi269 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
282 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
295 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
H A Dstm32mp157c-odyssey-som.dtsi283 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
296 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
309 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
H A Dstm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi8 * LPDDR4 1x16Gbits 1x32bits 1200MHz
11 * memclk 1200MHz (2x DFI clock)
22 #define DDR_MEM_NAME "LPDDR4 1x16Gbits 1x32bits 1200MHz"
H A Dstm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi8 * LPDDR4 1x32Gbits 1x32bits 1200MHz
11 * memclk 1200MHz (2x DFI clock)
22 #define DDR_MEM_NAME "LPDDR4 1x32Gbits 1x32bits 1200MHz"
H A Dstm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi8 * LPDDR4 2x16Gbits 1x32bits 1200MHz
11 * memclk 1200MHz (2x DFI clock)
22 #define DDR_MEM_NAME "LPDDR4 2x16Gbits 1x32bits 1200MHz"
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h36 #define MHz (1000 * KHz) macro
37 #define OSC_HZ (24 * MHz)
/rk3399_ARM-atf/docs/plat/marvell/armada/
H A Dbuild.rst233 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
234 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
235 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
236 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
241 - C080 or I080 - chip with 800 MHz CPU - use ``CLOCKSPRESET=CPU_800_DDR_800``
242 - C100 or I100 - chip with 1000 MHz CPU - use ``CLOCKSPRESET=CPU_1000_DDR_800``
243 - C120 - chip with 1200 MHz CPU - use ``CLOCKSPRESET=CPU_1200_DDR_750``
342 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h24 #define MHz (1000 * KHz) macro
25 #define OSC_HZ (24 * MHz)
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c160 PRATE(p_100m_24m) = { 100 * MHz, OSC_HZ };
161 PRATE(p_350m_175m_116m_24m) = { 350 * MHz, 175 * MHz, 116 * MHz, OSC_HZ };
162 PRATE(p_175m_116m_58m_24m) = { 175 * MHz, 116 * MHz, 58 * MHz, OSC_HZ };
163 PRATE(p_116m_58m_24m) = { 116 * MHz, 58 * MHz, OSC_HZ };

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