12831bc3aSCaesar Wang /* 2*2c4b0c05SJimmy Brisson * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. 32831bc3aSCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 52831bc3aSCaesar Wang */ 62831bc3aSCaesar Wang 7c3cf06f1SAntonio Nino Diaz #ifndef SUSPEND_H 8c3cf06f1SAntonio Nino Diaz #define SUSPEND_H 9c3cf06f1SAntonio Nino Diaz 10*2c4b0c05SJimmy Brisson #include <stdint.h> 112831bc3aSCaesar Wang #include <dram.h> 122831bc3aSCaesar Wang 132831bc3aSCaesar Wang #define KHz (1000) 142831bc3aSCaesar Wang #define MHz (1000 * KHz) 152831bc3aSCaesar Wang #define GHz (1000 * MHz) 162831bc3aSCaesar Wang 172831bc3aSCaesar Wang #define PI_CA_TRAINING (1 << 0) 182831bc3aSCaesar Wang #define PI_WRITE_LEVELING (1 << 1) 192831bc3aSCaesar Wang #define PI_READ_GATE_TRAINING (1 << 2) 202831bc3aSCaesar Wang #define PI_READ_LEVELING (1 << 3) 212831bc3aSCaesar Wang #define PI_WDQ_LEVELING (1 << 4) 222831bc3aSCaesar Wang #define PI_FULL_TRAINING (0xff) 232831bc3aSCaesar Wang 249aadf25cSLin Huang void dmc_suspend(void); 259aadf25cSLin Huang __pmusramfunc void dmc_resume(void); 26*2c4b0c05SJimmy Brisson extern __pmusramdata uint8_t pmu_enable_watchdog0; 272831bc3aSCaesar Wang 28c3cf06f1SAntonio Nino Diaz #endif /* SUSPEND_H */ 29