1 /* 2 * Copyright (c) 2024-2025, Rockchip Electronics Co., Ltd. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RK3568_CLOCK_H 8 #define RK3568_CLOCK_H 9 10 #define CRU_CLKGATE_CON0 0x300 11 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON0 + (i) * 4) 12 13 #define SCRU_GATE_CON00 0x0180 14 #define SCRU_GATE_CON01 0x0184 15 #define SCRU_GATE_CON02 0x0188 16 17 #define SGRF_SOC_CON2 0x0008 18 19 #define MPLL_HZ (800 * MHz) 20 #define MPLL_REFDIV 3 21 #define MPLL_FBDIV 200 22 #define MPLL_POSTDIV1 2 23 #define MPLL_POSTDIV2 1 24 #define MPLL_DSMPD 1 25 #define MPLL_FRAC 0 26 27 #define PPLL_HZ (200 * MHz) 28 #define GPLL_HZ (1188 * MHz) 29 #define ACLK_SECURE_FLASH_S_HZ (297 * MHz) 30 #define HCLK_SECURE_FLASH_S_HZ (148500000) 31 #define PCLK_SECURE_FLASH_S_HZ (99 * MHz) 32 #define PCLK_TOP_S_HZ (99 * MHz) 33 #define HCLK_VO_S_HZ (99 * MHz) 34 #define PCLK_DDR_HZ (99 * MHz) 35 #define PCLK_PDPMU_S_HZ (100 * MHz) 36 #define HCLK_PDPMU_S_HZ (100 * MHz) 37 38 #define RK3568_PLL_MODE_CON 0x20 39 #define RK3568_PLL_MODE_SHIFT 0 40 #define RK3568_PLL_MODE_MASK (0x3 << RK3568_PLL_MODE_SHIFT) 41 #define RK3568_PLL_MODE_SLOWMODE 0 42 #define RK3568_PLL_MODE_NORMAL 1 43 #define RK3568_PLLCON(i) (i * 0x4) 44 #define RK3568_PLLCON0_FBDIV_MASK 0xfff 45 #define RK3568_PLLCON0_FBDIV_SHIFT 0 46 #define RK3568_PLLCON0_POSTDIV1_MASK 0x7 47 #define RK3568_PLLCON0_POSTDIV1_SHIFT 12 48 #define RK3568_PLLCON1_REFDIV_MASK 0x3f 49 #define RK3568_PLLCON1_REFDIV_SHIFT 0 50 #define RK3568_PLLCON1_POSTDIV2_MASK 0x7 51 #define RK3568_PLLCON1_POSTDIV2_SHIFT 6 52 #define RK3568_PLLCON1_LOCK_STATUS (1 << 10) 53 #define RK3568_PLLCON1_DSMPD_MASK 0x1 54 #define RK3568_PLLCON1_DSMPD_SHIFT 12 55 #define RK3568_PLLCON1_PWRDOWN (1 << 13) 56 57 #define RK3568_CLK_SEL(x) ((x) * 0x4 + 0x100) 58 #define RK3568_PMUCLK_SEL(x) ((x) * 0x4 + 0x100) 59 60 #define PMUCRU_MODE_CON00 0x0080 61 #define PMUCRU_PMUCLKSEL_CON00 0x0100 62 #define PMUCRU_PMUCLKSEL_CON03 0x010c 63 #define PMUCRU_PMUGATE_CON01 0x0184 64 #define PMUCRU_CLKGATES_CON(i) (0x180 + (i) * 4) 65 #define PMUCRU_CLKGATES_CON_CNT 3 66 67 void pvtplls_suspend(void); 68 void pvtplls_resume(void); 69 void rockchip_clock_init(void); 70 71 #endif /* RK3568_CLOCK_H */ 72