1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 */ 5 6/* 7 * STM32MP25 LPDDR4 board configuration 8 * LPDDR4 2x16Gbits 1x32bits 1200MHz 9 * 10 * version 2 11 * memclk 1200MHz (2x DFI clock) 12 * width 32 32: full width / 16: half width 13 * ranks 2 Single or Dual rank 14 * density 16Gbits (per 16bit channel) 15 * Addressing RBC row/bank interleaving 16 * DBI-RD No Read DBI 17 * DBI-WR No Write DBI 18 * RPST 1.5 Read postamble (ck) 19 * Per_bank_ref Yes 20 */ 21 22#define DDR_MEM_NAME "LPDDR4 2x16Gbits 1x32bits 1200MHz" 23#define DDR_MEM_SPEED 1200000 24#define DDR_MEM_SIZE 0x100000000 25 26#define DDR_MSTR 0x03080020 27#define DDR_MRCTRL0 0x00000030 28#define DDR_MRCTRL1 0x00000000 29#define DDR_MRCTRL2 0x00000000 30#define DDR_DERATEEN 0x00000203 31#define DDR_DERATEINT 0x0124f800 32#define DDR_DERATECTL 0x00000000 33#define DDR_PWRCTL 0x00000100 34#define DDR_PWRTMG 0x00130001 35#define DDR_HWLPCTL 0x00000002 36#define DDR_RFSHCTL0 0x00210014 37#define DDR_RFSHCTL1 0x00000000 38#define DDR_RFSHCTL3 0x00000000 39#define DDR_RFSHTMG 0x81240072 40#define DDR_RFSHTMG1 0x00360000 41#define DDR_CRCPARCTL0 0x00000000 42#define DDR_CRCPARCTL1 0x00001000 43#define DDR_INIT0 0xc0020002 44#define DDR_INIT1 0x00010002 45#define DDR_INIT2 0x00000d00 46#define DDR_INIT3 0x00c40024 47#define DDR_INIT4 0x00310008 48#define DDR_INIT5 0x00100004 49#define DDR_INIT6 0x00660047 50#define DDR_INIT7 0x001d0047 51#define DDR_DIMMCTL 0x00000000 52#define DDR_RANKCTL 0x0000066f 53#define DDR_RANKCTL1 0x00000011 54#define DDR_DRAMTMG0 0x1718141a 55#define DDR_DRAMTMG1 0x00050524 56#define DDR_DRAMTMG2 0x060c1111 57#define DDR_DRAMTMG3 0x0090900c 58#define DDR_DRAMTMG4 0x0b04060b 59#define DDR_DRAMTMG5 0x02030909 60#define DDR_DRAMTMG6 0x02020007 61#define DDR_DRAMTMG7 0x00000302 62#define DDR_DRAMTMG8 0x03034405 63#define DDR_DRAMTMG9 0x0004040d 64#define DDR_DRAMTMG10 0x001c180a 65#define DDR_DRAMTMG11 0x440c021c 66#define DDR_DRAMTMG12 0x1a020010 67#define DDR_DRAMTMG13 0x0b100002 68#define DDR_DRAMTMG14 0x000000e9 69#define DDR_DRAMTMG15 0x00000000 70#define DDR_ZQCTL0 0x22580012 71#define DDR_ZQCTL1 0x01e0493e 72#define DDR_ZQCTL2 0x00000000 73#define DDR_DFITMG0 0x0395820a 74#define DDR_DFITMG1 0x000a0303 75#define DDR_DFILPCFG0 0x07f04111 76#define DDR_DFILPCFG1 0x000000f0 77#define DDR_DFIUPD0 0x4040000c 78#define DDR_DFIUPD1 0x0040007f 79#define DDR_DFIUPD2 0x00000000 80#define DDR_DFIMISC 0x00000041 81#define DDR_DFITMG2 0x0000150a 82#define DDR_DFITMG3 0x00000000 83#define DDR_DBICTL 0x00000001 84#define DDR_DFIPHYMSTR 0x80000001 85#define DDR_ADDRMAP0 0x00000004 86#define DDR_ADDRMAP1 0x00090909 87#define DDR_ADDRMAP2 0x00000000 88#define DDR_ADDRMAP3 0x00000000 89#define DDR_ADDRMAP4 0x00001f1f 90#define DDR_ADDRMAP5 0x080f0808 91#define DDR_ADDRMAP6 0x08080808 92#define DDR_ADDRMAP7 0x00000f08 93#define DDR_ADDRMAP8 0x00003f3f 94#define DDR_ADDRMAP9 0x08080808 95#define DDR_ADDRMAP10 0x08080808 96#define DDR_ADDRMAP11 0x00000008 97#define DDR_ODTCFG 0x04000400 98#define DDR_ODTMAP 0x00000000 99#define DDR_SCHED 0x80001b00 100#define DDR_SCHED1 0x00000000 101#define DDR_PERFHPR1 0x04000200 102#define DDR_PERFLPR1 0x08000080 103#define DDR_PERFWR1 0x08000400 104#define DDR_SCHED3 0x04040208 105#define DDR_SCHED4 0x08400810 106#define DDR_DBG0 0x00000000 107#define DDR_DBG1 0x00000000 108#define DDR_DBGCMD 0x00000000 109#define DDR_SWCTL 0x00000000 110#define DDR_SWCTLSTATIC 0x00000000 111#define DDR_POISONCFG 0x00000000 112#define DDR_PCCFG 0x00000000 113#define DDR_PCFGR_0 0x00704100 114#define DDR_PCFGW_0 0x00004100 115#define DDR_PCTRL_0 0x00000000 116#define DDR_PCFGQOS0_0 0x0021000c 117#define DDR_PCFGQOS1_0 0x01000080 118#define DDR_PCFGWQOS0_0 0x01100c07 119#define DDR_PCFGWQOS1_0 0x04000200 120#define DDR_PCFGR_1 0x00704100 121#define DDR_PCFGW_1 0x00004100 122#define DDR_PCTRL_1 0x00000000 123#define DDR_PCFGQOS0_1 0x00100007 124#define DDR_PCFGQOS1_1 0x01000080 125#define DDR_PCFGWQOS0_1 0x01100c07 126#define DDR_PCFGWQOS1_1 0x04000200 127#define DDR_UIB_DRAMTYPE 0x00000002 128#define DDR_UIB_DIMMTYPE 0x00000004 129#define DDR_UIB_LP4XMODE 0x00000000 130#define DDR_UIB_NUMDBYTE 0x00000004 131#define DDR_UIB_NUMACTIVEDBYTEDFI0 0x00000002 132#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002 133#define DDR_UIB_NUMANIB 0x00000008 134#define DDR_UIB_NUMRANK_DFI0 0x00000002 135#define DDR_UIB_NUMRANK_DFI1 0x00000002 136#define DDR_UIB_DRAMDATAWIDTH 0x00000010 137#define DDR_UIB_NUMPSTATES 0x00000001 138#define DDR_UIB_FREQUENCY_0 0x000004b0 139#define DDR_UIB_PLLBYPASS_0 0x00000000 140#define DDR_UIB_DFIFREQRATIO_0 0x00000001 141#define DDR_UIB_DFI1EXISTS 0x00000001 142#define DDR_UIB_TRAIN2D 0x00000000 143#define DDR_UIB_HARDMACROVER 0x00000003 144#define DDR_UIB_READDBIENABLE_0 0x00000000 145#define DDR_UIB_DFIMODE 0x00000000 146#define DDR_UIA_LP4RXPREAMBLEMODE_0 0x00000000 147#define DDR_UIA_LP4POSTAMBLEEXT_0 0x00000001 148#define DDR_UIA_D4RXPREAMBLELENGTH_0 0x00000001 149#define DDR_UIA_D4TXPREAMBLELENGTH_0 0x00000000 150#define DDR_UIA_EXTCALRESVAL 0x00000000 151#define DDR_UIA_IS2TTIMING_0 0x00000000 152#define DDR_UIA_ODTIMPEDANCE_0 0x00000035 153#define DDR_UIA_TXIMPEDANCE_0 0x00000028 154#define DDR_UIA_ATXIMPEDANCE 0x00000028 155#define DDR_UIA_MEMALERTEN 0x00000000 156#define DDR_UIA_MEMALERTPUIMP 0x00000000 157#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000 158#define DDR_UIA_MEMALERTSYNCBYPASS 0x00000000 159#define DDR_UIA_DISDYNADRTRI_0 0x00000001 160#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000a 161#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005 162#define DDR_UIA_WDQSEXT 0x00000001 163#define DDR_UIA_CALINTERVAL 0x00000009 164#define DDR_UIA_CALONCE 0x00000000 165#define DDR_UIA_LP4RL_0 0x00000004 166#define DDR_UIA_LP4WL_0 0x00000004 167#define DDR_UIA_LP4WLS_0 0x00000000 168#define DDR_UIA_LP4DBIRD_0 0x00000000 169#define DDR_UIA_LP4DBIWR_0 0x00000000 170#define DDR_UIA_LP4NWR_0 0x00000004 171#define DDR_UIA_LP4LOWPOWERDRV 0x00000000 172#define DDR_UIA_DRAMBYTESWAP 0x00000000 173#define DDR_UIA_RXENBACKOFF 0x00000000 174#define DDR_UIA_TRAINSEQUENCECTRL 0x00000000 175#define DDR_UIA_SNPSUMCTLOPT 0x00000000 176#define DDR_UIA_SNPSUMCTLF0RC5X_0 0x00000000 177#define DDR_UIA_TXSLEWRISEDQ_0 0x0000000f 178#define DDR_UIA_TXSLEWFALLDQ_0 0x0000000f 179#define DDR_UIA_TXSLEWRISEAC 0x0000000f 180#define DDR_UIA_TXSLEWFALLAC 0x0000000f 181#define DDR_UIA_DISABLERETRAINING 0x00000000 182#define DDR_UIA_DISABLEPHYUPDATE 0x00000001 183#define DDR_UIA_ENABLEHIGHCLKSKEWFIX 0x00000000 184#define DDR_UIA_DISABLEUNUSEDADDRLNS 0x00000001 185#define DDR_UIA_PHYINITSEQUENCENUM 0x00000000 186#define DDR_UIA_ENABLEDFICSPOLARITYFIX 0x00000000 187#define DDR_UIA_PHYVREF 0x00000014 188#define DDR_UIA_SEQUENCECTRL_0 0x0000131f 189#define DDR_UIM_MR0_0 0x00000000 190#define DDR_UIM_MR1_0 0x000000c4 191#define DDR_UIM_MR2_0 0x00000024 192#define DDR_UIM_MR3_0 0x00000031 193#define DDR_UIM_MR4_0 0x00000000 194#define DDR_UIM_MR5_0 0x00000000 195#define DDR_UIM_MR6_0 0x00000000 196#define DDR_UIM_MR11_0 0x00000066 197#define DDR_UIM_MR12_0 0x00000047 198#define DDR_UIM_MR13_0 0x00000008 199#define DDR_UIM_MR14_0 0x00000047 200#define DDR_UIM_MR22_0 0x0000001d 201#define DDR_UIS_SWIZZLE_0 0x00000003 202#define DDR_UIS_SWIZZLE_1 0x00000002 203#define DDR_UIS_SWIZZLE_2 0x00000000 204#define DDR_UIS_SWIZZLE_3 0x00000001 205#define DDR_UIS_SWIZZLE_4 0x00000006 206#define DDR_UIS_SWIZZLE_5 0x00000007 207#define DDR_UIS_SWIZZLE_6 0x00000005 208#define DDR_UIS_SWIZZLE_7 0x00000004 209#define DDR_UIS_SWIZZLE_8 0x00000005 210#define DDR_UIS_SWIZZLE_9 0x00000004 211#define DDR_UIS_SWIZZLE_10 0x00000007 212#define DDR_UIS_SWIZZLE_11 0x00000006 213#define DDR_UIS_SWIZZLE_12 0x00000000 214#define DDR_UIS_SWIZZLE_13 0x00000003 215#define DDR_UIS_SWIZZLE_14 0x00000002 216#define DDR_UIS_SWIZZLE_15 0x00000001 217#define DDR_UIS_SWIZZLE_16 0x00000005 218#define DDR_UIS_SWIZZLE_17 0x00000007 219#define DDR_UIS_SWIZZLE_18 0x00000006 220#define DDR_UIS_SWIZZLE_19 0x00000004 221#define DDR_UIS_SWIZZLE_20 0x00000000 222#define DDR_UIS_SWIZZLE_21 0x00000001 223#define DDR_UIS_SWIZZLE_22 0x00000003 224#define DDR_UIS_SWIZZLE_23 0x00000002 225#define DDR_UIS_SWIZZLE_24 0x00000007 226#define DDR_UIS_SWIZZLE_25 0x00000004 227#define DDR_UIS_SWIZZLE_26 0x00000005 228#define DDR_UIS_SWIZZLE_27 0x00000006 229#define DDR_UIS_SWIZZLE_28 0x00000002 230#define DDR_UIS_SWIZZLE_29 0x00000003 231#define DDR_UIS_SWIZZLE_30 0x00000001 232#define DDR_UIS_SWIZZLE_31 0x00000000 233#define DDR_UIS_SWIZZLE_32 0x00000000 234#define DDR_UIS_SWIZZLE_33 0x00000001 235#define DDR_UIS_SWIZZLE_34 0x00000002 236#define DDR_UIS_SWIZZLE_35 0x00000003 237#define DDR_UIS_SWIZZLE_36 0x00000004 238#define DDR_UIS_SWIZZLE_37 0x00000005 239#define DDR_UIS_SWIZZLE_38 0x00000000 240#define DDR_UIS_SWIZZLE_39 0x00000001 241#define DDR_UIS_SWIZZLE_40 0x00000002 242#define DDR_UIS_SWIZZLE_41 0x00000003 243#define DDR_UIS_SWIZZLE_42 0x00000004 244#define DDR_UIS_SWIZZLE_43 0x00000005 245 246 247#include "stm32mp25-ddr.dtsi" 248