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Searched refs:ID_AA64PFR0_ELX_MASK (Results 1 – 18 of 18) sorted by relevance

/rk3399_ARM-atf/plat/imx/common/
H A Dimx_bl31_common.c17 el_status &= ID_AA64PFR0_ELX_MASK; in plat_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplatform_common.c42 el_status &= ID_AA64PFR0_ELX_MASK; in socfpga_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/marvell/armada/common/aarch64/
H A Dmarvell_common.c116 el_status &= ID_AA64PFR0_ELX_MASK; in marvell_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl2_plat_setup.c69 el_status &= ID_AA64PFR0_ELX_MASK; in poplar_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_bl31_setup.c51 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/ti/common/
H A Dti_bl31_setup.c40 el_status &= ID_AA64PFR0_ELX_MASK; in k3_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c150 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c163 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c225 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_bl31_setup.c99 el_status &= ID_AA64PFR0_ELX_MASK; in sq_get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/
H A Dimx8mn_bl31_setup.c98 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_bl31_setup.c123 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/
H A Dimx8mm_bl31_setup.c127 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/include/arch/aarch64/
H A Darch.h224 #define ID_AA64PFR0_ELX_MASK ULL(0xf) macro
225 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK
226 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK
227 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK
228 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK
H A Darch_helpers.h851 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; in el_implemented()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/
H A Dimx8mp_bl31_setup.c129 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8qx/
H A Dimx8qx_bl31_setup.c104 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_bl31_setup.c83 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()