1 /*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <drivers/console.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <drivers/nxp/trdc/imx_trdc.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21
22 #include <imx8_lpuart.h>
23 #include <plat_common.h>
24 #include <plat_imx8.h>
25 #include <platform_def.h>
26
27 #define MAP_BL31_TOTAL \
28 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
29 #define MAP_BL31_RO \
30 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
31
32 static const mmap_region_t imx_mmap[] = {
33 AIPS1_MAP, AIPS2_MAP, AIPS4_MAP, GIC_MAP,
34 TRDC_A_MAP, TRDC_W_MAP, TRDC_M_MAP,
35 TRDC_N_MAP,
36 {0},
37 };
38
39 static entry_point_info_t bl32_image_ep_info;
40 static entry_point_info_t bl33_image_ep_info;
41
42 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)43 static uint32_t get_spsr_for_bl33_entry(void)
44 {
45 unsigned long el_status;
46 unsigned long mode;
47 uint32_t spsr;
48
49 /* figure out what mode we enter the non-secure world */
50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
51 el_status &= ID_AA64PFR0_ELX_MASK;
52
53 mode = (el_status) ? MODE_EL2 : MODE_EL1;
54
55 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
56 return spsr;
57 }
58
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)59 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
60 u_register_t arg2, u_register_t arg3)
61 {
62 static console_t console;
63
64 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
65 IMX_CONSOLE_BAUDRATE, &console);
66
67 /* This console is only used for boot stage */
68 console_set_scope(&console, CONSOLE_FLAG_BOOT);
69
70 /*
71 * tell BL3-1 where the non-secure software image is located
72 * and the entry state information.
73 */
74 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
75 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
76 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
77
78 #if defined(SPD_opteed)
79 /* Populate entry point information for BL32 */
80 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
81 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
82 bl32_image_ep_info.pc = BL32_BASE;
83 bl32_image_ep_info.spsr = 0;
84
85 /* Pass TEE base and size to bl33 */
86 bl33_image_ep_info.args.arg1 = BL32_BASE;
87 bl33_image_ep_info.args.arg2 = BL32_SIZE;
88
89 /* Make sure memory is clean */
90 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
91 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
92 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
93 #endif
94
95 imx_bl31_params_parse(arg0, OCRAM_BASE, OCRAM_SIZE,
96 &bl32_image_ep_info, &bl33_image_ep_info);
97 }
98
bl31_plat_arch_setup(void)99 void bl31_plat_arch_setup(void)
100 {
101 /* no coherence memory support on i.MX9 */
102 const mmap_region_t bl_regions[] = {
103 MAP_BL31_TOTAL,
104 MAP_BL31_RO,
105 };
106
107 /* Assign all the GPIO pins to non-secure world by default */
108 mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff);
109 mmio_write_32(GPIO2_BASE + 0x14, 0x3);
110 mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff);
111 mmio_write_32(GPIO2_BASE + 0x1c, 0x3);
112
113 mmio_write_32(GPIO3_BASE + 0x10, 0xffffffff);
114 mmio_write_32(GPIO3_BASE + 0x14, 0x3);
115 mmio_write_32(GPIO3_BASE + 0x18, 0xffffffff);
116 mmio_write_32(GPIO3_BASE + 0x1c, 0x3);
117
118 mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff);
119 mmio_write_32(GPIO4_BASE + 0x14, 0x3);
120 mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff);
121 mmio_write_32(GPIO4_BASE + 0x1c, 0x3);
122
123 mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff);
124 mmio_write_32(GPIO1_BASE + 0x14, 0x3);
125 mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff);
126 mmio_write_32(GPIO1_BASE + 0x1c, 0x3);
127
128 setup_page_tables(bl_regions, imx_mmap);
129 enable_mmu_el3(0);
130
131 /* trdc must be initialized */
132 trdc_config();
133 }
134
bl31_platform_setup(void)135 void bl31_platform_setup(void)
136 {
137 generic_delay_timer_init();
138
139 plat_gic_driver_init();
140 plat_gic_init();
141 }
142
bl31_plat_get_next_image_ep_info(unsigned int type)143 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
144 {
145 if (type == NON_SECURE) {
146 return &bl33_image_ep_info;
147 }
148
149 if (type == SECURE) {
150 return &bl32_image_ep_info;
151 }
152
153 return NULL;
154 }
155
plat_get_syscnt_freq2(void)156 unsigned int plat_get_syscnt_freq2(void)
157 {
158 return COUNTER_FREQUENCY;
159 }
160